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IFT 201: Unit 1 Lecture 1.3: Processor Architecture-3 Dr. Joseph M Kuitche Information Technology ASU Polytechnic School Review of previous lecture • Memory operands: load and store • Immediate operands (addi) are used to avoid load instruction on constants • Most architecture reserve a special register (usually $zero) for the constant 0 • Any integer quantity can be represented exactly using any base or radix • It is important to get proficient with base-2 or binary system • You can convert from decimal to binary using either subtraction or division methods • When assuming only positive numbers, we are said to be using unsigned representation • In signed representation, the MSB indicates the sign of the number: 1 for negative number, and 0 for positive numbers • Signed binary integers may be expressed in 3 different ways, of which 2’s complement representation is mostly used • To represent a number using more bits, just replicate the sign bit to the left Instructions are encoded in binary MIPS instructions Called machine code Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register numbers, … Regularity! Register numbers $t0 – $t7 are reg’s 8 – 15 $t8 – $t9 are reg’s 24 – 25 $s0 – $s7 are reg’s 16 – 23 §2.5 Representing Instructions in the Computer Representing Instructions Chapter 2 — Instructions: Language of the Computer — 3 MIPS Register Set FIGURE 2.1 MIPS assembly language revealed in this chapter. This information is also found in Column 1 of the MIPS Reference Data Card at the front of this book. Copyright © 2014 Elsevier Inc. All rights reserved. 5 MIPS INSTRUCTIONS FORMATS Arithmetic, Logic instructions Data transfer, addi, Branch instructions op R-format 6 bits rs rt rd shamt funct 5 bits 6 bits 5 bits 5 bits 5 bits op rs rt address I-format 6 bits Unconditional jump (jump) J-format instruction 5 bits 5 bits 16 bits op address 6 bits 26 bits op rs rt rd Operation code (opcode) 1st source register # 2nd source register # Destination register # shamt funct Shift amount Function 00000 for now code MIPS INSTRUCTIONS - Arithmetic Category Instruction Example Meaning Comments Arithmetic add add $at, $at, $v1 $at = $v0 + $v1 3 operands, data in registers subtract sub $at, $v0, $v1 $at = $v0 - $v1 3 operands, data in registers R-format op rs rt rd Field size 6 bits 5 bits 5 bits 5 bits Name Format shamt funct 5 bits 6 bits Example Arithmetic, logic instruction format Comments add R 0 2 3 1 0 32 add $at, $v0, $v1 sub R 0 2 3 1 0 34 sub $at, $v0, $v1 R-format Example (Arithm) op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add $t0, $s1, $s2 special $s1 $s2 $t0 0 add 0 17 18 8 0 32 000000 10001 10010 01000 00000 100000 000000100011001001000000001000002 = 0232402016 Chapter 2 — Instructions: Language of the Computer — 8 Activity 1.3.1 – Arithmetic Provide the MIPS assembly code, binary, and hexadecimal representations of the high-level instruction below. f = g + h – 5; Assume the variables f, g, and h are stored in registers $s0, $s1, and $s2 respectively Instructions for bitwise manipulation Operation C Java MIPS Shift left << << sll Shift right >> >>> srl Bitwise AND & & and, andi Bitwise OR | | or, ori Bitwise NOT ~ ~ nor §2.6 Logical Operations Logical Operations Useful for extracting and inserting groups of bits in a word Chapter 2 — Instructions: Language of the Computer — 10 Shift Operations rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits shamt: how many positions to shift Shift left logical op Shift left and fill with 0 bits 10011110 00111100 sll by i bits multiplies by 2i Shift right logical Shift right and fill with 0 bits 11100101 01110010 srl by i bits divides by 2i (unsigned only) AND Operations Useful to mask bits in a word Select some bits, clear others to 0 and $t0, $t1, $t2 $t2 0000 0000 0000 0000 0000 1101 1100 0000 $t1 0000 0000 0000 0000 0011 1100 0000 0000 $t0 0000 0000 0000 0000 0000 1100 0000 0000 Chapter 2 — Instructions: Language of the Computer — 12 OR Operations Useful to include bits in a word Set some bits to 1, leave others unchanged or $t0, $t1, $t2 $t2 0000 0000 0000 0000 0000 1101 1100 0000 $t1 0000 0000 0000 0000 0011 1100 0000 0000 $t0 0000 0000 0000 0000 0011 1101 1100 0000 Chapter 2 — Instructions: Language of the Computer — 13 NOT Operations Useful to invert bits in a word Change 0 to 1, and 1 to 0 MIPS has NOR 3-operand instruction a NOR b == NOT ( a OR b ) nor $t0, $t1, $zero Register 0: always read as zero $t1 0000 0000 0000 0000 0011 1100 0000 0000 $t0 1111 1111 1111 1111 1100 0011 1111 1111 Chapter 2 — Instructions: Language of the Computer — 14 Activity 1.3.2 – Logic Consider the execution of the program segment below (which consists of all instructions shown) for the MIPS architecture discussed in class. Initial values in registers pertinent to this problem are: $a0 = 4 and $t0 = 4032; the values in memory location 1232 is 4000; values are in decimal. Assuming the program segment is stored in memory starting at address (6,000)10 Give the machine-language equivalent for the instruction labeled “End”. INIT: Top: Sec: Nex: Key: End: lw beq addi beq lw add beq beq nand $t1, 1232($zero) $zero, $zero, Nex $s0, $t1, -8 $zero, $zero, End $s0, 0($t1) $t1, $t1, $a0 $t1, $t0, Sec $zero, $zero, Top $s0, $t1, $a0 MIPS INSTRUCTIONS – Data transfer & addi Category Instruction Example load word lw $at, 100($v0) Meaning Comments $at = Memory[$v0 + 100] Data from memory to register Memory[$a2+100] = $a0 Data from register to memory Data transfer store word sw $a0, 100($a2) I-format op rs rt address Field size 6 bits 5 bits 5 bits 16 bits Name Format Example Data transfer, branch format Comments lw I 35 2 1 100 lw $at, 100($v0) sw I 43 6 4 100 sw $a0, 100($a2) lw/sw Example op rs rt 6 bits 5 bits 5 bits constant or address offset 16 bits lw $t0, 1200($t1) lw $t1 $t0 offset 35 9 8 1200 100011 01001 01000 0000 0100 1011 0000 1000 1101 0010 1000 0000 0100 1011 00002 = 8D2804B016 addi Example op rs rt 6 bits 5 bits 5 bits constant or address offset 16 bits addi $s1, $s2, 100 addi $s2 $s1 constant 8 18 17 100 001000 Activity 1.3.4 – lw and addi Consider the execution of the program segment below (which consists of all instructions shown) for the MIPS architecture discussed in class. Initial values in registers pertinent to this problem are: $a0 = 4 and $t0 = 4032; the values in memory location 1232 is 4000; values are in decimal. Assuming the program segment is stored in memory starting at address (6,000)10 Give the machine-language equivalent for the instructions labeled “INIT” and “Sec”. INIT: Top: Sec: Nex: Key: End: lw beq addi beq lw add beq beq and $t1, 1232($zero) $zero, $zero, Nex $s0, $t1, -8 $zero, $zero, End $s0, 0($t1) $t1, $t1, $a0 $t1, $t0, Sec $zero, $zero, Top $s0, $t1, $a0 Branch to a labeled instruction if a condition is true beq rs, rt, L1 if (rs == rt) branch to instruction labeled L1; bne rs, rt, L1 Otherwise, continue sequentially §2.7 Instructions for Making Decisions Conditional Operations if (rs != rt) branch to instruction labeled L1; j L1 unconditional jump to instruction labeled L1 Chapter 2 — Instructions: Language of the Computer — 20 Compiling If Statements C code: if (i==j) f = g+h; else f = g-h; f, g, … in $s0, $s1, … Compiled MIPS code: bne add j Else: sub Exit: … $s3, $s4, Else $s0, $s1, $s2 Exit $s0, $s1, $s2 Assembler calculates addresses Chapter 2 — Instructions: Language of the Computer — 21 Activity 1.3.5 – Decision • For the following C statements, provide the MIPS Assembler using a minimal number of MIPS assembly instructions if (j==k) a = a + 1; a = b + c; More Conditional Operations Set result to 1 if a condition is true slt rd, rs, rt if (rs < rt) rd = 1; else rd = 0; slti rt, rs, constant Otherwise, set to 0 if (rs < constant) rt = 1; else rt = 0; Use in combination with beq, bne slt $t0, $s1, $s2 bne $t0, $zero, L # if ($s1 < $s2) # branch to L Chapter 2 — Instructions: Language of the Computer — 23 MIPS INSTRUCTIONS – Conditional branch Category Instruction Conditional branch Example Meaning branch on equal beq $8, $5, L set on less than slt $9, $6, $23 Field size 6 bits if ($8==$5) go to L Equal test and branch. Addr is relative to (PC+4) if ($6 < $9) $9=1 else $9 = 0 Compare less than; used with beq 5 bits 5 bits 16 bits address I-format op rs rt R-format op rs rt Name Format rd I 4 8 5 slt R 0 6 23 Data transfer, branch format Arithmetic, logic instruction format Comments beq $8, $5, addr x=[addr-(PC+4)]/4 x 9 Comments shamt funct Example beq Comments 0 42 set $9, $6, $23 MIPS INSTRUCTIONS – Unconditional jump Category Unconditional jump Instruction Example jump j 2500 go to 10000 Jump to target address jump register jr $ra go to address in $17 Jump to instruction pointed to by register 5 bits 16 bits Field size 6 bits J-format op R-format op 5 bits rs rt J jr R 0 17 rd Comments Comments Jump to target address address Name Format j Meaning shamt funct Arithmetic, logic instruction format Example Comments y j 10000 y= addr/4 0 0 0 8 jr $17 Activity 1.3.6 – Branch Consider the execution of the program segment below (which consists of all instructions shown) for the MIPS architecture discussed in class. Initial values in registers pertinent to this problem are: $a0 = 4 and $t0 = 4032; the values in memory location 1232 is 4000; values are in decimal. Assuming the program segment is stored in memory starting at address (6,000)10 Give the machine-language equivalent for the instruction labeled “Key”. INIT: Top: Sec: Nex: Key: End: lw beq addi beq lw add beq beq and $t1, 1232($zero) $zero, $zero, Nex $s0, $t1, -8 $zero, $zero, End $s0, 0($t1) $t1, $t1, $a0 $t1, $t0, Sec $zero, $zero, Top $s0, $t1, $a0 Compiling Loops • C while(j != 0) { /* loop body */ t = t + j--; } • Assembly beq $t0,$zero,done ; loop body add $s0, $s0, $t0 addi $t0, $t0, -1 done … Assuming $t0 = j $s0 = t Activity 1.3.7 – Loop • For the following C statements, provide the MIPS Assembler using a minimal number of MIPS assembly instructions while (a != 5) { t = a; a = b + a--; } Memory Layout Text: program code Static data: global variables Dynamic data: heap e.g., static variables in C, constant arrays and strings $gp initialized to address allowing ±offsets into this segment E.g., malloc in C, new in Java Stack: automatic storage Chapter 2 — Instructions: Language of the Computer — 29