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High Power Handling High Power Handling in UltraCMOS® Devices W hat is Maximum Linear Power? Peregrine defines its high power capability as the maximum input power that the device can handle without degrading the linearity of the product. In this definition the maximum input power level is not directly related to the 1dB compression point (P1dB), which is different from products designed on more traditional high power processes such as Gallium Arsenide (GaAs). Customers that are used to GaAs products expect to see linearity degradation occur at the P1dB and will specify the input power with margin to the P1dB in order to guarantee no reduction in the linearity performance. 0 46 45 45.1 45.2 45.3 45.4 45.5 45.6 45.7 -10 45.8 45 -20 44 -30 -40 43 -50 42 -60 -70 41 -80 40 -90 39 -100 Input Power (dBm) 2nd Harmonic 3rd Harmonic Pout Linear (Pout) Figure 1. Measured data on PE42850: Input Power vs. Output Power and 2nd & 3rd Harmonic Performance Output Power (dBm) Many of the high power applications are becoming more complex as end products need to support multiple frequency bands or signal paths. This added complexity means a small footprint is essential in order to fit the additional features into an acceptable volumetric size. For an UltraCMOS® product, no additional margin is required because the maximum input power occurs before the 1dB compression point and this means there is no linearity degradation at the maximum input. This concept is illustrated in Figure 1 which shows the performance of the PE42580 SP5T 42 dBm (CW) switch, the graph shows that the output power is not compressing but the harmonics start to increase at approximately 45.6 dBm of CW input power. Harmonics (dBc) The further a signal needs to travel the greater the required power. As the power increases so does the magnitude of the unwanted spurious signals. These spurious affect other systems; these can be complex communication scenarios where different systems can be located in frequency bands very close to each other, such as a simple garage door opener and cellular phone in close proximity. The spurious emissions are defined by the linearity of the device, so it is critical that the device can handle high power while simultaneously maintaining high linearity. Benefits of UltraCMOS The UltraCMOS process uses a high resistivity substrate that minimizes substrate losses and parasitic capacitances. This reduces insertion loss and dissipated power, which simplifies thermal management of the device. High power handling is realized with low voltage FET’s by using a stacking technique to create a “virtual high voltage CMOS FET” which is possible due to the high isolation of UltraCMOS. The high isolation is important in order for the voltage across the FET (VDS) to be equally distributed. The concept is illustrated in Figure 2. HaRP™ is a design technique that significantly improves the linearity of the FET across the designed operating range (frequency, power, supply voltage and temperature), when combined with the UltraCMOS technology it uniquely enables Peregrines products to be highly linear up to the maximum operating power the device is specified to operate at. This capability means that the products can be optimized for low insertion loss, isolation, and size. This enables improved system performance, long battery life and low total cost. High Voltage FET UltraCMOS® Stacked FET Bias Bias Bias Bias Figure 2. FET stacking is very efficient way to handle power using low voltage devices High Power RF Switches UltraCMOS® technology delivers unprecedented combination of 30W power handling and excellent linearity across the UHF/VHF through LTE frequency bands. The PE42820 and PE42821 are ideal for transmit/ receive, filter bank and antenna band switching applications in high-power RF systems such as wireless infrastructure devices and land-mobile-radio (LMR) for public safety and military environments. The PE42850 and PE42851 high power, high linearity switches utilize UltraCMOS and HaRP technologies. They are configurable as either SP3T or SP5T switches and support 42 dBm (17W) continuous wave or 45 dBm (32W) pulsed wave with harmonic performance as low as –90 dBc making them ideal for LMR applications. Exceptional power handling: 17 Watt CW Broad bandwidth: 30 MHz up to 2.7 GHz High linearity: 2fo/3fo as low as -90 dBc @ 1.15:1 VSWR Low power consumption of 130 µA @ 3.4 V © 2014 Peregrine Semiconductor Corporation. All rights reserved. The Peregrine name, logo and UltraCMOS are registered trademarks, and HaRP is a trademark of Peregrine Semiconductor Corporation. All other trademarks are the property of their respective owners. All information on these pages are subject to change without notice. Consult website for latest specifications. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com