Download High Performance in UltraCMOS® Devices

UltraCMOS® Excellence
High Performance
in UltraCMOS® Devices
W
hat is UltraCMOS® Technology?
UltraCMOS® Technology is a patented, advanced form
of Silicon-on-Insulator (SOI) process on a sapphire
substrate, enabling the combination of high-performance
RF, mixed-signal, passive elements, nonvolatile memory
and digital functions on a single device without blocking
capacitors. By utilizing a sapphire substrate, which is
a near-perfect insulator, UltraCMOS wafers enjoy low
defect density for simpler construction; dielectrically
isolated transistors for excellent power handling and
multiple thresholds; and inherent CMOS logic levels.
Further, SOS doesn’t have any body junctions, so the
only voltage variable capacitance is Cox. UltraCMOS
delivers the fundamental reliability, cost effectiveness,
high yields, scalability and monolithic integration of
standard CMOS, while achieving peak RF performance
traditionally expected from the more exotic process
technologies.
Process Technology Roadmaps
Peregrine’s combination of process architecture,
circuit designs, and device modeling has enabled an
accelerated technology roadmap. In 2013, Peregrine
announced the latest generation of UltraCMOS®
process technology—Semiconductor Technology
Platform 8 (STeP8). The on-resistance, off-capacitance
(RonCoff) product is a key figure of merit for RF
process technologies and important in the selection of
RFFE components.
Figure 2. UltraCMOS Technology Roadmap
Figure 1. UltraCMOS Wafers
Figure 2 shows how STeP8 technology shows a 36%
improvement in RonCoff performance over the previous
generation of UltraCMOS, STeP5—dramatically
improving the linearity, insertion loss, and isolation
capabilities of Peregrine’s RFIC products.
HaRP™ Technology
UltraCMOS® technology is composed of stack of
field effect transistors manufactured on an insulating
sapphire substrate, providing the ability to pass high
power RF signals. The HaRP invention allows for very
linear FETs which when stacked together provide for
excellent linear performance.
drift while maintaining high linearity and isolation
over an extended frequency range. In high-power
applications, HaRP technology-enhanced devices meet
critical harmonics specifications with improved power
handling. In addition, the HaRP-enabled high-throw,
high-power switches for quad-band GSM and GSM/
WCDMA handset applications have delivered a longawaited breakthrough in Intermodulation Distortion
(IMD) handling, a specification required by the 3GPP
standards body for GSM/WCDMA applications.
DuNE™ Digital Tuning Technology
Figure 3. FET stacking is very efficient way to handle
power using low voltage devices
Figure 3 shows an example of FET stacking in
an UltraCMOS device, while Figure 4 shows the
improvement in the noise floor measurment of a typical
switch or DSA product.
-80
Without HaRP™
-85
Third Order Product (dBm)
-90
OIP3 = +56
dBm
Vss = -2.8V DC (baseline measurement)
-95
25 dB Improvement
-100
-105
-110
Vss = 0 / -2.8V Pulsed
-115
-120
Noise Floor
-125
OIP3 = +69
dBm
HaRP™ Enabled
-130
0
250
500
750
1000
1250
1500
1750
2000
2250
2500
Time (µs)
Figure 4. STeP2 noise floor improvement results
Tx = 1950 MHz @ 20dBm
Blocker = 1760 MHz @ -15dBm
IMD3 Spec = <-105 dBm @ worst phase
By applying our proven, patented UltraCMOS process
and HaRP switch technologies, Peregrine developed
DuNE tuning technology, a circuit design technology
used to design the Digitally Tunable Capacitor (DTC),
and Tunable Control Switches (TCS) and Digitally
Tunable Network (DTN) products in development.
Supporting a wide range of tuning applications – from
cellular and mobile antennas to impedance matching,
output matching and filters – DuNE technologyenhanced products offer high power handling, excellent
linearity and straightforward RF integration.
Quality and Reliability
We are committed to providing high quality products
and services that meet or exceed our customers’
expectations. We have developed and implemented a
quality management system to create an organizational
environment designed to meet the highest level
of quality and reliability standards. Our quality
management system has been certified and maintained
to ISO 9001 standards since 2001. We achieved AS9100
Quality Management System Standards certification in
2003 to address the strict quality system requirements
of the aerospace industry. In early 2012, we further
improved the robustness of our quality management
system by receiving our ISO/TS 16949:2009
Quality Management System certification by the
automotive industry and in 2013 we released our first
product with AEC-Q100 Grade 2 Certification.
In demanding applications such as RF test equipment,
HaRP technology-enhanced ATE switches settle
very quickly, reducing gate lag and insertion loss
© 2013 Peregrine Semiconductor Corporation. All rights reserved. The Peregrine name, logo and UltraCMOS are registered trademarks, and HaRP and DuNE are
trademarks of Peregrine Semiconductor Corporation. All other trademarks are the property of their respective owners.
All information on these pages are subject to change without notice. Consult website for latest specifications.
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com