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Adaptive Techniques for Mitigating Spatio-Temporal Variability Shrikanth Ganapathy WP3 TRAMS Meeting, June 17th 2010, Barcelona ADAPTIVE BODY BIASING • The Body Voltage is varied to modulate threshold dynamically • Types – FBB and RBB • Bias Voltages – Latency Dependent (Leakage ??) • Bias Voltages are determined after manufacturing • Granularity -> One Bias Voltage for Entire Chip • Solution ?? – Dynamic Fine-Grain Body Biasing WP3 TRAMS Meeting, June 17th 2010, Barcelona DIFFERENCE BETWEEN ABB & DFGBB ABB DFGBB Determining Type of Body Bias Required Bias Voltage Set at Manufacturing Time Bias Voltage Tuned Dynamically at RunTime Applying Body Bias Either RBB or FBB Both RBB & FBB in Time-shared Manner Granularity of Bias Voltage One Bias Voltage for entire Chip One bias voltage for each circuit block Hardware Charge Pump (Very simple) No straight Forward Implementation • Hardware for DFGBB • Circuit to measure leakage/latency local to that circuit block (3T1D based) • Body bias generator that generates optimal body bias values based on the Measurement WP3 TRAMS Meeting, October 1st 2010, Barcelona CURRENT ABB PROPOSAL IN 6T • Transistors are designed with High Threshold (for Leakage reduction) • At run-time, FBB is applied to lower Threshold (to improve Speed) • Reduces Leakage by 67% Source – K.Roy Conventional VT=270mV FBSRAM VDD VPWELL 0V Active 0.5V Standby VT=350mV 32x32 Forward Body-Biased Sub-array M1 0.4V power supply M2 SUBSL .. M3 WL31 MA MP WL 0 … ... MN VPWELL .. 32 ... ... 32 ... ISSUES WITH THE EXISTING SYSTEM • As a result of Process Variations, Threshold can be much higher – The amount of FBB voltage needs to be revised • Leakage and Latency are largely dependent on Temperature – Sensors can be used • Temporal Variations of threshold are not taken into account WP3 TRAMS Meeting, June 17th 2010, Barcelona KEY REQUIREMENT OF DFGBB MECHANISM • Bias Voltages should account for Temporal Variations • Independent Biasing of Arrays • Even under FBB, the maximum (worst) leakage should be within 3σ • If using RBB, transition latency to ZBB/FBB should be minimum WP3 TRAMS Meeting, June 17th 2010, Barcelona Dynamic Fine-Grain Body Biasing WP3 TRAMS Meeting, October 1st 2010, Barcelona FORWARD BODY BIAS GENERATOR D E C O D E R 1 2 3 8 L V L S H F T R D E M U X R E S I S T O R To Array 1 T R E E To Array 2 To Array n Address • Resistor Tree generates the Bias Voltages • A Series of ‘n’ transistors divide the potential into ‘n’ intermediate points – If there are 20 transistors and VDDH – VDDL = 5V, then at the output of every transistor a voltage increase/decrease of 0.25V is observed • The DEMUX is used to select array based on input address WP3 TRAMS Meeting, June 17th 2010, Barcelona Latency Improvement 100 % Latency Improvement Minimum Average Maximum 80 60 40 20 0 0.1 0.2 0.3 0.4 Forwardy Body Bias Voltage (V) WP3 TRAMS Meeting, October 1st 2010, Barcelona Leakage Savings 70 Minimum Average Maximum % Energy Savings 60 50 40 30 20 10 0 - 0.1 - 0.4 - 0.2 - 0.5 - 0.3 Reverse Body Bias Voltage (V) • Savings Computed after Accounting for Energy Overhead due to BB Generators and FBB WP3 TRAMS Meeting, October 1st 2010, Barcelona PARAMETRIC YIELD • Latency Constraint - µ + (0.2σ, 0.4σ….,σ) • Leakage Constraint - µ + 3σ 110 Reject (Too Leaky) Reject (Too Slow) True Yield ( No Bias ) ( 0.4V Bias ) Fine Grain Biasing (Our proposal) % Number of Caches 100 90 80 70 60 50 Latency Constraint WP3 TRAMS Meeting, June 17th 2010, Barcelona LIMIT ON BIAS VOLTAGES 110 0.1V ZBB 0.3V 0.2V 0.4V % Number of Caches 100 95% 90 80 70 60 Latency Constraint WP3 TRAMS Meeting, June 17th 2010, Barcelona THANKS!!! WP3 TRAMS Meeting, June 17th 2010, Barcelona