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Navik Agrawal
Greg Kuperman
Paul Verzana
ESE 570 – Digital Circuits and VLSI Fundamentals
Final Design Project
5 May 2004
128 BYTE SRAM
Clock Speed @ 2 MHZ
8 Bit Parallel Read
8 Bit Parallel Write
Background and Theory
The storage of information is essential in any given computer manipulation. Storage
allows the computer to place information in a given spot for a given period of time.
Thus, after a given period of time, it is important that the bit of information retains its
proper value, especially when the storage cell is accessed again for retrieval of that bit.
This is the premise of Random Access Memory.
For our project, we designed a 128 Byte SRAM chip. In doing so, we gained valuable
insight into how storage and retrieval of information for RAM works.
System Specifications
Our SRAM chip is capable of storing 128 bytes of information.
Our design allows for an 8 bit parallel write operation. This allows for the writing of a
byte in one operation. Also, our SRAM can read out a byte at a time. With our row
decoder, information can be stored at any row address.
Our clock speed operates at approximately 2 MHz.
For writing data, a setup time of approximately 30 ns is necessary. This requirement
means that the data must be set to its proper value 30 ns prior to be written into the
respective row.
Our SRAM was designed to model the HC11 on-board RAM, which operates @ 2 MHz
and holds 256 bytes of information.
Architecture
The basic idea behind holding a bit of information requires a two inverter loop. This
forms the latch for storage.
With this design, the value will be retained as long as there is no fluctuation towards the
Vth, in which case could flip the stored value.
Now, by connecting two pass transistors to both sides of the latch, the stored value can be
shutoff from and open to the rest of the circuit. With the addition of the two pass
transistors, the basic SRAM cell is complete.
The two pass transistors connect the column bit lines to the latch. The circuit is shown
below.
The column bit lines are constantly being pulled up to VDD by way of two PMOS
transistors at the top of the line. The column bit lines are connected to all 128 latches per
column, and thus, their capacitance is typically very large. Having a large capacitance
allows the bit lines to discharge to ground and charge to Vdd depending on different
scenarios regarding the line. This is the premise behind the reading and the writing of the
SRAM chip.
To write a 1 into the latch, which is the value of V1, the DATA WRITE circuitry will
provide a path to ground for Vcn, thus discharging the Vcn column bit line. However,
the Vc line will stay charged at its value of Vdd. Thus, when the row select (RS) is
turned on, V1 will charge to Vc (5 V) and V2 will charge down to Vcn (0V). This
symmetric “push pull” system will lock a logic “1” into the latch.
To write a 0 into the latch, the DATA WRITE circuitry discharges Vc but maintains Vcn
at Vdd. Thus, when the row is selected, V1 will discharge to 0V and V2 will charge up
to 5 V. Hence, a logic “0” is latched into the cell.
This is the DATA WRITE circuitry.
Wn = WRITE
When Wn = 0, the circuit writes a value into the respective latch.
If DATA = 0, a 0 is written into the latch. Else if DATA = 1, a 1 is written into the latch.
Wn
DATA
Vc
Vcn
V1
0
0
1
0
1
X
1
0
1
0
1
1
1
0
V1
Here is how the DATA READ circuitry is interfaced with the columns. The two pass
transistors (indicated with the white arrows) provide paths to ground for both column bit
lines depending on the DATA READ circuit inputs.
During the write phase, Wn = 0, only one of these transistors will be closed.
During a read phase, Wn = 1, both of these transistors will be open so that the column bit
lines can precharge to VDD.
The READ operation works with a sense amplifier. Before the read operation is called,
both column bit lines are charged to VDD. Once the read operation is called, the pass
transistors between the column bit lines and the latch are closed. If a logic 1 is being
stored in the latch, V1 will be high and V2 will be 0. Thus, no significant current will
flow into V1 from Vc because both potentials are at VDD. However, a nonzero current
will flow from Vcn into V2 because of a difference in potentials. This change in current
decreases the voltage of the column bit line Vcn. The sense amplifier notices this
difference between Vc and Vcn and amplifies the difference to a logic 1.
If a logic 0 is being stored, the opposite happens and the sense amplifier amplifies the
difference to a logic 0.
Now, for instance, suppose a logic 1 is being stored in the latch and the read operation
has been initiated, column bit line Vcn begins to discharge into node V2.
It is important that the sense amplifier can read and amplify the difference between the
column bit line voltages before enough charge flows into V2 to increase V2 near the
threshold of the inverter. Failure to do so could flip the value of the latch. Thus,
transistor sizing is very crucial for this operation and shall be discussed later in the report.
This schematic shows a picture of an SRAM cell at the top. Below the cell is the sense
amplifier. To the left is the DATA WRITE circuitry, and to the right is the DATA OUT
circuitry. The DATA OUT circuitry consists of 2 inverters in cascade. The 2 inverters
provide a buffer output so that the data out cannot flip state with minor fluctuations.
With the Read and Write circuitry completely designed, the cells could be stacked on top
of each other. We created an array of 128 Rows and 8 columns, for a total of 128 bytes.
128 cells
Data Write Circuitry
Sense Amplifier
Data Out Circuitry
Here is a schematic of 1 column of 128 cells. To create the total array, 7 more columns
had to be connected and interfaced properly.
The other component to our SRAM circuit was the row decoder.
Design Considerations
The transistors in an SRAM circuit must be sized properly in order to maintain a properly
function RAM system. Some of the key things to focus on are to make sure that a DATA
WRITE operation is able to write the proper value into the latch, and a DATA READ
operation can retrieve the value without altering the value within the latch.
HSpice Simulation and Analysis of SRAM
To simulate our SRAM circuit, we needed to use HSPICE instead of Verilog because we
had to account for all the capacitances within the circuit. Because SRAM is an analog
circuit, timing issues were crucial. Setup times and hold times had to be properly
accounted for in our pulse voltage sources. By properly configuring the pulse voltage
sources for varying inputs, we were able to test multiple reads and writes in one
simulation.
We have setup a certain demonstration to prove our SRAM works.
In this demonstration, a byte of information will be written into Row 128. Another byte
of information will be written into Row 80, and finally, another byte of information will
be written into row 77. After these 3 bytes have been written, our circuit will read out the
values in the rows 128, 80, and 77. Once these rows have read out their values, 3
different bytes will be written into the rows overwriting the previous values. Once this
occurs, we shall read out the new values latched into each cell in the rows.
To summarize the operation, here is the following table.
NODE
DATA
BIT
a
D7
1
WRITE 1
0
X
READ
X
X
1
WRITE 1
0
X
READ
X
X
b
D6
c
D5
d
D4
e
D3
F
D2
g
D1
h
D0
0
0
0
X
X
X
0
1
1
X
X
X
1
1
1
X
X
X
0
0
0
X
X
X
0
1
0
X
X
X
0
0
0
X
X
X
0
0
0
X
X
X
1
1
0
X
X
X
0
1
1
X
X
X
0
0
0
X
X
X
1
1
1
X
X
X
1
1
0
X
X
X
0
0
1
X
X
X
1
1
0
X
X
X
The hexadecimal values are shown to point out that each byte is different.
Hex
Value
A2
B6
27
8B
CB
40
Row
#
127
80
77
127
80
77
127
80
77
127
80
77
Our decoder successfully turned on rows 128, 80, and 77 with every enable (“e”) pulse.
The enable pulses were spaced by 1.5 us. The spacing provided more than enough time
for the column bit lines to precharge back to VDD.
The “Wn” waveform shows when the circuit is writing and reading. When Wn is low the
circuit writes and when Wn is high the circuit reads.
All the column select pulses turned on each time the enable pulse turned on. This
allowed for 7 bit parallel write-in and read-out operations.
In the following HSpice output plots you will see 5 waveforms:
Wn (Determines Write or Read Operation)
RS# (Row Select)
Data Bit # (To be written into latch)
Voltage Row Node (a = 1st column, b = 2nd column…h = 8th column)
Data Out # (To be read out)
Each row has 8 voltage nodes, one for each cell from each of the 8 columns. Thus, there
are 8 plots per row. Altogether, there are 3 rows, making a total of 24 HSpice output
plots.
On the following page, a HSpice plot has been coded for reference. Please follow these
guidelines for all the other HSpice plots.
The impulse in the data out line is a characteristic of our schematic simulation. The
impulse will be discussed after the waveform plots.
Discussion of Impulses in Data Out Waveform
In our data output waves, when a logic 0 is being read, there always seems to be an
impulse in the first 30 ns of the READ operation. This impulse is a characteristic of the
column bit line capacitances. The impulse can only be shortened in time, but not
eliminated. The reason for this is because before every READ operation, the column bit
lines are charged up to VDD. When a READ operation is performed, initially both inputs
to the sense amplifier will be originally VDD. Only after a finite amount of time does one
column bit line show a reduction in charge. The time it takes for the column bit line to
reduce charge to a point where the sense amplifier can begin the proper amplification
corresponds to the impulse in the data output line.
For reading a logic 1, this impulse is not a problem because the correct amplification
reading is also a logic 1.
For faster SRAM chips, a stronger and better sense amplifier is needed. However, for our
speed requirements, the sense amplifier we used served well.
The following schematic portrays this discharging delay. Because we are essentially
using a cross coupled inverter for our sense amplifier, it is necessary for the column bit
line to discharge quite a bit to amplify the proper value. Hence, the impulse lasts for a
finite time of about 30 ns. After this time, the proper output value from the latch can be
read.
*** It is important to point out that these impulses disappear in our Post Layout
Simulations. This is due to the fact that the extracted layout accounts for all the
capacitances and properly adjusts the rise and fall times and delays within the circuit.
Transistor Schematics and Simulations
Layouts
Extracted Layouts
Layout Versus Schematic (For Entire Chip)
Post Layout Verification
To verify that layout worked properly, we ran a post layout simulation. To do this, we
created a symbol for the SRAM, and provided the voltage pulse sources.
The voltage sources were setup so that the same Data bits and Rows were input as were
for the schematic simulation.
The waveforms of the Data IN bits and Decoder Input bits are shown in the next 2 plots.
Notice that when the Enable pulse is high, the row is selected and the data bit is latched
into the system (if a Write operation is called).
The ultimate test was to make sure that the Post Layout Data Out waveforms matched
with that from the schematic simulation. Below are the Data Output waveforms from the
Schematic (top) and the Extracted Layout (bottom). They both match.
As can be seen, both plots were identical. Thus, our extracted layout design was a
success. It is even more impressive that data output waveforms for the extracted layout
eliminated the impulses. This is most likely due to the fact that all capacitances were
accounted for in the post layout simulation. Also, the extracted layout accounted for the
proper rise and fall times. Together, these effects enhanced our circuit’s performance
over the schematic simulations where we tried to account for the capacitances by
implicitly placing them in the circuit.
Conclusion