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2016 7th International Conference on Intelligent Systems, Modelling and Simulation Design of a New External Signal Controlled Polymorphic Gates Arwenjay Suarez, Harvey Oro, Limuel Peñaredonda, Rommel Anacan, Mark Nelson Pangilinan 1 Electronics Engineering Department, Technological Institute of the Philippines- Manila Manila, Philippines Abstract — As encountered in electronics systems, a conventional circuit fails in extreme conditions due to changes in transistors characteristics. Engineers are trying to deal with this problem for years until they come up with the adaptive electronics circuit they called polymorphic circuits. Polymorphic circuits are multifunctional in many ways. It has an ability to modify its system and vary with different conditions of environment; this depends on its components response. Its components are transistors combined to form a building block called polymorphic gates that changes its functionality as a response to controls such as temperature, power supply voltage (Vdd), light, an external signal, etc. For example, there is a logic gate that operates as AND when the temperature is 300 K and as OR when the temperature is 398 K. The reconfiguration of the polymorphic system does not depend on modifying the structure, instead on changing the functionality of individual building block. Considering the structure of the circuit, it always remains unchanged which makes it different from the classic reconfiguration process made with electronics system. This paper will design a building block polymorphic gates with the least transistors possible and applies it to a multifunctional two-bit Adder-Subtractor polymorphic circuit. After being applied to a polymorphic circuit, there will be comparisons of two technologies of IC design using Tanner EDA Tools and LT Spice IV. systems to be smaller. Resources are conserved with output still as good as in the traditional design. Another approach to multi-functionality is based on polytronics or polymorphic electronics. Polytronics refers to electronics with superimposed built-in functionality. Polytronic circuits have several intrinsically built-in functions, and can have the same output provide different functional responses under the control of specified parameters such, voltage, current, temperature, etc. These control parameters change the characteristic of a device depending on the design [1]. A. Polymorphic Gates Conventionally, an electronic circuit changes its functionality by changing its physical structure and/or by an instruction controlled by an external signal. Furthermore, a logic circuit changes its operation if and only if it is the logic gate itself physically changes its function. A polymorphic Circuit is a circuit that has other functions other than its main functions. Polymorphic Circuits changes its function to other through the variations of either the source voltage level, the circuit’s temperature, or an external signal. The circuit doesn’t have to be reconfigured to change its functionality. Keywords — Polymorphic Gates; Adaptive Electronics; Multifunctional Circuit I. TABLE I. PUBLISHED POLYMORPHIC GATES INTRODUCTION Continuous growth and development of electronics industries have been persisting over the past several years due to the fast-growing technology. Requirements to produce more efficient electronics increase exponentially and continually become more complex. Flexible and multifunctional systems resolve this problem because they aim to expand potential scope and utility of electronic devices thru simplified and minimal amount of components [2]. Multifunctional systems, on one hand, are traditionally designed by switching the output of single-function subsystems, each of independent stand-alone circuits. Meaning, when a command is given, or a condition is satisfied, a switching action occurs, routing the output of a subsystem which corresponds to the condition satisfied. For every function, one subsystem is physically required. On another hand, programmable and/or reconfigurable system design allows subsystems to be fewer and/or 2166-0670/16 $31.00 © 2016 IEEE DOI 10.1109/ISMS.2016.62 B. Paper Objectives The paper covers the simulation of polymorphic gates as a building block in designing a polymorphic circuit and involves the test of different technologies using Tanner EDA tools and LT SPICE IV, which are the tools available in the institution. The polymorphic gate which is designed through simulator uses external signal as its controller. The following specific objectives are: 413 x design a building block polymorphic gate with minimum transistors lesser than those which are already published; x apply it to a circuit which also performs polymorphic application to test its functionality; and x evaluate two softwares, Tanner EDA and LT SPICE IV as polymorphic circuit simulator. selected for reproduction and the process repeats. In most cases after some generations, an acceptable solution can be found. This paper uses the unconstrained evolution approach. This approach allows the free exploration of the search space, with no topological restrictions. The disadvantage is that it must all happen in simulation since there is no hardware implementation that would support it. Construction of a polymorphic circuit depends on how unconventional the connection of many transistors would be. For now, trial and error only are the basis to generate polymorphic circuit. For several trial and error process, unusual transistor connections and odd waveform during simulations, the needed output was acquired. This output is necessary to achieve and get all the desired outputs this project needs to have. This needed output is an AND/OR polymorphic circuit that has only four (4) transistor used in a slightly unconventional manner which is using a pair of PMOS and NMOS or simply CMOS. C. Project Scope and Limitations This paper involves the creation of polymorphic gates as a building block in creating a polymorphic circuit. Simulations using Tanner EDA tools software and LT SPICE IV will be conducted to test the effectiveness of the designed circuit. Since the process of creating polymorphic gates and the polymorphic circuit does not follow any formula or standard procedures, trial and error system for the design are made by researchers. It was only limited to running through simulations with applications of standards and will never be manufactured and tested in the actual environment due to a high cost of production. The said two software are both used in the industry and being updated yearly with standards of library files. II. PROJECT DEVELOPMENT A. Construction of the Polymorphic Gates Desired Output Logic gates serve as an elementary building block of a digital circuit. Often this can be found having two inputs and one output. With different system state and requirements, every terminal is in one of the two binary conditions low (0) or high (1), represented by different voltage levels. Figure 1: The Necessary Circuit (AND/OR) for the Desired Output This circuit behaves as NOR/AND Polymorphic circuit and uses the AND/OR building block. Using the OR function of the polymorphic circuit AND/OR and adding an inverter to negate the function OR to produce logic NOR function and a common mode that utilizes the control input which at positive or logic 0 value it gives the output of NOR and logic 0 value gives an AND function. B. Construction of a New Polymorphic Gate The polymorphic design approach depends mainly on changes in the device characteristics, generally on effects which are commonly negligible in a first order approximation by traditional design. The evolutionary method can do without design rules, as long as the circuit specifications are straightforward, which is the case in polymorphic circuits. Moreover, candidate circuits can be evaluated and ranked. An automated synthesis system based on evolutionary algorithms demand multiple requirements that the circuit needs to satisfy. Fundamentally, the objective of this approach is to find the best solution from a collection of the candidate solution. The candidate solutions, evaluated against a fitness function incorporating desired criteria, are determined by a generative process and these candidates compete against each other. The best candidates are then Figure 2. NOR/OR Proposed Polymorphic Gates 414 NOR/OR Polymorphic circuit uses the AND/OR circuit mentioned above. Using the OR function of the polymorphic circuit AND/OR and adding an inverter to negate the function OR to produce logic NOR function and a common mode that utilizes the control input which at positive or logic 1 value it gives the output of NOR and logic 1 value gives an OR function. Figure 5. AND/NAND Proposed Polymorphic Gates This polymorphic gate is different from the previous circuits since this uses only six (6) transistors connected in a different manner as of the previous three. This is generated in the trial and error experiments as when creating the building block AND/OR circuit. ( C. Spice Simulation - LTSPICE IV Selected circuits that are suited for the desired project are simulated. The spice simulation is done for the completion of the selected circuits’ construction. It is important for the completion of the selected circuits to set the required parameters of the circuit variables and select the appropriate options required for the simulations.For the supply voltage, a net label VDD with input as the port type is added and connected to the selected circuits. By adding a spice directive text and typing VDD VDD 0 DC 3.3 in the spice directive window, Vdd was set to 3.3 volts. Other net labels, A, B, and C with input as a port type are added and also connected to every candidate circuits. Different inputs variables are set to the specified card parameters by adding a spice directive text and typing Vb A GND DC 0 PULSE (0 3.3 0 1p 1p 20n 40n) for net label A, Vb B GND DC 0 PULSE (0 3.3 0 1p 1p 10n 20n) for net label B, and Vb C GND DC 0 PULSE (0 3.3 0 1p 1p 40n 80n) in the spice directive window. Summarization of the SPICE card parameters can be seen in Tables 3.6, 3.7, and 3.8. ( Polymorphic Gates Figure 3. NOR/AND Proposed This circuit behaves as NOR/AND Polymorphic circuit and uses the AND/OR building block. To use the OR function of the polymorphic circuit AND/OR and adding an inverter to negate the function OR to produce logic NOR function and a common mode that utilizes the control input which at positive or logic 0 value it gives the output of NOR and logic 0 value gives an AND function. TABLE II. INPUT A SPICE CARD PARAMETERS Figure 4. OR/NAND Proposed Polymorphic Gates The OR/NAND Polymorphic circuit was generated using the AND/OR circuit. To use the AND function of the polymorphic circuit AND/OR and adding an inverter to negate the function AND to produce logic NAND function and a common mode that utilizes the control input which at positive or logic 0 value it gives the output of NAND and logic 1 value gives an OR function. / 415 TABLE III. INPUT B SPICE CARD PARAMETERS TABLE 4. Input C SPICE Card Parameters Figure 8. NOR/AND Schematic using Tanner EDA S-Edit Tool Circuit analysis is done using transient analysis. Adding a spice directive text and typing .tran 0 80n 0 1p the specified SPICE card parameters are employed in the spice directive window. Summarization of the SPICE card parameters used in the transient analysis can be seen in the table. Figure 9. NOR/NAND Input-Output Waveforms from Tanner EDA S-Edit Tool TABLE V. SPICE CARD PARAMETERS FOR THE TRANSIENT ANALYSIS To see the desired output of each of the circuits, complete schematic designs of the selected circuits are simulated using LT Spice IV. As simulation completed, voltage waveforms of the different net labels are generated and displayed in a new window of the LT Spice workspace Figure 10. NOR/AND Schematic using Tanner EDA S-Edit Tool Figure 6. OR/NOR Schematic using Tanner EDA S-Edit Too Figure 11. OR/NAND Input-Output Waveforms from Tanner EDA S-Edit Tool Figure 7. OR/NOR Input-Output Waveforms from Tanner EDA SEdit Tool 416 TABLE VII. SPICE ANALYSIS: TRANSIENT/FOURIER ANALYSIS Figure 12. NAND/AND Schematic using Tanner EDA S-Edit Tool D. Application of the new Polymorphic Gates by Construction of Adder/Subtractor using Polymorphic Gates Figure 13. NAND/AND Input-Output Waveforms from Tanner EDA S-Edit Tool TABLE VI. TANNER EDA TOOL VOLTAGE PARAMETERS Figure 14. Adder/Subtractor Polymorphic Circuit using LTSPice Figure 14. Output Waveform of the Proposed Polymorphic Design III. SUMMARY AND CONCLUSION In the end, the project has established building blocks polymorphic gates AND/NAND, OR/NOR, NOR/AND NAND/OR. Those were all simulated in both software, LT SPICE IV and Tanner EDA considering the same parameters based on the availability of library files in each software. All polymorphic gates produced the desired output as expected though it does not follow the conventional CMOS design. Those proposed polymorphic gates are all evaluated to find the most efficient gate and put it on an application. The AND/NAND polymorphic gate is rated as the most efficient of the four proposed gates. Its functionality is 417 composed of basic and universal gates which are suitable for most design process. Since the project intends to create a polymorphic circuit, a two-bit Polymorphic Adder/Subtractor is designed using AND/NAND polymorphic gates. After simulation using the chosen effective software LT SPICE IV, the circuit is found to be a transformable Adder/Subtractor. It functions as an adder when the external signal is logic 1 and subtractor when the external signal is logic 0. ACKNOWLEDGEMENT The study is dedicated to our families who supported us financially to finish the task. Then next to God, who provide us with confidence and wisdom to complete the assigned task wholeheartedly. We would also like to thank the Electronics Engineering Department and the College of Engineering and Architecture of the Technological Institute of the Philippines-Manila who has pushed as and continually encouraged us to finish this study. To PCIEERD for the financial support and Dr. Marianne Jeannette Laxa, for editing the paper. REFERENCES [1] Stoica, A., et al, (2001). Polymorphic electronics. Proc. of Evolvable Systems: From Biology to Hardware Conference, Springer LNCS, Volume 2210 pp. 291–302. [2] Stoica, A., et al, (2004). Taking evolutionary circuit design from experimentation to implementation: Some useful techniques and a silicon demonstration, IEE Proc.-Comp. Digit. Tech., 151(4), 2004, pp.:295–300. [3] Stoica, A., et al, (2002). On polymorphic circuits and their design using evolutionary algorithms. Proc. of IASTED International Conference on Applied Informatics (AI2002). Insbruck, Austria [4] Sekanina, L., et al, (2006). Extrinsic and intrinsic evolution of multifunctional combinational modules. 2006 IEEE World Congress on Computational Intelligence, IEEE CIS, pp. 9676-9683. [5] Sekanina, L., et al, (2006). Novel logic circuits controlled by Vdd. 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Prague, CZ, IEEE CS, pp. 85-86. [6] Sekanina, L., et al, (2006). Evolution of multifunctional combinational modules controlled by the power supply voltage. 1st NASA/ESA Conference on Adaptive Hardware and Systems, Piscataway, US, IEEE CS, pp. 186- 193. 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