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UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on September 9, 2002 by Leland Chang ([email protected]) Borivoje Nikolic Homework #2 Solutions EECS 141 Due Tues., September 17th, 5pm @ 275 Cory Problem 1 – Extracting Parameters for the Unified Model From the figure above, determine the following parameters: VT0, , . VT0 This one should immediately signal you to look at curves that don’t have body-effect (VBS = 0V). Pick two points, each from different curves that satisfy the no-body-effect condition. Make sure they’re in the same operating region too! Point A B VGS 2.5V 2.0V VDS 2.5V 2.5V ID 5.15mA 2.94mA Operating Region saturation saturation Choose points with the same VDS to cancel out terms in the drain current equation: W (VGS , A 2 L 1 W k p (VGS , B 2 L 1 I D, A I D, B kp 5.15 2.94 2 VT 0 ) (1 V DS , A ) 2 VT 0 ) (1 V DS , B ) ( 2.5 VT 0 ) 2 ( 2.0 VT 0 ) 2 VT0 = 0.45V We can use the same methodology as above. This time, we want to keep V GS constant. Point A B VGS 2.5V 2.5V VDS 2.5V 2.0V W (VGS , A 2 L 1 W k p (VGS , B 2 L 1 I D, A I D, B kp 5.15 4.96 ID 5.15mA 4.96mA 2 VT ) (1 V DS , A ) 2 VT ) (1 V DS , B ) (1 2.5) (1 2.0 ) = 0.09V-1 Operating Region saturation saturation It shouldn’t be a surprise, but that leaves us to keep almost everything constant except for V SB. Point VSB VGS VDS ID A B 1.0V 0.0V 2.5V 2.5V 2.5V 2.5V 4.10mA 5.15mA W 2 (VGS , A VT ) (1 VDS , A ) 2 L 1 W 2 k p (VGS , B VT 0 ) (1 V DS , B ) 2 L 1 I D, A I D, B Operating Region saturation saturation kp 4.10 5.15 ( 2.5 VT ) 2 ( 2.5 0.45) 2 VT = 0.671V Now solve for using the following equation: VT VT 0 VSB 2 F 2 F 0.671 0.45 1 0.6 0.6 = 0.45V1/2 Problem 2 – Showing Off Your SPICE Prowess Using SPICE, generate the family of curves for a PMOS with the following parameters: W/L = 10.0u/0.25u Sweep VDS from -2.5V to 0V in 0.1V increments VGS = -0.5V, -1V, -1.5V, -1.5V, -2V, -2.5V VBS = 0V, 0.5V, 1V The following is a listing of one possible SPICE deck. Yours may be different, but the curves should be the same. The .ALTER statement is a little trick that that changes one parameter and re-runs the simulation. In addition, your plots may be the opposite in magnitude from my curves because SPICE has a weird convention of current directions. As long as the absolute magnitude of your numbers are correct, you should be in good shape! PS1 2B PMOS Curves .lib '/home/ff/ee141/MODELS/g25.mod' TT .param bias=0 .param supply=2.5 m1 d g s b pmos w=2.0u l=0.25u vgs g s 0 vds d s 0 vbs b s bias vb b 0 supply .dc vds -2.5 0 .1 vgs -2.5 -0.5 0.5 .plot LX4(M1) .option post=2 nomod .alter .param bias=0.5 .alter .param bias=1 .end The plots are located in a separate file on the web page. Problem 3 – Helping a Stanford Friend with Device Analysis a) Is the measured transistor a PMOS or an NMOS device? Explain your answer. This is a PMOS device. Negative gate-source, drain-source, currents should be your biggest hint. b) From the measurements above, help her to determine the following parameters for this device: VT0, , . This problem is solved using the EXACT same method as problem 1, except that the points are already chosen for you. I will skip the equations and state the answers. c) VT0 -0.6V – The device is in velocity saturation, so we use the velocity saturation equations of the unified model. The measurements you should use are 1 and 4. -0.55V1/2 – Use measurements 1 and 5 in the same fashion as problem 1. Use the velocity saturation equations from the unified model. -0.11V-1 – Use measurements 1 and 6 in the same fashion as problem 1. Use the velocity saturation equations from the unified model. Now, to really impress your friend, you use the values you obtained in part b) to figure out the operating region at each measured data point. Possible operating regions are: “linear”, “cutoff”, “saturation”, or “velocity saturation.” Measurement 1: velocity saturation Measurement 2: cutoff Measurement 3: saturation Measurement 4: velocity saturation Measurement 5: velocity saturation Measurement 6: velocity saturation Measurement 7: linear Problem 4 – First Order Delay Analysis a) Determine VOH and VOL. Explain your answer. VOH VOL b) 3000 2.5 V 3000 50 0V – Luckily for us, we at least have a pretty good pull down because the infinite resistance of the PMOS can be assumed to be an open circuit. 2.46V – Simple resistor divider circuit. VOH Calculate tpLH and tpHL to obtain the average propagation delay, tp. Propagation delay is ln(2)*RC or 0.69*RC tpLH 0.69ps – When the output goes from low to high, the output node charges via a resistive path. We can model this using a RC network, where R is the parallel combination of 50 and 3k, and C is the 20fF load. Note that the parallel combination method is just an approximation that works in this case because the PMOS “resistance” is much smaller than the 3k resistor. tpLH 41.4ps – We can treat it as if the transistor wasn’t even there. R=3k, C=20fF. tp 21.0ps – Not a very good average since they the low-high and high-low numbers are so far apart anyway. Problem 5 – Generating a Voltage Transfer Characteristic Draw the VTC for this circuit. Determine (or estimate, if necessary, from your VTC) the following parameters: VOH, VOL, VM We are given both load line plots for the active PMOS device and the non-linear device of the shaded box. How do we link the information provided by these curves to generate information about input and output voltages? First, we need to realize that the output voltage is related to the voltage drop across the PMOS source and drain. That is, Vout = Vshaded-box = VDD + VDS Similarly, Vin is related to the gate voltage applied to the PMOS: Vin = VDD + VGS We know the I-V characteristics of each device. We also know that the currents flowing through each device must be equal. Using the relation above, we can superimpose the two I-V plots together to end up with a plot of current vs. Vout. The intersections are the operating points of this circuit and will give us the input-output voltage relationships we need to build our VTC. Below is the revised, superimposed graph with the intersections labeled: 0.9 0.8 Vin = 0V 0.7 Current [mA] a) 0.6 0.5 Vin = 0.2V 0.4 B 0.3 0.2 Vin = 0.4V 0.1 D 0.0 E,F0.0 C Vin = 0.6V Vin = 0.7, 0.9 0.1 0.2 0.3 0.4 0.5 0.6 Vout [V] Point A B C D E F A Vin 0V 0.2V 0.4V 0.6V 0.7V 0.9V Vout 0.68V 0.64V 0.60V 0.07V 0V 0V 0.7 0.8 The resolution of our plot will not be as fine as we’d like, but you can see how if we had more points, the curve becomes more and more accurate Vout [V] 0.8 0.6 0.4 0.2 0.0 0.0 0.2 0.4 0.6 Vin [V] 0.8 Looking at the VTC, it is quite easy to determine what VOH, VOL, and VM are: b) VOH ~0.65V – When the carbon nanotube PMOS turns on, it tries to pull Vout high. At the same time, the shaded-box is trying to pull Vout low. Depending on the ratio of their effective resistances, VOL will change. This is something that will be discussed later on the semester when ratioed logic is covered in the course. VOL 0V – With the PMOS off, the shaded-box can pull Vout all the way down to zero. VM ~0.45V – Pretty close to the ideal symmetrical VTC for an inverter. Notice that this circuit is similar to a traditional CMOS inverter, except that the nonlinear device acts as an NMOS transistor (NMOS devices are hard to make using these carbon nanotubes). From the concepts discussed thus far in lecture and from the results of your VTC, what are the disadvantages of this method? Incomplete pull-up of the output node means we don’t get full rail-to-rail swing at the output. This also means that we have static power consumption because there is always a direct path from supply to ground when the PMOS transistor is on. For low power applications, we aim to minimize static power…and well, this is a disadvantage.