Download Modeling, Controller Design and Semiconductor

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Modeling, Controller Design and Semiconductor
Level Simulation of a Multilevel UPFC
Natália M.R. Santos1, J. Fernando Silva2, Vítor M.F. Pires1 and Rui M.G. Castro2
Abstract – The Unified Power Flow Controller (UPFC) is
nowadays the most versatile FACTS controller, offering a
unique combination of shunt and series compensations to
enable flexible control of power systems. In this paper, the
modeling, control design and detailed digital simulation of an
UPFC, in the MATLAB/SIMULINK environment is presented.
The model of the UPFC, connected to a power network through
a transmission line, is shown and used to design suitable
controllers. The two back-to-back connected multilevel
converters of the UPFC are simulated, considering the power
semiconductors switching, using standard SIMULINK blocks
to obtain faster simulations. The transmission line and the
power system are simulated using the Power System Blockset to
provide flexibility. The simulation interface of the two
multilevel converters with the Power System Blockset is
explained and simulation results shown and discussed.
Index Terms – FACTS, Unified Power Flow Controller
(UPFC), Multilevel Converter, Modeling, Control, Simulation.
I. INTRODUCTION
R
ecent economic, social and legislative developments
have demanded the review of traditional power
transmission systems and the creation of new concepts
and practices, allowing full use of existing power generation
and transmission facilities without compromising system
availability and security.
The need for new power flow controllers capable of
increasing transmission capacity and controlling power
flows through predefined transmission corridors will
certainly increase.
Due to the rapid development in the field of power
electronics, an increasing number of high power
semiconductor converters are used for transmission system
control and power flow optimization, under the heading of
Flexible AC Transmission Systems (FACTS) devices [1,2].
One particular concept, called the Unified Power Flow
Controller (UPFC), has been proposed by Gyugi in 1992 [2],
that combines the functions of some FACTS devices and is
capable to control a wide range of typical transmission
parameters, such as voltage, line impedance and phase angle.
The UPFC is perhaps the most versatile of the FACTS
controllers, offering a unique combination of shunt and
series compensations and guaranteeing flexible power
system control [3,4]. The flexible power flow control and
high dynamics can be achieved by applying electronic power
converters [5]. It is particularly beneficial to use power
converters based on full controlled switches, such as Gate
Turn Off thyristors (GTO) and the more recently available
high power Insulated Gate Bipolar Transistor (IGBT),
suitable to handle higher switching frequencies.
One solution to high power application is the use of
multilevel converters [6], which can operate at higher DC
voltages than two level converters, allowing higher power
handling capability with reduced harmonic distortion and
lower switching power losses.
Considering the increasing capabilities of MATLAB/
SIMULINK software package for simulation of dynamical
systems, the semiconductor level non-linear state-space
models, programmed in MATLAB/SIMULINK [7], can be
efficiently used to simulate power converters and to design
and study their controllers.
The last versions of MATLAB/SIMULINK include a
power systems toolbox (Power System Blockset – PSB), a
design tool [8] for modeling and simulating electric power
systems within the SIMULINK environment. This toolbox
features the most commonly used power devices (generators,
transformers, transmission lines, voltage sources) and
electrical models of power semiconductors, and allows the
simulation of power systems and power electronics.
The objective of this paper is to present the model of a
UPFC connected to a transmission line of a power network
(section II), active and reactive power control design
(section III) and detailed digital simulation (section IV) of
the UPFC in the MATLAB/SIMULINK environment. The
two back-to-back connected multilevel converters of the
UPFC are computer simulated, considering the switching
behavior of the power semiconductors, using standard
SIMULINK blocks to obtain faster simulations. The
multilevel converters use sliding mode internal loops to
control the input currents, output voltages and to equalize
the DC voltages of the DC link capacitors. The transmission
line and the power system are simulated using PSB to
provide flexibility in modifying the network topology. The
simulation interface of the two multilevel converters with
PSB is explained and simulation results are shown and
discussed.
II. SYSTEM CONFIGURATION AND MODELING
1)
Natália M.R. Santos and Vítor M.F. Pires are with the Department of
Electrical Engineering, Escola Superior de Tecnologia, Polytechnics
Institute of Setúbal, Setúbal, Portugal (e-mail: [email protected],
[email protected])
2)
J. Fernando Silva and Rui M.G. Castro are with Instituto Superior
Técnico, Technical University of Lisbon, at Centro de Automática da
Universidade Técnica de Lisboa and Electrical Energy Center, Lisboa,
Portugal, respectively (e-mail: [email protected], [email protected])
The basic operation principle of a UPFC can be found in
open literature [2]-[5]. The schematic diagram of the UPFC
basic structure consists of two switching power multilevel
converters connected back-to-back through a common DC
link (Fig. 1).
2
Bus 1
VvR
-
Tsh
XL
+ VcR -
IB1
+
The complex power equation can be written as follows:
Bus 2
I
Transmission
line
Ts
I vR
S = P0 + PcR + PvR + j (Q0 + QcR + QvR )
I B2
Shunt
converter
Series
converter
Udc
VvR
θvR
θcR
VcR
Fig. 1. UPFC schematic diagram
The series multilevel converter provides the main function
of the UPFC by injecting a voltage, with variable magnitude
(VcR) and phase angle (θcR), through a series connected
transformer (Ts). Because the transmission line current flows
through this voltage source, the series converter exchanges
active and reactive power with the transmission line through
the transformer (Ts).
The shunt multilevel converter (Fig. 1) is required to
supply or absorb the active power demanded by the series
converter at the common DC link, i.e., to keep constant the
DC link voltage. Furthermore, it can also generate or absorb
a reactive power, Q1, from bus 1 independently.
The equivalent circuit of a UPFC, used to derive the
steady-state model, is shown in Fig. 2, where the output of
the series converter is modeled as a voltage source
connected in series (VcR) and the input of the shunt converter
is a current source connected in parallel (IvR) with the line.
VcR
XcR
I
G1
V1 IvR
XL
I1
V0
V2
G2
Fig. 2. UPFC model equivalent circuit
I vR = I − I1
V + VcR − V2
I1 = 0
jX L
TRANSMISSION LINE
The series converter is controlled to generate the desired
magnitude of the voltage VcR (VcRref) and the desired phase
angle θcR (θcRref≈π/2), to maintain both active and reactive
power flows respectively, at the transmission line, close to
some pre-specified values.
The shunt converter supplies the active power demanded
by the series converter at the common DC link, maintaining
constant the common DC link voltage Udc. The shunt
converter can also regulate the reactive power injected at bus
1. Therefore, the UPFC operation tries to enforce the
reference variables: active and reactive power (Pcref, Qcref)
for the series converter and Iqref, Udcref, for the shunt
converter (Fig. 3).
+ VcR -
I
I vR
+
VvR
-
(2)
XL
2
P
Q
Series Converter
Shunt Converter
DC/AC
AC/DC
Udc
Shunt
Converter
Control
Series
Converter
Control
+
Iqref
V cR
θcR
Active Power
Loop Control
Udcref
Reactive Power
Loop Control
+
The complex voltage at nodes 1 and 2, V1 and V2, the
complex voltage source VcR and the complex current source
IvR, are given by (2), where δ is the phase angle between
voltages V1 and V2, θcR is the phase angle of VcR and θvR is
the phase angle of IvR.
V1 = V1 ; V2 = V2 e -jδ ; VcR = VcR e jθcR ; I vR = I vR e jθvR
III. ACTIVE AND REACTIVE POWER FLOW CONTROL IN THE
-
(1)
(3)
As can be seen from (3), in a transmission system without
UPFC (VcR=0, IvR=0), the active and reactive powers should
be P0 and Q0 defined in (3). The power transfer on the
transmission line can be fine tuned by adjusting the
magnitude of voltage (VcR) and the phase angle (θcR),
assuming θcR∈[-π/2, +π/2].
1
The main advantages of this topology are the separate
operation of both sources, as two independent reactive
power controllers, and the simultaneously compensation of
the active power.
Considering Fig. 2, the currents are given by (1) where XL
is the line reactance and XcR is the series reactance:
V − V0
I= 1
jX cR
V1V2
⎧
⎪P0 = X + X senδ
L
cR
⎪
⎪
⎛ 1
⎞ 2
XL
V1V2
⎟⎟V1 −
−
cosδ
⎪Q0 = ⎜⎜
+
(
)
X
X
X
X
X
cR
L
cR ⎠
L + X cR
⎝ cR
⎪
⎪
V1VcR
⎪PcR =
senθcR
X L + X cR
⎪
⎨
⎪Q = V1VcR cosθ
cR
⎪ cR X L + X cR
⎪
⎪P = X LV1I vR cosθ
vR
⎪ vR X + X
L
cR
⎪
X LV1 I vR
⎪
⎪QvR = − X + X senθvR
L
cR
⎩
P cref
+
Qcref
Fig. 3. UPFC control structure
A. Active Power Controller
To design the control system for active and reactive
power (series converter), the equivalent circuit of Fig. 2 was
considered [9]. For most practical systems, the power
converters can be assumed ideal, θcR≈π/2, and XcR, IvR can be
3
neglected when compared to XL and I1 respectively.
Therefore, from (3), the transfer function (∆PcR/∆VcR) of the
system, at a given operating point, can be written as in (4).
∆PcR =
V1
∆VcR
XL
(4)
Assuming low pass filter devices with time constant Tl to
measure P and Q, and considering (4), the block diagram of
the P control is represented in Fig. 4.
enforce P and Q. The shunt converter also uses sliding mode
control [10] in an internal loop to enforce the input currents
needed to supply the series converter needed power, to inject
reactive power into bus 1 and to equalize the DC voltages of
the DC link capacitors (Fig. 6).
To apply sliding mode control concepts and space
vectors, the three phase neutral point clamped three level
converter [11], shown in Fig. 6, is first modeled in the α,β
frame.
i0
∆PcR
Pref +
∆VcR
C(s)
-
V1
XL
1
1 + sTl
P
i
ic1
I1
I2
S11
I3
S31
S21
C1
UC1
S21
S22
S32
D11
D21
D31
Fig. 4. Block diagram of active power control
A PI (proportional-integral) controller C(s) is used to
provide zero steady state error, while ensuring stability. The
PI gains KpP and KiP, are calculated in (5) to obtain a first
order behavior with time constant τeq.
K pP =
X LTl
X
and K iP = L
τ eqV1
τ eqV1
B. Reactive Power Controller
The analysis of the reactive power controller assumes the
same conditions of the analysis of the active power
controller. Therefore, from (3) the transfer function
(∆QcR/∆θcR) is:
V 1 VcR
∆θ cR
XL
(6)
The block diagram of the reactive power control system
is presented in Fig. 5.
∆QcR
Qref +
-
C(s)
∆θcR
−
V1VcR
XL
um2
ic2
um3
UC2
1
1 + sTl
Q
Fig. 5. Block diagram of reactive power control
i’0
X LTl
XL
and K iQ = −
τ eqV1VcR
τ eqV1VcR
S23
S33
D12
D22
D32
S14
S24
S34
I’1
I’2
I’3
i1
Us2
i2
Us3
i3
AC
Load
i’
Fig. 6. Three phase, neutral point clamped, three level converter topology
The state variables of the multilevel converter (assuming
ideal components) are the AC currents i1,2,3 and DC voltages
Uc1 and Uc2. Depending on the sign of the current i0, the
converter operates in inverter mode (i0 >0, DC/AC
converter) or in rectifier mode (i0 <0, AC/DC converter)
[11].
The valid switch states of one leg can be ideally
represented by a switching variable γk(t) (8). Assuming
Uc1=Uc2=Udc/2, the possible leg output voltages (Udc/2; 0 ;
-Udc/2), Umk will be Umk=γk(t) Udc/2.
⎧ 1 if S k1 ∧ S k 2 are ON ∧
⎪
γ k = ⎨ 0 if S k 2 ∧ S k 3 are ON ∧
⎪
⎩− 1 if S k 3 ∧ S k 4 are ON ∧
S k 3 ∧ S k 4 are OFF
S k1 ∧ S k 4 are OFF
(8)
S k1 ∧ S k 2 are OFF
Then, the converter output Us voltages can be given by:
Similarly, the gains of the PI controller C(s) (Fig. 5), KpQ
and KiQ, are:
K pQ = −
S13
Us1
C2
(5)
The KpP and KiP values depend on the line reactance XL, on
the voltage V1 and on the time constants Tl and τeq.
∆QcR = −
um1
Udc
⎡ 2
⎢ 3
⎢ 1
U s = ⎢−
⎢ 3
⎢− 1
⎢⎣ 3
(7)
The PI controller for Q has gains dependent on XL, V1, Tl,
τeq and also on the series voltage source VcR.
IV. MULTILEVEL CONVERTER MODEL
The presented active and reactive control loops have been
used in one UPFC with two back-to-back connected
multilevel converters and the whole system simulated using
standard SIMULINK blocks. The used approach considers
the switching behavior of ideal power semiconductors, to
obtain accurate and fast simulations. The series converter
uses sliding mode to control the output voltages needed to
1
3
2
3
1
−
3
−
1⎤
− ⎥
3 ⎡γ 1 ⎤
1 ⎥ ⎢ ⎥ U dc
− ⎥ ⎢γ 2 ⎥
3⎥
2
2 ⎥ ⎣⎢γ 3 ⎦⎥
3 ⎥⎦
(9)
Using the Concordia transformation between fixed frames
1,2,3 and α,β , the state-space model in the α,β frame, is
obtained by [11]:
1
⎡
1 −
⎡U sα ⎤
2 ⎢
2
⎢
⎢U ⎥ =
3
3
⎣ sβ ⎦
⎢0
⎢⎣
2
where:
1 ⎤⎡Γ ⎤
1
2 ⎥ ⎢Γ ⎥ U dc
⎥⎢ 2 ⎥
3⎥
2
−
⎢⎣ Γ3 ⎥⎦
⎥
2 ⎦
−
(10)
4
(γ
1
(2γ1 − γ 2 − γ 3 )
3
1
Γ2 = (− γ1 + 2 γ 2 − γ 3 )
3
1
Γ3 = (− γ1 − γ 2 + 2 γ 3 )
3
Γ1 =
(11)
A. Output Voltage Control of Multilevel Series Converter
Sliding mode [11] is used to control the output voltage of
converter. The control objective imposes, in a certain
switching period T, that the output voltages (10) USα USβ
(denoted USα,β) average values must equal their reference
average values
1
T
T
∫
0
U s αref and U s βref (virtual flux control):
U Sα , β ref dt −
1
T
∫
T
0
U Sα ,β dt = eUsα ,β = 0
(12)
Therefore, the sliding surface S(eα,β,t), able to enforce the
control goal USα,β=USα,βref is (12), where kα,β is used to
impose the switching frequency:
S (eα ,β , t ) =
kα ,β
T
T
∫ (U α β
S ,
ref
− U Sα ,β )dt =0
(13)
0
Using sliding mode stability, the switching law must
select the proper values of USα,β [12] to verify the reaching
condition [10]:
S (eα ,β , t )S& (eα ,β , t ) < −ε S (eα ,β , t )
(14)
where ε is a sufficiently small error. The control action must
guarantee:
S& (eα , β , t ) = −ε sign (S (eα , β , t ))
(15)
which is ensured by choosing the appropriate vector from all
the available 27 possible output voltage vectors [11],
represented in the α,β frame. This can be done increasing
the USα,β voltage levels, if:
S (eα ,β , t ) > ε S (eα ,β , t ) and S& (eα ,β , t ) > 0
(16)
2
3
) (
B. Input Current Control of Multilevel Shunt Converter
In accordance with Fig. 3, the shunt converter operates
mostly in rectifier mode, supplying the active power for the
series converter, maintaining the common DC link voltage
constant Udc=Udcref, and regulating the reactive power Q1
injected at bus 1. As the input currents must exhibit a fast
dynamics compared to the slow dynamics of Udc, the two
tasks can be accomplished determining, respectively: 1) The
Idref current suitable to maintain constant the DC bus voltage
level (thus supplying the series converter needed active
power), using a PI controller with gains kpv and kiv
determined to obtain low sensitivity to current i0, being:
t
I dref = k pv (U dc − U dcref ) + kiv ∫ (U dc − U dcref ) dt
(17)
and 2) Iqref is Iqref = Q1/vd.
The sliding surfaces to control the iα,β currents, derived
from the Idref and Iqref using the Park transformation, are
[6,11]:
S (eiα ,β , t ) = k iα ,β (iα ,β ref − iα ,β )
e&Uc =
(
) (
)
iC1 iC 2
γ − γ i + γ − γ i2
−
=
C C
C
2
1 1
2
3
2
2
S (eiα ,β , t ) > ε S (eiα ,β , t ) and S& (eiα ,β , t ) > 0
2
3
) (
)
− γ 12 i1 + γ 32 − γ 22 i2 < 0 if S (eUc , t ) > 0
or ensuring
(24)
or decreased if:
S (eiα ,β , t ) < −ε S (eiα ,β , t ) and S& (eiα ,β , t ) < 0
(25)
The herein presented multilevel converters control loops,
together with the switching models (9) and (10) have been
modeled using standard SIMULINK [7] blocks to obtain
faster simulations.
In order to validate the proposed model of the UPFC, a
simplified test network (Fig. 7) was chosen, which consists
of two generators (315kV, 50Hz), one transmission line and
a load.
The inclusion of the UPFC in a network will not only
improve steady state load flow but also enhance network
transient stability and accuracy.
Transmission line: 315kV
G1
(19)
Ts
SG1=100MVA
Tsh
S Tsh=10MVA
315kV/1.5kV
choose a vector guarantying:
(γ
(23)
Efficient choice of space vectors [6,11] for the shunt
converter is similar to the series converter. The shunt
converter voltage level USα,β is increased if:
(18)
Since its derivative is:
2
3
(22)
0
V. CASE STUDY
This strategy is able to select one of the 19 distinct output
voltage vectors. The extra ones are load redundant but can
be used to equalize the capacitor voltages (so that
Uc1=Uc2=Udc/2) [6,11]. As Uc1 and Uc2 depend on the γk (t)
control variables, a suitable sliding surface is:
S (eUc , t ) = kU eUc (t ) = kU (U c1 − U c 2 ) = 0
(21)
These extra conditions enable the choice of most
redundant vectors.
or decreasing the USα,β voltage levels if:
S (eα ,β , t ) < −ε S (eα ,β , t ) and S& (eα ,β , t ) < 0
)
− γ 12 i1 + γ 32 − γ 22 i2 > 0 if S (eUc , t ) < 0
(20)
S Ts=3x4MVA
31.5kV/3.15kV
U dc
SG2=200MVA
PL =300MW
QL=120MVAr
UPFC
Fig. 7. Test network model
G2
ZL=3+j31.4Ω
5
The herein proposed simulation layout tries to minimize
the high simulation times needed by the two multilevel
converter power semiconductors of the UPFC, if represented
by MATLAB/SIMULINK [7] power system models using
the “Power System Blockset” PSB [8], a MATLAB/
SIMULINK toolbox that includes electrical models of power
devices. Instead, much faster SIMULINK blocks are used to
implement switching models (9), (10). Furthermore, to
enhance flexibility, the electrical network elements are
added as PSB models to easily enable the simulation of real
networks with UPFC, for transient studies. The test network
model as well as the interface between the UPFC (using
SIMULINK signals incompatible with the voltages and
currents of the AC network), are herein described.
The developed UPFC network interface is implemented
using PSB blocks and data found in Fig.7. Fig. 8 shows the
block diagram used in the MATLAB/SIMULINK program
to simulate the network presented in Fig. 7. Most blocks are
straightforward to implement except the series and shunt
branch blocks.
The Fig. 8 block diagram includes the Interface 1 that
corresponds to the series multilevel converter connection
with the transmission line, and the interface 2 corresponding
to the connection of the shunt multilevel converter with the
line transmission by transformer Ts.
The Interface 1 contains the subsystem “Series Branch”,
detailed in Fig. 9 (a). It includes three single-phase
transformers (31.5kV/3.15kV each) and three controllable
voltage sources to allow the connection of SIMULINK
outputs to electrical quantities. To inject the desired voltage
VcR to control the active and reactive power flow in the
transmission line, the voltage applied to the primary of the
series transformer should be the multilevel inverter output
voltage VcR1,2,3, which is imposed by a controllable voltage
source, dependent of voltage signals generated by UPFC.
Using this procedure, the interface between the UPFC
model developed in SIMULINK and the PSB “Series
Branch” features high flexibility and makes it possible to
adapt the model to most power systems.
The Interface 2 is represented by the shunt transformer,
the output filter (load) and the subsystem “Shunt Branch”, as
shown in Fig. 8. The shunt transformer is a three phase
linear transformer with YY connection (315kV/1.5kV,
10MVA), which is connected to the shunt converter input
filter, mainly inductive. Adequate parameters must be
Fig. 8. SIMULINK block diagram for network model
(a)
(b)
Fig. 9. (a) Series branch block diagram; (b) Shunt branch block diagram
chosen for this input filter in order to limit the input currents
ripple for the allowed switching frequency [12].
The subsystem “Shunt Branch” was implemented using
the block diagram of Fig. 9 (b), with three controllable
voltage sources depending on values of the shunt converter
output voltages.
VI. SIMULATION RESULTS
The digital simulation results of active and reactive power
flow control by the UPFC system are shown in Fig.10. Initial
values are Pref=30MW and Qref=12Mvar (per phase). Steps
are applied at t=0.25s to Pref=100MW and at t=0.6s to
Qref=40Mvar (per phase).
The Pref step disturbs the Q controller and the Qref step
disturbs the P controller (Fig.10), but active and reactive
power flows are quickly restored to their reference values,
with a response time near two time constants.
P[MW
], Q[MVAr]
12
Uc1,Uc2, Udc [V]
6
Pref
Qref
P
Q
11
10
9
5000
Uc1
Uc2
Udc
4500
4000
3500
8
7
3000
6
2500
5
4
2000
3
1500
2
1000
0.2
1
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
t [s]
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Fig. 13. Simulated results of the UPFC DC link capacitor voltage
1
t [s]
Fig. 10. Simulated results of active and reactive power (phase 1)
VII. CONCLUSIONS
Fig. 11 (a) presents the simulated results of rms series
voltage VcR in phase 1, while Fig. 11 (b) shows the rms shunt
converter current (phase 1). In both cases, after the cross
influence imposed by the Pref and Qref steps, the controller
response is satisfactory, stable and well balanced.
Fig. 12 (a) presents the simulated results of three-phase
series voltage VcR, with the active and reactive power at their
reference values, i.e., at the end of the simulation period of
1s, showing near sinusoidal balanced voltages. Furthermore,
as illustrated in Fig. 12 (b), the three phase current of the
shunt converter after the transient operation imposed by the
power references, is also near sinusoidal and well balanced.
1500
In this paper, the mathematical model of a UPFC has
been presented and control methods for both the series and
shunt converters have been described.
The dynamic modeling of a UPFC based on multilevel
converters topology using sliding mode control and space
vector modulation application was formulated.
The SIMULINK simulated UPFC, the PSB simulated
network and the interfaces between the two multilevel
converters and the AC network were designed in order to
provide accurate digital simulations, fast computational
times and to provide flexibility, being easy to add new AC
network devices.
The simulated results presented confirm that the
performance of the proposed UPFC controllers is
satisfactory for active and reactive power flow control.
Vcr1 [V]
ivr1 [A]
2500
2000
1000
1500
VIII. REFERENCES
1000
[1]
500
500
0
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
t [s]
0
0.2
1
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
t [s]
(a)
(b)
Fig. 11. (a) Simulated results of the UPFC in phase 1: (a) rms series
voltage; (b) rms shunt current
i123 [A]
Vcr [V]
2000
1500
4000
3000
1000
2000
500
1000
0
0
-500
-1000
-1000
-2000
-1500
-3000
-2000
0.8
0.9
1
t [s]
-4000
0.8
0.9
1
t [s]
(a)
(b)
Fig. 12. Simulated results of the UPFC in the primary side: (a) series
voltage; (b) shunt current
Fig. 13 shows the simulation results of the DC link
capacitor voltage Udc. It can be observed that the Udc voltage
response is satisfactory for the applied steps of active and
reactive power reference. After a small initial trouble the DC
link capacitor voltage follows its reference (UdcRef=4000V),
which implies that the shunt converter current responds
adequately to maintain a near constant DC link voltage.
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