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ENE 311
Lecture VII
p-n Junction
A p-n junction plays a major role in electronic devices. It is used in
rectification, switching, and etc. It is the simplest semiconductor devices and is a key
building block for other electronic, microwave, or photonic devices.
Basic fabrication steps
(a) A bare n-type Si wafer.
(b) An oxidized Si wafer by dry or wet oxidation.
(c) Application of resist.
(d) Resist exposure through the mask.
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(a) The wafer after the development. (b) The wafer after SiO2 removal.
(c) The final result after a complete lithography process.
(d) A p-n junction is formed in the diffusion or implantation process.
(e) The wafer after metalization. (f) A p-n junction after the compete process.
The figures above show the steps to fabricate a p-n junction. These steps include
oxidation, lithography, diffusion or ion implanation, and metallization.
Oxidation – This process is to make a high-quality silicon dioxide (SiO2) as an
insulator in various devices or a barrier to diffusion or implanation during fabrication
process. There are two methods to grow SiO2: dry and wet oxidation, using dry
oxygen and water vapor, respectively. Generally, dry oxidation is used to form thin
oxides because of its good Si-SiO2 interface characteristics, while wet oxidation is
used for forming thicker layers since its higher growth rate.
Lithography – This process is called photolithography used to delineate the
pattern of the p-n junction.
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Diffusion and Ion Implantation – This is used to put the impurity into the
semiconductor. For diffusion method, the semiconductor surface not protected by the
oxide is exposed to a high concentration of impurity. The impurity moves into the
crystal by solid-state diffusion. For the ion-implantation method, the impurity is
introduced into the semiconductor by accelerating the impurity ions to a high-energy
level and then implanting the ions in the semiconductor.
Metallization – This process is used to form ohmic contacts and
interconnections. After this process is done, the p-n junction is ready to use.
Thermal equilibrium condition
The most important characteristic of p-n junction is rectification. The figure
shows the I-V characteristic of a typical silicon p-n junction. The forward biased
voltage is normally less than 1 V and the current increases rapidly as the biased
voltage increases. As the reverse bias increases, the current is still small until a
breakdown voltage is reached, where the current suddenly increases.
Assume that both p- and n-type semiconductors are uniformly doped. When
both semiconductors are joined, carrier diffusion occurs. Electrons diffuse from n-side
toward p-side and holes diffuse from p-side toward n-side. As electrons leave the nside, they leave behind the positive donor ions (ND+) near the junction. In the same
way, some of negative acceptor ions (NA-) are left near the junction as holes move to
the n-side.
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(a) Uniformly doped p-type and n-type semiconductors before the junction is formed.
(b) The electric field in the depletion region and the energy band diagram of a p-n junction in
thermal equilibrium.
This forms 2 regions called “neutral” regions and “space-charge” region. The
space-charge region is also called “depletion region” due to the depletion of free
carriers. Carrier diffusion induces an internal electric field in the opposite direction to
free charge diffusion. Therefore, the electron diffusion current flows from left to right,
whereas the electron drift current flows from right to left.
At thermal equilibrium, the individual electron and hole current flowing across
the junction are identically zero. In the other words, the drift current cancels out
precisely the diffusion current. Therefore, the equilibrium is reached as EFn = EFp.
The space-charge density distribution and the electrostatic potential  are
given by Poisson’s equation as
d 2
dE

e

     ND  N A  p  n
2
dx
dx


(1)
Note: Assume that all donor and acceptor atoms are ionized.
Assume NA = 0 and n >> p for n-type neutral region and ND = 0 and p >> n for
p-type neutral region. The electrostatic potential  in of the n- and p-type with respect
to the Fermi level can be found with the help of n  ni exp  EF  Ei  / kT and
p  ni exp  Ei  EF  / kT as
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 n  EF  Ei  
kT  N D 
ln 

e  ni 
 p    Ei  EF   
kT  N A 
ln 

e  ni 
(2)
(3)
The total electrostatic potential difference between the p-side and the n-side
neutral region is called the “built-in potential” Vbi. It is written as
Vbi   n   p 
kT  N A N D 
ln 

e  ni2 
(4)
a) A p-n junction with abrupt doping changes at the metallurgical junction.
(b) Energy band diagram of an abrupt junction at thermal equilibrium.
(c) Space charge distribution.(d) Rectangular approximation of the space charge distribution.
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Ex. Calculate the built-in potential for a silicon p-n junction with NA = 1018 cm-3 and
ND = 1015 cm-3 at 300 K.
Soln
Depletion Region
The p-n junction may be classified into two classes depending on its impurity
distribution: the abrupt junction and linearly graded junction. An abrupt junction can
be seen in a p-n junction that is formed by shallow diffusion or low-energy ion
implantation. The impurity distribution in this case can be approximated by an abrupt
transition of doping concentration between the n- and the p-type regions. In the
linearly graded junction, the p-n junction may be formed by deep diffusions or highenergy ion implantations. That results in the impurity distribution varies linearly
across the junction.
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Abrupt junction
Consider an abrupt junction as in the figure above, equation (1) can be written
as
d 2 eN A

dx 2

2
d
eN
 D
2
dx

for -x p  x  0
(5)
for 0  x  xn
The charge conservation is expressed by the condition Q = 0 or
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N A x p  N D xn
(6)
To solve equation (5), we need to solve it separately for p- and n-type cases.
p-side:
Integrate eq.(4) once, we have
d

eN A x

dx
c
We know that E  
d
dx
 eN A x  c 

 

E p ( x)   
Apply boundary condition: E p ( x  x p )  0
 eN A (  x p ) 
 c  0



Ep (xp )   
c
eN A x p

Therefore, we have
E p ( x)  
eN A ( x  x p )
(7)

n-side:
Similarly, we can have
En ( x) 
eN D ( x  xn )

  Em 
eN D x
(8)

Let consider at x = 0
eN A x p
E p (0)  En (0)  


eN D ( xn )

 Em
(9)
We may relate this electric field E to the potential over the depletion region as
Vbi  
xn
0
 xp
 xp
 E ( x)dx    E ( x)dx
Vbi 
From (6), we have
xn
eN A x 2p
2
  E ( x)dx
p  side
eN D xn2

2
0
n  side
(10)
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N Axp
xn 
ND
N x
xp  D n
NA
(11)
Substitute (11) into (10), this yields
xp 
2Vbi
N
 D
e  N A  ND  N A
2Vbi
N
xn 
 A
e  N A  ND  ND
(12)
Hence, the space-charge layer width or depletion layer width can be written as
W  x p  xn 
2Vbi
e
 N  ND 
 A

 N AND 
(13)
Ex. Si p-n diode of NA = 5 x 1016 cm-3 and ND = 1015 cm-3. Calculate (a) built-in
voltage (b) depletion layer width (c) Em
Soln (a)
kT  N A N D 
ln 

e  ni2 


5  1016  1015 
 0.0259ln 
 1.45  1010 2 


Vbi 
Vbi  0.679 eV
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If one side has much higher impurity doping concentration than another, i.e.
NA >> ND or ND >> NA, then this is called “one-sided junction”.
(a) One-sided abrupt junction (with NA >> ND) in thermal equilibrium.
(b) Space charge distribution.
(c) Electric-field distribution.
(d) Potential distribution with distance, where Vbi is the built-in potential.
Consider case of p+-n junction as in the figure (NA >> ND),
W  xn 
2 Vbi
eN D
(14)
This means the width of space-charge layer in the heavily doped side is negligible,
and the depletion layer is essentially located in the n-side alone. Similarly, for n+-p
junction of ND >> NA
W  xp 
2Vbi
eN A
(15)
The electric-field distribution could be written as
E ( x )   Em 
eN B x

where NB = lightly doped bulk concentration (i.e., NB = ND for p+-n junction)
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The maximum electric field Em at x = 0 can be found as
Em 
eN BW

Therefore, the electric-field distribution E(x) can be re-written as
E ( x) 
eN B

 W  x    Em 1 

x

W
(16)
The potential distribution can be found from integrating (16) as
 ( x) 
Vbi x 
x
2 
W 
W
(17)
Ex. For a silicon one-sided abrupt junction with NA = 1019cm-3 and ND = 1016 cm-3,
calculate the depletion layer width and the maximum field at zero bias.
Soln
Linearly Graded Junction
In this case, the Possion equation (1) is expressed by
d 2
dE

e
W
W

    ax for -  x 
2
dx
dx


2
2
(18)
where a is the impurity gradient in cm-4 and W is the depletion-layer width
By integrating (18) with the boundary conditions that the electric-field is zero
at W/2, E(x) can be found as
2
ea  W / 2   x 
E ( x)   

 
2

2
(19)
The maximum field Em at x = 0 is
eaW 2
Em 
8
(20)
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The built-in potential is given by
eaW 3
12
(21)
kT   aW / 2  aW / 2   2kT  aW 
ln 
ln 


e 
ni2
e

 2ni 
(22)
Vbi 
and
Vbi 
Linearly graded junction in thermal equilibrium.
(a) Impurity distribution.
(b) Electric-field distribution.
(c) Potential distribution with distance.
(d) Energy band diagram.
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Ex. For a silicon linearly graded junction with an impurity gradient of 1020 cm-4, the
depletion-layer width is 0.5 μm. Calculate the maximum field and built-in voltage.
Soln
Note: Practically, the Vbi is smaller than that calculated from (22) by about 0.05 to 0.1
V.