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Problem 1 - An introductory adder problem
a) Show that the expression for S in Eq. 11.6 is equivalent to the one in Eq. 11.1
S  ABC i  AB  BC i  AC i A  B  C i  


 ABC i  AB C i A  BA  B  C i   ABC i  A  B  C i  A B A  B  C i  


 ABC i  A C i  A B  B C i  A B A  B  C i  
 ABC i  ABC i  A BC i  A BC i  A BC i 
 ABC i  ABC i  A BC i  A BC i
b) Size the transistors in Fig 11.4 such that each stage (carry and sum) has the same pull-up/pull-down
strength as a minimum-sized 2/1 inverter. Find the logical effort for each input (consider the carry and sum
stages separately).
5 5
6.7
6.7
6.7
6.7
5
2.86
3.3
6.7
5
6.7
2
3
2 2
2
2
2
2
2
2
2
1
2 3
3
1
Logical effort:
Carry
A
B
Ci
4.67
4.67
1.78
Sum
A
B
Ci
6.11
6.11
6.11
c) Now consider the mirror adder in Fig. 11.6. Make sure that you understand what it does. Size the
transistors such that each stage (carry and sum) has the same pull-up/pull-down strength as a
minimum-sized 2/1 inverter. Find the logical effort for each input (consider the carry and sum stages
separately).
6
4
4
4
4
4
6
4
2
4
4
4
6
2
2
2
3
2
2 3
2
2
2
3
Logical effort:
Carry
A
B
Ci
12/3
12/3
6/3
Sum
A
B
Ci
15/3
15/3
15/3
We can see that the mirror adder has lower logical effort for all inputs except Co. However we should not
forget the extra loading and delay of the additional inverters in the complementary architecture. When those
are included the mirror adder wins overall.
Problem 2 – Conditional Sum Adder
Here is a neat adder structure called the conditional sum adder. Shown below is a 4-bit version of the circuit.
Note that in the diagram, multiplexors are represented by switch-controlled arrows.
Using a pass-transistor implementation, the circuit schematic for each adder cell can be:
a) Derive Boolean equations for the four outputs of the one-bit conditional adder cell
S0 = A  B C0 = AB
S1 = (A  B)’
C1 = A + B
b) Derive an expression for the propagation delay of the adder as a function of the number of Bits, N.
Assume that the delay through each conditional cell is tcell and that the delay of a MUX is tMUX.
Basically, we need an additional level of multiplexors every time we double the number of bits.
So…in the worst-case critical path, we must pass the carry-out from the least-significant bit all the
way to the most-significant bit, which means that we must go through each MUX level. # of
levels = log2 N. On top of that, we always need to calculate C0/C1 and S0/S1, so we have one
cell delay.
Delay = tcell + log2 N tMUX
Problem 3 – Timing & Race Conditions
The following circuit consists of a source portion, which adds the outputs of two registers R1 & R2
and a destination portion, which stores the sum in R3. The connections between the source and
the destination are made by an automatic router, which creates wires with an average length of
1mm and containing an average of 10 contact holes in series. This leads to a resistance of about
200  and capacitance of about 100 fF for each wire.
A clock driver buffers the clock signal at the source and is routed by the same tool to the
destination, where it connects to R3 and two other registers (R4 & R5) which happen to be close
by. Each register presents a load of 300 fF to the clock driver.
Assume the following timing values for the logic: tcarry = 250 ps, tsum = 300 ps (including the wire
load), tsetup = 150 ps, thold = 100 ps, tclk-Q = 50 ps.
a) Does this circuit have a race problem?
What is the minimum clock period?
First, we need to find the skew between the source register clock (’) and the destination register’s clock (”).
We can do this with a 2 model of the wire and the Elmore delay model.
150 
600 fF
’
200 
50 fF
50 fF
”
900 fF
t’ = 0.69 (150) (650 f) = 67 ps
t” = 0.69 [ (150)(650 f) + (150+200)(950) ] = 297 ps
 = t” - t’ = 229 ps (eq. 9.1)
Next, we check the race condition to see if the circuit will work properly. Note that the minimum logic delay
is a single sum.
thold +   tclk-Q + tsum
(eq. 10.4)
100 + 229  300 + 50
329  350
TRUE (barely)... Thus, this circuit has no race problem
Lastly, we find the minimum clock period. Note that the maximum logic delay is a single sum plus the delay
of the carry chain.
T  tclk-Q + (31 tcarry + tsum) + tsetup -  (eq 10.3)
T  50 + (31)(250) + 300 – 230 + 150
T  8.02 ns
b) What if you removed R4 and R5? Would there be a race problem? What would the new
minimum clock period be?
Identical to part a), except the capacitance at ” is much less.
150 
650 fF
’
200 
”
350 fF
t’ = 0.69 (150) (650 f) = 67 ps
t” = 0.69 [ (150)(650 f) + (150+200)(350) ] = 152 ps
 = t” - t’ = 85 ps
thold +   tclk-Q + tsum
100 + 85  300 + 50
185  350
TRUE ... Thus, no race problem
Note, however, that this circuit has a much better margin of
error than the one from part (a).
T  tclk-Q + 31 tcarry + tsum-  + tsetup
T  50 + (31)(250) + 300 – 85 + 150
T  8.17 ns
Note that the minimum cycle time is longer with the smaller skew.
c) What if the driver were placed at the destination (with R3,R4 & R5)? Would there be a race
problem? What would the new minimum clock period be?
Identical to (a), except that the clock in driven in the other direction.
’
650 fF
200 
”
150 
950 fF
t” = 0.69 (150) (950 f) = 98 ps
t’ = 0.69 [ (150)(950 f) + (150+200)(650) ] = 255 ps
 = t” - t’ = -157 ps
thold +   tclk-Q + tsum
100 - 157  300 + 50
-57  350
TRUE ... Thus, no race problem
Note that this circuit has the best margin of error over all
three cases.
T  tclk-Q + 31 tcarry + tsum-  + tsetup
T  50 + (31)(250) + 300 + 157 + 150
T  8.41 ns
Note that the minimum cycle time is the longest over all three cases.
Note: it is acceptable to use a T model instead of the  model. For parts a and b, the  model delays the first
register’s clock with extra capacitance at its clock input, giving a more optimistic skew, while the T model is
more pessimistic. The T model would give a skew that is 0.69*150*50f = 5.2ps worse, but shorten the
minimum clock period by as much. Part c) would see the opposite effect.
Also, the wording was ambiguous as to whether tsum is the delay to the far end of the line to the register, or just
to the output of the adder. The above solution assumed the former, but it’s acceptable to interpret tsum as the
latter, in which case an interconnect delay of 0.69*200*50=6.9ps should be added to tsum. This helps the race
condition check, but increases the minimum clock period.