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Lecture 6
Logic Simulation
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What is simulation?
Design verification
Circuit modeling
True-value simulation algorithms
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Compiled-code simulation
Event-driven simulation
Summary
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Simulation Defined
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Definition: Simulation refers to modeling of a
design, its function and performance.
A software simulator is a computer program;
an emulator is a hardware simulator.
Simulation is used for design verification:
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Validate assumptions
Verify logic
Verify performance (timing)
Types of simulation:
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Logic or switch level
Timing
Circuit
Fault
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Simulation for Verification
Specification
Synthesis
Response Design Design
analysis changes (netlist)
Computed
responses
True-value
simulation
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Input stimuli
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A 32-bit ripple-carry adder
00
11
00
00
1
1
00
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00
1
1
1
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Design verification Vectors for 4-bit
adder circuit (functional correctness)
Delay Test for longest path : C0
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C4 , vector 2,6(3,7)
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C4: 0
1
5
5.2:Simulation for
Test Evaluation
Determines the Fault Coverage
Produce a set of test vector
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Test evaluation for single stuck at fault
Four-bit adder
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Reverse-Order simulation
101010101
100110011
011001100
010101010
Reverse-Order simulation cannot be used for sequential Circuits
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5.3: Modeling Circuits
for Simulation
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Modules, blocks or components described by
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Interconnects represent
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Input/output (I/O) function
Delays associated with I/O signals
Examples: binary adder, Boolean gates, FET,
resistors and capacitors
ideal signal carriers, or
ideal electrical conductors
Netlist: a format (or language) that describes
a design as an interconnection of modules.
Netlist may use hierarchy. ( HDL (Verilog ),
VHDL)
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Modeling Levels and Type of
simulaton
Timing
Application
Clock
boundary
Architectural
and functional
verification
0, 1, X
and Z
Zero-delay
unit-delay,
multipledelay
Logic
verification
and test
0, 1
and X
Zero-delay
Logic
verification
Fine-grain
timing
Timing
verification
Continuous
time
Digital timing
and analog
circuit
verification
Modeling
level
Circuit
description
Function,
behavior, RTL
Programming
language-like HDL
Logic
Connectivity of
Boolean gates,
flip-flops and
transistors
Switch
Transistor size
and connectivity,
node capacitances
Timing
Transistor technology Analog
voltage
data, connectivity,
node capacitances
Circuit
Tech. Data, active/
passive component
connectivity
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Signal
values
0, 1
Analog
voltage,
current
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Example: A Full-Adder
c
a
b
A
B
C
N1
d
O1
HA1
e
HA
D
E
HA2
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F
A2
O2
f
Carry
Sum
VLSI Test: Lecture 6
HA;
inputs: a, b;
outputs: c, f;
AND: A1, (a, b), (c);
AND: A2, (d, e), (f);
OR: O1, (a, b), (d);
NOT: N1, (c), (e);
FA;
inputs: A, B, C;
outputs: Carry, Sum;
HA: HA1, (A, B), (D, E);
HA: HA2, (E, C), (F, Sum);
OR: O2, (D, F), (Carry);
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Logic Model of MOS Circuit
pMOS FETs
a
b
VDD
Ca
Cb
Cc
c
a
Da
b
Db
nMOS FETs
Da and Db are
interconnect or
propagation delays
Dc is inertial delay
Ca , Cb and Cc are
parasitic capacitances
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c
Dc
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of gate
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Options for Inertial Delay
Inputs
(simulation of a NAND gate)
Transient
region
a
b
Logic simulation
c (CMOS)
c (zero delay)
c (unit delay)
X
c (multiple delay)
Unknown (X)
c (minmax delay)
0
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rise=5, fall=3
min =2, max =5
Time units
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Signal States
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Two-states (0, 1) can be used for purely
combinational logic with zero-delay.
Three-states (0, 1, X) are essential for
timing hazards and for sequential logic
initialization.
Four-states (0, 1, X, Z) are essential for MOS
devices. See example below.
Analog signals are used for exact timing of
digital logic and for analog circuits.
Z
(hold previous value)
0
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0
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Level of Simulation
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Register-level , for systems modeled entirely
in RTL or as an interconnection of
components modeled in RTL
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Functional-level, for systems modeled as an
interconnection of primitive functional blocks
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Gate-level simulation;
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Transistor-level (we consider logic level and
not circuit-level analog simulation)
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Mixed-level simulation
4Week
Fault-Tolerant System Design
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True-Value Simulation
Algorithms
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Compiled-code simulation
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Applicable to zero-delay combinational logic
Also used for cycle-accurate synchronous sequential
circuits for logic verification
Efficient for highly active circuits, but inefficient for
low-activity circuits
High-level (e.g., C language) models can be used
Event-driven simulation
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Only gates or modules with input events are
evaluated (event means a signal change)
Delays can be accurately simulated for timing
verification
Efficient for low-activity circuits
Can be extended for fault simulation
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Compiled-Code Algorithm
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Step 1: Levelize combinational logic and
encode in a compilable programming language
Step 2: Initialize internal state variables (flipflops)
Step 3: For each input vector
Set primary input variables
Repeat (until steady-state or max. iterations)
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Execute compiled code
Report or save computed variables
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Compiled Simulation
 Delay can be modeled
by
Explicitly adding them
to
Software model
4Week
Fault-Tolerant System Design
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Example: A Full-Adder
a
b
A
B
C
c
A1
e
d
O1
HA1
4Week
N1
D
E
A2
HA2
F
o2
f
Carry
Sum
Fault-Tolerant System Design
HA;
inputs: a, b;
outputs: c, f;
AND: A1, (a, b), (c);
OR: O1, (a, b), (d);
NOT: N1, (c), (e);
AND: A2, (d, e), (f);
FA;
inputs: A, B, C;
outputs: Carry, Sum;
HA: HA1, (A, B), (D, E);
HA: HA2, (E, C), (F, Sum);
OR: O2, (D, F), (Carry);
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Asynchronous circuit simulation with compiled-code mode
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Fault-Tolerant System Design
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Correct model for compiled simulati
0
1
0 1 0
1
0
Shows that a compiled
simulator cannot deal with
Races and hazards
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Fault-Tolerant System Design
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Main flow of
event-driven
simulation
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Fault-Tolerant System Design
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Event-Driven Algorithm
(Example)
2
0
e =1
t=0
2
2
d=0
4
b =1
f =0
g
0
4
8
Time, t
2
VLSI Test: Lecture 6
c=0
d, e
d = 1, e = 0
f, g
3
4
g=0
5
6
f=1
g
7
8
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Activity
list
1
g =1
Time stack
a =1
c =1
Scheduled
events
g=1
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Time Wheel (Circular Stack)
Current
time
pointer
max
t=0
1
Event link-list
2
3
4
5
6
7
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Efficiency of Eventdriven Simulator
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Simulates events (value changes) only
Speed up over compiled-code can be ten
times or more; in large logic circuits about
0.1 to 10% gates become active for an input
change
Steady 0
0 to 1 event
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Steady 0
(no event)
VLSI Test: Lecture 6
Large logic
block without
activity
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Delay Models
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Delay modeling
is a key element
controlling the
trade-off between
the accuracy and
the complexity of
the simulation
algorithm.
Delay Modeling
for gates:
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Fault-Tolerant System Design
4Week
4Week
Fault-Tolerant System Design
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Transitionindependent delay
model
d
d
d
f
r
dI=4
dI=2
4Week
d
Fault-Tolerant System Design
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Output Inertial Delay
4Week
Fault-Tolerant System Design
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Delay Modeling for Functional
element
4Week
Fault-Tolerant System Design
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Wire delays Modeled by delay element
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Fault-Tolerant System Design
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Summary
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Logic or true-value simulators are essential
tools for design verification.
Verification vectors and expected responses
are generated (often manually) from
specifications.
A logic simulator can be implemented using
either compiled-code or event-driven method.
Per vector complexity of a logic simulator is
approximately linear in circuit size.
Modeling level determines the evaluation
procedures used in the simulator.
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