Download Lecture 5 Combinational Logic Implementation Using Multiplexers

Lecture 5
Combinational Logic Implementation
Using Multiplexers, ROMS, FPGAs
Prith Banerjee
ECE C03
Advanced Digital Logic Design
Spring 1998
ECE C03 Lecture 5
1
Outline
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Combinational Logic Implementations
Multiplexers
Decoders
ROMS
Field Programmable Logic Arrays
READING: Katz 4.2.2, 4.2.3, 4.2.4, 4.2.5, 10.3,
Dewey 5.7
ECE C03 Lecture 5
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Use of Multiplexers/Selectors
Multi-point connections
A0
Sa
A1
B0
B1
MUX
MUX
A
B
Multiple input sources
Sb
Sum
Ss
Multiple output destinations
DEMUX
S0
S1
ECE C03 Lecture 5
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General Concept of Using Multiplexers
2
n
data inputs, n control inputs, 1 output
n
used to connect 2 points to a single point
control signal pattern form binary index of input connected to output
Z = A' I 0 + A I 1
A
0
1
Functional form
Logical form
ECE C03 Lecture 5
Z
I0
I1
I1
0
0
0
0
1
1
1
1
I0
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
Z
0
0
1
0
0
1
1
1
Two alternative forms
for a 2:1 Mux Truth Table
4
I0
Use
of
Multiplexers/Selectors
2:1
I1
mux
Z = A' I 0 + A I 1
Z
A
I0
I1
I2
I3
4:1
mux
A
I0
I1
I2
I3
Z
B
8:1
mux
I4
I5
I6
I7
A
Z = A' B' I0 + A' B I1 + A B' I2 + A B I3
B
Z
C
Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 +
A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7
n -1
2
In general, Z = S
m I
k=0
k k
in minterm shorthand form for a 2 n :1 Mux
ECE C03 Lecture 5
5
Alternative Implementation
A
B
I0
Z
I1
I2
I3
Transmission Gate
Implementation of
4:1 Mux
Gate Level
Implementation
of 4:1 Mux
twenty transistors
thirty six transistors
ECE C03 Lecture 5
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Design of Large Multiplexers
Large multiplexers can be implemented by cascaded smaller ones
I0
I1
I2
I3
0 4:1
1 mux
2
3S S
I4
I5
I6
I7
0 4:1
1 mux
2
3S S
1
1
B
Control signals B and C simultaneously
choose one of I0-I3 and I4-I7
8:1
mux
0 2:1
mux
1 S
0
Z
Control signal A chooses which of the
upper or lower MUX's output to gate to Z
I0
0
I1
1 S
0
C
C
A
I2
0
I3
1 S
0
1
Alternative 8:1 Mux Implementation
C
I4
0
I5
1 S
C
I6
0
I7
1 S
ECE C03 Lecture 5
Z
2
3 S0
S1
A
B
7
C
2
Multiplexers/Selectors as General
Purpose Blocks
n-1
:1 multiplexer can implement any function of n variables
n-1 control variables; remaining variable is a data input to the mux
Example:
F(A,B,C) = m0 + m2 + m6 + m7
= A' B' C' + A' B C' + A B C' + A B C
= A' B' (C') + A' B (C') + A B' (0) + A B (1)
1
0
1
0
0
0
1
1
0
1
2
3
4
5
6
7
F
8:1
MUX
S2 S1 S0
A
B
C
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F
1
0
1
0
0
0
1
1
C
C
0
C
C
0
1
0
1
2
3
4:1
MUX
S1
A
F
S0
B
1
"Lookup Table"
ECE C03 Lecture 5
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Generalization of Multiplexer/Selector
Logic F
I I … I
1
n-1 Mux
control variables
single Mux
data variable
…
2
n
0
1
0
0
0
1
1
0
1
1
Four possible
configurations
of the truth table rows
0
In
In
1
Can be expressed as
a function of In, 0, 1
Example:
G(A,B,C,D) can be implemented by an 8:1 MUX:
K-map
Choose A,B,C
as control variables
Multiplexer
Implementation
TTL package efficient
May be gate inefficient
ECE C03 Lecture 5
1
D
0
1
D
D
D
D
0
1
2
3
4
5
6
7
G
8:1
mux
S2
A
S1
B
S0
C
9
Decoders/Demultiplexers
Decoder: single data input, n control inputs, 2
n
outputs
control inputs (called select S) represent Binary index of output to which
the input is connected
data input usually called "enable" (G)
1:2 Decoder:
O0 = G • S; O1 = G • S
3:8 Decoder:
O0 = G • S0 • S1 • S2
O1 = G • S0 • S1 • S2
2:4 Decoder:
O0 = G • S0 • S1
O2 = G • S0 • S1 • S2
O1 = G • S0 • S1
O3 = G • S0 • S1 • S2
O2 = G • S0 • S1
O4 = G • S0 • S1 • S2
O3 = G • S0 • S1
O5 = G • S0 • S1 • S2
O6 = G • S0 • S1 • S2
ECE C03 Lecture 5
O7 = G • S0 • S1 • S2
10
Alternative Implementations
G
Output0
Select
/G
Select
Output0
Output1
Output1
1:2 Decoder, Active Low Enable
1:2 Decoder, Active High Enable
/G
G
Select0
Output0
Output0
Output1
Output1
Output2
Output2
Output3
Output3
Select0
Select1
2:4 Decoder, Active High Enable
Select1
2:4 Decoder, Active Low Enable
ECE C03 Lecture 5
11
Switch Level Implementations
Select
Select
G
G
Output
0
Select
Select
Output
0
Select
Select
"0"
Select
Output
1
Select
Select
Output
1
Select
Naive, Incorrect Implementation
Select
All outputs not driven at all times
"0"
Select
Correct 1:2 Decoder Implementation
ECE C03 Lecture 5
12
Switch Implementation of 2:4 Decoder
Select
G
0
Select
1
Output
0
Operation of 2:4 Decoder
"0"
"0"
G
S0 = 0, S1 = 0
Output
1
"0"
one straight thru path
three diagonal paths
"0"
G
Output
2
"0"
"0"
G
Output
3
"0"
"0"
ECE C03 Lecture 5
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Decoder as a Logic Building Block
Enb
3:8
dec
S2
A
S1
B
S0
0
1
2
3
4
5
6
7
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABC
Decoder Generates Appropriate
Minterm based on Control Signals
C
Example Function:
F1 = A' B C' D + A' B' C D + A B C D
F2 = A B C' D' + A B C
F3 = (A' + B' + C' + D')
ECE C03 Lecture 5
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Decoder as a Logic Building Block
Enb
4:16
dec
S3 S2 S1 S0
A
B C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
F1
F2
F3
D
If active low enable, then use NAND gates!
ECE C03 Lecture 5
15
Alternative Implementation of 32:1 Mux
I7
I6
I5
I4
I3
I2
I1
I0
C
D
E
EN
I31 7 151
EN 1 6
5
1
Y5
I23 7 151
41 4
6
3
W 6
EN 1 5 52 2
1
3
5
1
I15 7 151
41 4
40Y 6
1
52 3
W
EN 1 6
5
2
3
3 1 Y 19
1
5C
7 151
41 4
B
4 0W 1 6A
6 5 3
0
22
5
9
1
3 1 Y 15 C
4
4 0 1 6B
13
W0 A
2
9
1
1 1 C
B
0 1A
S2 0
1
S1
S0
1 1G 1Y3
1391Y2
A 3 1B 1Y1
2 1A 1Y0
B
15 2G 2Y3
2Y2
13 2B 2Y1
14 2A 2Y0
1 GA
3 A3
4 A2
5 A1
6 A0
13
12
11
10
1
5
153
YA 7 F(A, B, C, D, E)
B3
B2
YB 9
B1
B0
GBS1 SO
2 14
A B
7
6
5
4
9
10
11
12
7 EN 146
5
154
I31 7 151
1
3
6
7 EN
22
I5 145
31 Y 5
154
I23 7 I4151
40
3
7 EN 146 I3 1
W 6
2
I5 5 I2 2
9C
154 I1 3 1 Y 10
5B
I15 7 I4151
3 I0 4 0 W 116A
7 EN 146 I3 1
I5 5 I2 22 C 9 C
S2
154 I1 31Y 10
5B
I7 7 I4 151
S1
I6 6 I3 1 3 I0 40WD 116A
I5 5 I2 2 2 C 9C
S2E S0
5
I4 4 I1 3 1 Y 10
S1
D 11B
I3 3 I0 4 0 W
6A
I2 2 C 9 S2
S0
E
I1 1 10C
B
S1
D
I0 0 11A
C S2E S0
D S1
E S0
F(A, B, C, D, E)
Multiplexer + Decoder
Multiplexer Only
ECE C03 Lecture 5
16
5:32 Decoder
\EN
S4
S3
1G 1Y3
139 1Y2
1B 1Y1
1A 1Y0
2G 2Y3
2Y2
2B 2Y1
2A 2Y0
\EN
S2
S1
S0
\Y31
5:32
Decoder
Subsystem
.
.
.
S2
S1
S0
\Y0
S4 S3 S2 S1 S0
S2
S1
S0
S2
S1
S0
ECE C03 Lecture 5
G1
G2A
G2B
Y7
Y6
Y5
Y4
138 Y3
Y2
C
Y1
B
Y0
A
\Y31
\Y30
\Y29
\Y28
\Y27
\Y26
\Y25
\Y24
Y7
G1
G2A Y6
G2B Y5
138 Y4
Y3
Y2
C
Y1
B
Y0
A
\Y23
\Y22
\Y21
\Y20
\Y19
\Y18
\Y17
\Y16
Y7
G1
G2A Y6
G2B Y5
138 Y4
Y3
C
Y2
B
Y1
A
Y0
\Y15
\Y14
\Y13
\Y12
\Y11
\Y10
\Y9
\Y8
G1 Y7
G2A Y6
G2B Y5
138 Y4
Y3
Y2
C
Y1
B
Y0
A
\Y7
\Y6
\Y5
\Y4
\Y3
\Y2
\Y1
\Y0
17
Read-Only Memories
ROM: Two dimensional array of 1's and 0's
Row is called a "word"; index is called an "address"
Width of row is called bit-width or wordsize
Address is input, selected word is output
+5V +5V +5V +5V
n
2 -1
Dec
i
Word Line 0011
j
Word Line 1010
0
0
n-1
Address
Bit Lines
C03 Lecture 5
Internal ECE
Organization
18
Implementing Logic with ROMs
F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C'
A
0
0
0
0
1
1
1
1
Address
ROM
8 w ords ¥by
4 bits
A B C
address
F0
F1
F2
outputs
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F0
0
1
0
0
1
1
0
0
F1
0
1
1
0
0
0
0
1
F2
1
1
0
0
1
0
0
0
F3
0
0
0
1
1
0
1
0
Word Contents
F3
ECE C03 Lecture 5
19
ROMs vs PLAs
Memory array
Not unlike a PLA
structure with a
fully decoded
AND array!
Decoder
2n word
lines
n address
lines
2n words by
m bits
m output
lines
ROM vs. PLA:
ROM approach advantageous when
(1) design time is short (no need to minimize output functions)
(2) most input combinations are needed (e.g., code converters)
(3) little sharing of product terms among output functions
ROM problem: size doubles for each additional input, can't use don't cares
PLA approach advantangeous when
(1) design tool like espresso is available
(2) there are relatively few unique minterm combinations
(3) many minterms are shared among the output functions
ECE C03 on
Lecture
PAL problem: constrained fan-ins
OR5 planes
20
2764 EPROM
8K x 8
2764
VPP
PGM
A12
A11
A10
O7
A9
O6
A8
O5
A7
O4
A6
O3
A5
O2
A4
O1
A3
O0
A2
A1
A0
CS
OE
Read-Only Memories
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U3
OE
+
A13
/OE
A12:A0
D15:D8
D7:D0
+
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U1
OE
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U2
OE
+
+
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U0
OE
16K x 16
Subsystem
ECE C03 Lecture 5
21
Combinational Design with FPGAs
Programmable Logic Devices = PLD
PALs, PLAs = 10 - 100 Gate Equivalents
Field Programmable Gate Arrays = FPGAs
• Altera MAX Family
• Actel Programmable Gate Array
• Xilinx Logical Cell Array
100 - 1000(s) of Gate Equivalents!
ECE C03 Lecture 5
22
Altera Erasable Programmable Logic
Devices
Historical Perspective:
PALs – same technology as programmed once bipolar PROM
EPLDs — CMOS erasable programmable ROM (EPROM)
erased by UV light
Altera building block = MACROCELL
CLK
Clk
MUX
8 Product Term
AND-OR Array
+
Programmable
MUX's
AND
ARRAY
Output
MUX
Q
pad
I/O Pin
Invert
Control
F/B
MUX
Programmable polarity
ECE C03 Lecture 5
Seq. Logic
Block
Programmable feedback
23
Altera EPLDs
Altera EPLDs contain 8 to 48 independently programmed macrocells
Personalized by EPROM bits:
Global
CLK
Clk
MUX
Synchronous Mode
1
Flipflop controlled
by global clock signal
OE/Local CLK
Q
EPROM
Cell
Global
CLK
Clk
MUX
local signal computes
output enable
Asynchronous Mode
1
OE/Local CLK
Q
Flipflop controlled
by locally generated
clock signal
EPROM
Cell
+ Seq Logic: could be D, T positive or negative edge triggered
+ product term to implement
clear
ECE C03 Lecture
5 function
24
Altera EPLDs
AND-OR structures are relatively limited
Cannot share signals/product terms among macrocells
Altera solution: Multiple Array Matrix (MAX)
Logic
Array
Blocks
(similar to
macrocells)
LAB A
LAB H
LAB B
LAB C
LAB G
P
I
A
LAB D
LAB F
Global Routing:
Programmable
Interconnect
Array
EPM5128:
8 Fixed Inputs
52 I/O Pins
8 LABs
16 Macrocells/LAB
32 Expanders/LAB
LAB E
ECE C03 Lecture 5
25
Altera EPLDs
LAB Architecture
I/O Pad
Macrocell
ARRAY
I
N
P
U
T
S
I/O
Block
I/O Pad
P
I
A
Expander
Product
Term
ARRAY
Macrocell
P-Terms
Expander
P-Terms
Expander Terms shared among all
macrocells within the LAB
ECE C03 Lecture 5
26
Altera EPLDs
P22V10 PAL
INCREMENT
2904
1
0
0
FIRST
FUSE
NUMBERS
44
88
132
176
220
264
308
352
396
4
8
12
16
20
24
28
32
36
40
2948
2992
3036
3080
3124
3168
3212
3256
3300
3344
3388
3432
3476
3520
3564
3608
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
11
10
AR
D
Q
00
Q
01
SP
23
5808
P
R
1
0
5809
OUTPUT
LOGIC
MACROCELL
3696
3740
3784
3828
3872
3916
3960
4004
4048
4092
4136
4180
4224
4268
22
P - 5810
R - 5811
924
17
P - 5820
R - 5821
4312
OUTPUT
LOGIC
MACROCELL
4356
4400
4444
4488
4532
4576
4620
4664
4708
4752
4796
4840
21
P - 5812
R - 5813
1496
OUTPUT
LOGIC
MACROCEL
L
16
P - 5822
R - 5823
8
4884
OUTPUT
LOGIC
MACROCELL
4928
4972
5016
5060
5104
5148
5192
5236
5280
5324
20
P - 5814
R - 5815
4
OUTPUT
LOGIC
MACROCEL
L
15
P - 5824
R - 5825
9
5368
2156
2200
2244
2288
2332
2376
2420
2464
2508
2552
2596
2640
2684
2728
2772
2816
2860
5
OUTPUT
LOGIC
MACROCEL
L
7
3
1540
1584
1628
1672
1716
1760
1804
1848
1892
1936
1980
2024
2068
2112
P - 5818
R - 5819
3652
2
968
1012
1056
1100
1144
1188
1232
1276
1320
1364
1408
1452
18
6
440
484
528
572
616
660
704
748
792
836
880
OUTPUT
LOGIC
MACROCEL
L
OUTPUT
LOGIC
MACROCELL
5412
5456
5500
5544
5588
5632
5676
5720
OUTPUT
LOGIC
MACROCEL
L
14
P - 5826
R - 5827
19
10
P - 5816
R - 5817
SYNCHRONOUS
PRESET
(TO ALL REGISTERS)
5764
11
INCREMEN
T
13
0
4
8
12
16
20
24
28
32
36
40
Supports large number of product terms per output
Latches and muxes associated with output pins
ECE C03 Lecture 5
27
+
rows of interconnect
Anti-fuse Technology:
Program Once
Use Anti-fuses to build
up long wiring runs from
short segments
I/O Buffers, Programming and Test Logic
I/O Buffers, Programming and Test Logic
Logic Module
I/O Buffers, Programming and Test Logic
Rows of programmable
logic building blocks
I/O Buffers, Programming and Test Logic
Actel Programmable Gate Arrays
Wiring Tracks
8 input, single output combinational logic blocks
FFs constructed
from discrete cross coupled 28
gates
ECE C03 Lecture 5
Actel Logic Module
SOA
S0
Basic Module is a
Modified 4:1 Multiplexer
S1
D0
2:1 MUX
D1
2:1 MUX
Y
D2
2:1 MUX
D3
R
SOB
Example:
Implementation of S-R Latch
"0"
2:1 MUX
"0"
2:1 MUX
Q
"1"
2:1 MUX
ECE C03 Lecture 5
S
29
Actel Interconnect
Logic Module
Horizontal
Track
Anti-fuse
Vertical
Track
Interconnection Fabric
ECE C03 Lecture 5
30
Actel Routing Example
Logic Module
Input
Logic Module
Logic Module
Output
Input
Jogs cross an anti-fuse
minimize the # of jobs for speed critical circuits
2 - 3 hops for most interconnections
ECE C03 Lecture 5
31
Xilinx Logic Cell Arrays
CMOS Static RAM Technology: programmable on the fly!
All personality elements connected into serial shift register
Shift in string of 1's and 0's on power up
IOB
IOB
CLB
IOB
CLB
IOB
Wiring Channels
CLB
IOB
General Chip Architecture:
• Logic Blocks (CLBs)
• IO Blocks (IOBs)
• Wiring Channels
IOB
IOB
IOB
ECE C03 Lecture 5
CLB
32
Xilinx LCA Architecture
Inputs:
Tri-state enable
bit to output
input, output clocks
Outputs:
input bit
Program Controlled Options
OUT
INV
TS
INV
OUTPUT
SOURCE
SLEW
RATE
PASSIVE
PULLUP
Enable
Output
PAD
MUX
Internal FFs for
input & output paths
Out
D
Pull-up used with
unused IOBs
Q
Output
Buffer
R
Direct In
Fast/Slow outputs
5 ns vs. 30 ns rise
Vcc
Q
D
Registered In
TTL or CMOS
Input Buffer
R
Clocks
ECE C03 Lecture 5
Global Reset
33
Xilinx LCA Architecture
Configurable Logic Block: CLB
2 FFs
Reset
DIN
Any function of
5 Variables
Global Reset
Q1
A
B
C
D
E
Clock, Clock Enb
D RD
Q
CE
F
Mux
X
Mux
Y
Combinational
Function
Generator
Q2
G
Mux
Clock
Independent DIN
Mux
Mux
D RD
Q
CE
Clock
Enable
ECE C03 Lecture 5
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Xilinx CLB Function Generator
CLB Function Generator
A
B
Q1
A
B
Mux
C
D
E
F
Mux
C Mux
D
E
Q2
Q1
Function
of 5
Variables
Mux
Function
of 4
Variables
F
Function
of 4
Variables
G
Mux
Q2
G
Q1
A
B
Any function of 5 variables
C
D
E
Mux
Mux
Mux
Q2
ECE C03 Lecture 5
Two Independent Functions
of 4 variables each 35
Xilinx CLB Function Generator
Q1
A
B
Mux
C
Mux
Function
of 4
Variables
D
Certain Limited
Functions of 6 Variables
E
F
Q2
Mux
Q1
A
B
C
G
Mux
Mux
Function
of 4
Variables
D
Q2
ECE C03 Lecture 5
36
Xilinx Application Examples
5-Input Parity Generator
Implemented with 1 CLB:
F = A xor B xor C xor D xor E
(this is a different parity generator than the one in Chapter 8!)
2-bit Comparator: A B = C D or A B > C D
Implemented with 1 CLB:
(GT) F = A C + A B D + B C D
(EQ) G = A B C D + A B C D + A B C D + A B C D
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Xilinx Application Examples
n-Input Majority Circuit
Assert 1 whenever n/2 or greater inputs are 1
5-input Majority Circuit
9 Input Parity Logic
CLB
CLB
7-input Majority Circuit
CLB
CLB
CLB
CLB
n-input Parity Functions
5 input = 1 CLB, 2 Levels
ofLecture
CLBs5 yield up to 25 inputs!
ECE C03
38
Xilinx Application Examples
4-bit Binary Adder
A3 B3
A2 B2
CLB
Cout
A1 B1
CLB
S3
CLB
S2
C2
A3 B3 A2 B2
CLB
A0 B0 Cin
C1
CLB
S1
C0
S0
A1 B1 A0 B0 Cin
S2
2 x Two-bit Adders (3 CLBs
each) yields 2 CLBs to final
carry out
CLB
S0
S3
Cout
Full Adder, 4 CLB delays to
final carry out
S1
C2
ECE C03 Lecture 5
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Xilinx Interconnect Architecture
Interconnect
Direct
Connections
DI CE A
B
X
C CLB0
K
Y
E D R
Direct Connections
Global Long Line
Horizontal
Long Line
Switching
Matrix
Horizontal/Vertical
Long Lines
Switching Matrix
Connections
DI CE A
B
X
C CLB1
K
Y
E D R
Horizontal
Long Line
DI CE A
B
X
C CLB3
K
Y
E D R
DI CE A
B
X
C CLB2
K
Y
E D R
Vertical
Long Lines
ECE C03 Lecture 5
Global
Long Line
40
Comparison of Recent Xilinx Architectures
XC 2018
Parameter
XC 4025
XC3195
Number of FFs
2560
1320
174
Number of I/Os
256
176
74
Number of logic inputs 9
per CLB
Function generators per 3
CLB
Fast Carry Logic
yes
5
4
2
2
no
no
Number of logic outputs 4
per CLB
RAM bits
32768
2
2
0
0
ECE C03 Lecture 5
41
Summary
•
•
•
•
•
•
Combinational Logic Implementations
Multiplexers
Decoders
ROMS
Field Programmable Logic Arrays
READING: Katz 4.2.2, 4.2.3, 4.2.4, 4.2.5, 10.3,
Dewey 5.7
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