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Transcript
A 1.8-V 3.6-mW 2.4-GHz Fully integrated CMOS
Frequency Synthesizer for IEEE 802.15.4
M.Vamshi Krishna, J.Xie, M.A.Do, C.C.Boon, K.S.Yeo and Aaron V.Do
School of Electrical and Electronic Engineering
Nanyang Technological university, Singapore 639798
Email: [email protected]
Abstract—This paper presents a low power 2.4-GHz fully integrated 1 MHz resoltuion IEEE 802.15.4 frequency sysnthesizer
designed using 0.18 µm CMOS technology. An integer-N fully
programmable divider employs a novel True-single-phase-clock
(TSPC) 47/48 prescaler and 6 bit P and S counters to provide the
1MHz output with nearly 45% duty cycle. The PLL uses a series
quadrature voltage controlled oscillator (S-QVCO) to generate
quadrature signals. The PLL consumes 3.6 mW of power at 1.8
V supply with the fully programmable divider consuming only
600 µW. The S-QVCO consumes 2.8 mW of power with a phase
noise of -122.4 dBc/Hz at 1MHz offset.
Index Terms—D flip-flop (DFF), frequency synthesizer,
TSPC, phase-locked loop (PLL), Series-QVCO, Dual modulus
prescalers.
Fig. 1.
Transceiver architecture
I. I NTRODUCTION
M
OST of the wireless communication standards prior
to IEEE 802.15.4/Zigbee were tailored towards high
data rate and multimedia friendly applications. The need for
low data rate and low power wireless solutions with emphasis
on sensor network applications resulted in the development
of IEEE 802.15.4 standard. The recent development and
advanced scaling in CMOS technologies have made it more
feasible and more attractive to implement a single chip CMOS
wirless transceiver for its potential in achieving a high level
of integration and low power consumption [1].
In most of the narrow band communication systems, the
frequency synthesizer plays a major role in generating local
oscillation (LO) signal or carriers and is usually implemented
through a phase locked loop (PLL) [2]-[5]. The key characteristics of the synthesizer such as phase noise, spur suppression and settling time have an important impact on the
entire transceiver performance. When compared to the IEEE
802.11 standards, IEEE 802.15.4 standards have relaxed spurs
and phase noise requirements which enables the design to
be power optimized. However, achieving overall transceiver
requirements by adressing the need for accurate I-Q signal
generation poses additional challenges.
The high power consumption in the frequency synthesizer
is mainly due to the VCO and the first stage divider which
is driven by the VCO. The 2.4 GHz frequency synthesizer
reported in [2] with a frequency resolution of 5 MHz consumes
a power of 7.85 mW at 1.8V power supply using 0.18 μm
CMOS technology. Here, the first stage divider is designed
using current-mode logic (CML) [6] which consumes a large
amount of power. The synthesizer reported in [3] consumes
2.4 mW at 1.2V supply using 0.13μm CMOS technology.
It uses 16/17 dynamic logic prescaler as first stage divider
which consumes only 176μA at 2.5 GHz and the complete
divider is designed with 5 MHz resolution. Here, the VCO
provides only differential outputs. The frequency synthesizer
reported in [4] proposes new spur suppression technique, but
the entire circuit consumes a power of 18mW. Reference [5]
provides a synthesizer for IEEE 802.15.4/Zigbee applications
which consumes 15mW from supply voltages of 3V, 1.8V
and 1.2V using 0.18 μm CMOS technology. In this paper,
an integer-N, low power 2.4 GHz frequency synthesizer with
quadrature signal generation is proposed. In this design, the
fully programmable 1 MHz resolution divider is implemented
using dynamic logic circuits.
II. F REQUENCY S YNTHESIZER A RCHITECTURE
For the popular transeiver’s architecture shown in Fig. 1
with direct up-conversion for the TX and low IF downconversion for the RX , the synthesizer needs to generate
LO outputs having both I-Q outputs. The architecture of the
integer-N frequency synthesizer used in this design is shown
in Fig. 2. The fully programmable 1 MHz resolution divider
used in this design is based on the pulse-swallow topology
and it is constructed using a TSPC [7] 47/48 (N/N + 1) dual
modulus prescaler, a 6-bit programmable P -counter and a 6bit swallow S-counter. The quadrature output is provided by
the series Q-VCO and the reference frequency used in the
design is 1 MHz.
Bits p5 and p6 of the P -counter are tied to logic ’1’ and
Loop filter
REF
UP
UP
UPB
UPB
REF
1 MHz
PFD
FD
DN
DN
DNB
DNB
IVctrl
R3
Charge
Pump
C1
R2
Q-VCO
C3
Vbias
Vbias
Dummy
dividers
I+
QQ+
C2
II+
Buffer Q-
VCO_Vbias
CP_Vbias
Vdc
47/48 (N/N+1) Prescaler
Q+
II+
QQ+
Asynchronous divider (AD)
out
FD_1MHz
output
6 Bit Programmable
(P) Counter
LDB
P1
P5
P2
P3
P4
P6
Logic ‘1’
LDB
s1
Fig. 2.
s2
s3
s4
s5
Q+
MC
MOD
Fully programmable
divider
Schematic of the 2.4GHz Frequency synthesizer with 1 MHz resolution divider
CLK
Q
Q
CLK
CLK
2
2/3 Prescaler
MC
CLK
2
Qb
Qb
Q
Q
CLK
2
Qb
Q
2
Qb
Fout
to P and S
Counter
Qb
Inv
NAND2
NAND1
NOR2
NOR1
MOD
Fig. 3.
Control logic
s6
Asynchronous Divider (AD)
Fin
2/3 Prescaler
MOD
6 Bit Swallow
(S) Counter
LD
16
Prescaler Out
LD
N + 1 = (16 × (3)) + (0 × (2)) = 48
Proposed 47/48 dual modulus prescaler
p4 to logic ’0’ to allow it to programmable from 51 to 52
and all the bits of S-counter are programmable from 0 to 48
to provide division ratios between 2400 to 2483 in steps of
1 MHz. In the initial state, the 47/48 (N/N + 1) prescaler
operates in divide-by-48 mode, where P and S counters start
down counting to zero from their loaded value. Since P > S,
the S-counter finishes counting the clock cycles down-to zero
earlier than P -counter, at which time the prescaler switches
to divide-by-47 for the remaining (P − S) clock cycles. The
total division ratio (F D) is given by
F D = (48 × (S)) + (47) × (P − S) = (48 × P ) − S
TSPC 2/3 prescaler reported in [8], four asynchronous divideby-2 circuits and additional logic gates to control the division
ratio between 47 and 48.When M OD=’1’, the logic value at
the output of the inverter will be ’0’ and the 2/3 prescaler
operates in divide-by-3 mode. The division ratio (N + 1)
performed by the 47/48 prescaler is
(1)
The Q+ output of the QVCO is connected to the fully
programmable divider, since the divider input is single-phase.
The other 3 outputs of the QVCO are given to dummy dividers
to have balanced output. The buffer at the output of QVCO
consists of open drain buffers used for testing.
III. C IRCUIT I MPLEMENTATION
A. A 47/48 Dual Modulus Prescaler
The dual modulus 47/48 prescaler shown in Fig. 3 is
similar to the 32/33 prescaler reported in [8] except for an
additional inverter at the output of N AN D2 gate to invert
the operation of 2/3 prescaler. The 47/48 prescaler consists of
(2)
If M OD= ’1’, the output of the inverter will be logic ’0’ for
15 input clock cycles and at logic ’1’ for 1 input clock cycle.
The division ratio (N ) performed by the 47/48 prescaler is
N = (15 × (3)) + (1 × 2) = 47
(3)
The Post layout simulation results shows that the dual
modulus 47/48 prescaler consumes a current of 269.3μA and
262.8μA during the divide-by-47 and divide-by-48 modes
respectively. The maximum operating frequency is 4.8 GHz.
B. Swallow (S) Counter
The 6 bit swallow S-counter used in the fully programmable
divider is shown in Fig. 4. It consists of 6 asynchronous
loadable bit-cells, a NOR-embedded DFF [9] and additional
logic gates to allow it to be programmable from 0 to 48.
The asynchronous bit-cell used in this design shown in Fig.
5 is similar to the bit-cell reported in [10], except it uses two
additional transistors M6 and M7 whose inputs are controlled
by the logic signal M OD. When the S-counter counter
finishes counting down-to-zero, M OD switches to logic ’1’
and the prescaler changes to the divide-by-47 mode for the
remaining (P − S) clock cycles. During this mode, since Scounter is idle, transistors M6 and M7 which are controlled
by M OD, keep the nodes S1 and S2 at logic ’0’ and node S3
at logic ’1’, thus saving the switching power in the S-counter
for a period of (N × (P − S)) clock cycles.
CLK
CLK
CLK
Q
PI
SP
Bit-cell
LDB
LDB
Qb
LD
LD
S1
Q1
P1
LDB
Qb1
LD
Q1
Q1
CLK
Q
PI
MOD
SP
Bit-cell
LDB
LDB
Qb
LD
LD
S2
Q2
P2
LD
A
NOR Q
B embedded
DFF
Qb
CLK
Q2
CLK
Q
PI
MOD
Bit-cell
SP
LDB
LDB
Qb
LD
LD
S3
Q3
CLK
CLK
Q
PI
MOD
SP
Bit-cell
LDB
LDB
Qb
LD
LD
CLK
Q
PI
MOD
SP
Bit-cell
LDB
LDB
Qb
LD
LD
Q2
P3
S5
LD
Q3
Q4
P4
Qb4
LD
Fig. 4.
Qb6
Qb5
Q
Qb
Q4
Q5
CLK
PI
MOD
SP
Bit-cell
LDB
LDB
LD
CLK
Q
LDB
Qb1
Q2
Bit-cell
Qb
LD
P5
LDB
LD
LD
Fig. 6.
Asynchronous 6 bit S-counter
CLK
Qb2
Q
LD
NOR Q
B embedded
DFF
LDB
CLK
Qb
CLK
Q3
Bit-cell
LDB
Qb
LD
Qb3
CLK
PI
LDB
Q6
Qb
LD
PI
LDB
Q5
Bit-cell
LDB
A
Qb3
Q4
Q1
MOD
Q3
S4
Q
PI
LDB
Qb2
CLK
PI
Q
Q4
Bit-cell
LDB
Qb
LD
CLK
PI
Q
Qb4
Q5
Q6
CLK
PI
Q
Bit-cell
Bit-cell
Qb6
LDB
LD
Qb
Qb5
Qb
LDB
LD
Q5
P6
LDB
LD
Asynchronous 6 bit P-counter
V /Q+; tran (V)
LD
MOD
M1
M7
LD
LD
M2
M12
M8
M9
M22
LD
MOD
CLK
M15
S3
M19
LD
CLK
M5
S4
S5
Q
M10
S1
M4
M25
M18
PI
M14
M3
M21
LDB
M13
S2
CLK
CLK
M17
LDB
M23
LD
M26
M6
M11
LDB
M20
M24
V /FD; tran (V)
Qb
M16
Fig. 5.
Asynchronous loadable bit-cell for S-counter
C. Programmable (P ) Counter
The programmable P -counter as shown in Fig. 6 is a 6
bit asynchronous counter which consists of 6 loadable bitcells and additional logic gates. The bit-cell used in designing
the P -counter is similar to the bit-cell reported in [10] with
optimized transistor values for low power consumption. Here,
bit P6 and P5 are always at logic ’1’ and bit P4 at logic ’0’ to
have programmable values of 51 and 52. By choosing a fixed
value of 51 and 52, the swallow S-counter is programmed
in steps of one-bit to provide a division ratio from 2400 to
2483 with 1 MHz resolution. The Fully progammable divider
at 2.4 GHz consumes a power of 600μW. Fig. 7 shows the
post layout results of the divider at 2.4 GHz with output of
the divider having nearly 45% duty cycle. The duty cycles
changes by a larger value if there is large difference between
the values of prescaler (N ) and P , S-counters.
Fig. 7.
2400
Post layout results of programmable divider with division ratio of
D. Voltage Controlled Oscillator:
The VCO used in this design is a Series QVCO (SQVCO) and its schematic is shown in Fig. 8. The S-QVCO
has been proven to eliminate the trade-off between phase
noise and I/Q mismatch [11]. Therefore, the design can be
optimized for phase noise performance, while keeping I/Q
mismatch low. Compare to the Parallel-QVCO, the coupling
transistors N M3 -N M4 and N M7 -N M8 are in series with the
switching transistors N M1 -N M2 and N M5 -N M6 . Hence the
tail current for the coupling transistors is removed; and the S-
Vdd
Vctrl
PM1
PM3
PM4
charging
PM2
Vcp
INM1
Q+
NM2
QNM5
NM6
DNB
UPB
discharging
I+
DN
UP
Vbias
NM3
NM4
NM7
Vbias
NM8
NM10
NM9
Fig. 8.
Fig. 10.
Schematic of the chargepump
CP
Bias AVDD
Series quadrature voltage controlled oscillator
VCO
Bias
Q+
GND
Q-
REF
I+
I-
DVDD
S1
Fig. 9.
S4
S6
P2
VDC
P3
Quadrature signals of the S-QVCO
Fig. 11.
QVCO consumes less power. The current-reuse technique is
used to further reduce the current consumption of the S-QVCO
by adding cross-coupled PMOS transistors on top of the crosscoupled NMOS transistors. Open-drain transistors are added to
the output nodes of the S-QVCO to serve as the buffer to the
testing equipment. The gain of the S-QVCO from post layout
results is 414 MHz/V and Fig. 9 shows the quadrature output
signals of the S-QVCO. The analysis in [8] shows that TSPC
2/3 prescaler consumes low power if its input signal DC level
is higher. To accomodate this function, the S-QVCO output’s
DC level can adjusted to the value required by divider using
Vdc as shown in Fig. 2.
E. Phase Frequency Detector(PFD) and ChargePump
The PFD used in this design is a conventional NAND based
design. The dead-zone removal pulse is of 11ns, which is
sufficient to turn-ON U P and DN switches of the chargepump
shown in Fig. 10 during the locked condition. Since the gain
of S-QVCO is very high, the chargepump current is chosen to
be low (25μA) to allow for small lower loop filter capacitances
and ease integration.
F. Loop filter
The loop filter used in this design is 3rd order as shown
in Fig. 2. The loop filter parameters are imposed by the
system level performance specifications such as settling time,
Layout of the 2.4 GHz frequency synthesizer
phase noise and spur suppression. Initially a 2nd order filter
is designed and later a RC low-pass section is added. The
reference frequency used in this design is 1 MHz. The 2nd
order filter is assumed to be a critically damped system with a
loop bandwidth (fc ) of 45 KHz (satisfy the Gardner’s stability
criterion [12]), a chargepump current of 25μA (Icp ) and a
VCO gain (Kvco ) of 414 MHz/V. For a optimal stability
(α = 2) [5], the zero (fz1 ) and pole (fp1 ) are placed at 11.25
KHz (fc /α2 ) and 180 KHz (fc × α2 ) respectively. With a
natural frequency (fn ) of 22.5 KHz, average division ratio
(N ) of 2450, the values of R2 , C2 , C1 is calculated using
C2 =
R2 =
Icp × Kvco
= 207pF
2π × N × ωn2
(4)
1
= 78.5kΩ
2π × fz1 × C2
(5)
C2
= 12.9pF
16
(6)
C1 =
The additional RC low pass section added to the 2nd order
filter reduces the phase margin to 54 degrees and the damping
factor to slightly less than 1. The value of R3 and C3 are
found to be 78.5 k Ω and 5.6 pF respectively. With frequency
accuracy of 40 ppm, the calculated settling time is 47.4 μs,
which is nearly four times less than the required settling time
for IEEE 802.15.4 standard (192 μs) [5].
TABLE I
P ERFORMANCE S UMMARY OF S YNTHESIZER
Design parameters
Post layout results
Process (µm)
0.18
supply voltage (V)
1.8
Frequency synthesis
2400-2483 MHz
Reference Frequency
1 MHz
VCO gain
414 MHz/V
Tuning Range
Fig. 12.
Phase noise of the S-QVCO
16.7%
Phase noise at 1MHz
-122.4 dBc/Hz
Power Consumption (PLL)
3.6 mW
Power Consumption (VCO)
2.8 mW
Power Consumption (Divider)
0.6 mW
Settling time
58µs
Settling time =58 us
tion consumes only 600μW and synthesizer uses S-QVCO for
quadrature signal generation. The power consumption of the
whole frequency synthesizer is 3.6 mW.
Fig. 13.
Settling time of the frequency synthesizer
IV. S IMULATIONS R ESULTS
This fully programmable 1 MHz resolution frequency synthesizer has been designed using Global foundries 0.18μm
CMOS technology at 1.8 V power supply and post layout simulations are carried out to verify the design. Fig.11 shows the
layout of the designed frequency synthesizer which occupies
a core area of 0.95 × 0.9mm2 , dominated by the S-QVCO
inductors and by the loop filter. The S-QVCO consumes a
power of 2.8 mW with a phase noise of -122.4 dBc/Hz at 1
MHz offset shown in Fig. 12. The fully programmable divider
consumes a power of 600 μW and provides nearly 45% duty
cycle signal to the PFD. The post layout results shows that the
synthesizer takes 58 μs to settle as shown in Fig. 13, which
is slightly higher than the calculated value of 47.7 μs due to
parasitics and slightly reduced damping factor. The total power
consumption of the frequency synthesizer is 3.6 mW which is
lesser than the frequency synthesizers reported in literature
[2]-[5].
V. C ONCLUSION
In this paper, a fully integrated 1 MHz resolution 2.4
GHz IEEE 802.15.4 frequency synthesizer is designed using
Global foundries 0.18μm CMOS technology is presented. A
new 47/48 dual modulus prescaler based on dynamic logic
is proposed along with improved bit-cell for the swallow Scounter. The fully programmable divider with 1 MHz resolu-
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