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Digital Fundamentals
Analog to Digital (A to D) Conversion
Supplement
Prepared by Mike Crompton (20 August 2008)
Analog to Digital Conversion (A to D)
The 3 bit Flash (simultaneous) Converter.
The diagram at right represents an analog to
digital converter that gives a 3 bit output
when ever the Enable is activated.
It’s main components are:
 An 8 resistor voltage divider with
outputs taken at 1V steps (from 1V to
7V) which provide a fixed reference
against which the incoming analog
voltage will be compared.
 7 comparators that will give a positive
voltage out (a Hi) when their + input is
at a higher voltage than their – input and
0V out (a Lo) when their – input is
higher than their + input.
 A Priority Encoder that responds only to
the highest of it’s inputs, ignoring
anything less when there are multiple
inputs. This encoder will give a 3 bit
binary output that corresponds to the
binary equivalent of it’s highest input.
The operation is relatively simple. When an
analog voltage is applied, all the comparators
that have a Reference voltage that is less than
the analog input voltage will output a Hi.
Only the highest will be recognized by the
Priority Encoder which will then output a 3
bit binary number. e.g. If the incoming
analog voltage was 5.5V then comparators 1
to 5 will all give a high output. The encoder
will recognize the output from comparator 5
only and produce ‘101’ at it’s output.
Obviously comparator 6 will not give a Hi O/P because the fixed reference of 6V on it’s
– I/P is still higher than the 5.5V analog input on it’s + I/P. It will continue to output a 0.
This particular converter can only differentiate between input voltage changes of 1Volt,
and to a maximum of 7V. An increased number of resistors in the voltage divider
network could increase it’s sensitivity and allow it to respond to changes of less than 1V.
The encoder would have to have more inputs and outputs to allow it to go beyond the
present 7V maximum.
The advantage of this converter is it’s speed and ability to continuously and
simultaneously change it’s O/P as the analog input voltage changes.
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Simple Encoder
Shown at right is a much simplified example
of an encoder that might be used as part of an
A to D converter. As can be seen it has a 3
bit O/P and is made from 3 ordinary OR
gates and a series of switches. In an actual
circuit/device the switches could well be
transistors that will saturate at different
voltage levels. The circuit operation is as
follows:
 With all switches open, none of the OR
gates will be activated and therefore the
O/Ps will register the binary number 000.
 If only switch 1 is closed the upper OR
gate will give an output Hi and that will
activate the 20 (LSB) O/P giving the
binary number 001.
 If only switch 2 is closed the middle OR
gate will activate the 21 O/P giving the
binary number 010.
 If only switch 3 is closed then the upper two OR gates will activate the 2 0 and the 21
O/Ps giving the binary number 011. (The same O/P would result if switch 1 and 2
were closed)
 If only switch 4 is closed the bottom OR gate will activate the 22 (MSB) O/P giving
the binary number 100.
 Switches 1 and 4 will activate the upper and lower OR gates giving the binary O/P
101.
 Switches 2 and 4 will activate the lower two OR gates giving binary 110.
 Finally switches 3 and 4 will activate all three OR gates and the binary O/P would be
111. (The same O/P would result if switches 1, 2 and 4 or all four switches were
closed).
One problem with the Flash or other simultaneous A to D converters is their lack of
sensitivity and/or the relatively low number of bits that appear as the digital output. These
disadvantages can be overcome with the addition of many more components or with the
use of additional converting devices. If however, there is no need for instant and
continuous output, another family of A to D converters is available that does give greater
sensitivity and a larger number of output bits. One of the most common of these is the
‘Stairstep Ramp’ A to D converter shown on the following page.
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‘Stairstep Ramp’ A to D converter
The diagram at right is a ‘Stairstep
Ramp’ A to D converter which consists
of several logic devices covered in the
past. i.e. An 8 bit binary counter, an 8
bit D to A converter, 8 latches, an AND
gate, a control circuit that would be
unique to each particular type of A to D
converter and a single comparator
similar to those used in the Flash
converter that has been discussed on
page 2 earlier in this supplement.
The operation of this device is fairly
involved but does not really contain
anything that has not been covered in
the basic logic operation of each
individual device.
Let us first presume a set of starting conditions:
a) The counter is cleared and all it’s 8 O/Ps are Lo.
b) The D to A converter has zeros on all it’s I/Ps because the counter O/Ps are Lo.
c) The – I/P of the comparator is at 0V because the D to A converter O/P is 0V.
d) The Control circuit will produce a momentary Enable pulse and a delayed Clear pulse
when it’s edge triggered I/P goes from Hi to Lo. The delay is to allow the latches to
be set/reset before the counter clears.
e) The Latches are D type with only one data I/P and a clock I/P that will be fed by the
enable pulse from the Controller, not the system clock.
Now apply an analog voltage to the + I/P of the comparator. The O/P goes positive and
on the next clock pulse the AND gate O/P goes to a 1 and the counter increments by 1
(from 0 to 1). The D to A converter produces it’s first step voltage which is fed to the –
I/P of the comparator. If the analog voltage is still greater than the step voltage the
comparator’s O/P remains Hi and on the next clock pulse the And gate O/P goes to 1 and
increments the counter by 1 (from 1 to 2). The D to A converter O/P voltage goes up by
another step and this is fed once again to the – I/P of the comparator. As long as the
analog voltage remains greater than the step voltage the counter continues to increment,
and the D to A converter continues to increase the step voltage.
When the step voltage exceeds the analog voltage the comparator O/P goes Lo. This
triggers the controller to produce the Enable pulse. When the enable pulse is applied to
the latches, they will Set or Reset depending on whether the counter O/Ps connected to
their D I/Ps are 1 or 0 (Hi or Lo). The respective Q O/Ps of the latches will now register a
binary number that is in direct proportion to the analog voltage. After the short delay, the
controller Clear pulse clears the counter, which in turn clears the D to A converter and
puts the step voltage back to 0V so the process can begin again.
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The disadvantage of this device is the time taken to produce a digital O/P. The maximum
number of steps is 28 = 256 (8 bit), and the maximum count is 1111111 or 255 (28 = 256
minus 1). If the analog voltage is at it’s maximum the time to produce the O/P will be
255 times the clock frequency period time. e.g. If the clock is 1kHz the period time is
.001 Secs or 1 mSec so the total time will be 255 * 0.001 = 0.255 Secs. This, in computer
terms is a very long time. Increasing the clock frequency will help to reduce this time, but
it must be remembered that due to propagation delays in the devices, there is a maximum
frequency above which the devices will not have time to react.
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