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Design of CMOS Comparators for FLASH ADC
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Design of CMOS Comparators for
FLASH ADC
M. Madhavilatha
ECE Deptt., Jawaharlal Nehru Technological University, Hyderabad,
A.P, India, E-mail: [email protected].
G.L. Madhumati
ECM Deptt., PVPSIT, Kanuru, Vijayawada, JNTU, Hyderabad,
A.P, India, E-mail: [email protected].
K. Rama Koteswara Rao
ECE Deptt., DVRDHS & MIC, Kanchikacherla, JNTU, Hyderabad,
A.P, India, E-mail: [email protected].
ABSTRACT: The analog to digital converters is the key components
in modern electronic systems. As the digital signal processing
industry grows the ADC design becomes more and more
challenging for researchers. In these days an ADC becomes a
part of the system on chip instead of standalone circuit for data
converters. This increases the requirements on ADC design
concerning for example speed, power, area, resolution, noise etc.
New techniques and methods are going to develop day by day to
achieve high performance ADCs. Of all types of ADCs the flash
ADC is not only famous for its data conversion rate but also it
becomes the part of other types of ADC for example pipeline and
multi bit Sigma Delta ADCs. The main problem with a flash
ADC is its power consumption, which increases in number of
bits. The performance limiting blocks in such ADCs are typically
comparators. This paper presents the comparison of power
consumption of different comparators used in flash ADCs with
CMOS technology. The layout comparisons are also done.
Keywords: Analog-to-digital converter (ADC), comparators, low
power, high speed, low area, CMOS Technology.
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1. INTRODUCTION
In today’s world, where demand for portable battery operated
devices is increasing, a major thrust is given towards low power
methodologies for high resolution and high-speed applications. This
reduction in power can be achieved by moving towards smaller
feature size processes. One application where low power, high
resolution and high speed are required is Analog-to-Digital Converters
(ADCs) for mobile and portable devices. The performance limiting
blocks in such ADCs are typically inter-stage gain amplifiers and
comparators. In the literature major emphasis has been made to the
inter-stage gain amplifiers but very little effort has been made
towards the design of comparators. The accuracy of such comparators, which is defined by its offset, along with power consumption
is of keen interest in achieving overall higher performance of ADCs.
In the past, pre-amplifier based comparators have been used for
ADC architectures such as flash and pipeline. The main drawback
of pre-amplifier based comparators is the high constant power
consumption. To overcome this problem, dynamic comparators are
often used that make a comparison once every clock period and
require much less power as compared to the pre-amplifier based
comparators. Compared to the pre-amplifier based comparators
however, these dynamic comparators suffer from large offsets
making them less favorable in flash based ADC architectures.
In pipeline ADCs, digital correction techniques along with adequate
over-range protection can tolerate such large offsets.
The rest of the paper is organized as follows: Section 2 describes
the design of the Flash ADC and its various components. Section 3
discusses the various types of comparators. Section 4 discusses the
simulation results.
2. ANALOG TO DIGITAL CONVERTER
Analog to digital converters are the basic building blocks that
provide an interface between an analog world which accepts an
analog value (voltage/current) and converts it into digital form that
can be processed by a microprocessor. As it is the main block in
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Design of CMOS Comparators for FLASH ADC
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mixed signal Applications, it becomes a bottleneck in data processing
applications and limits the performance of the over all system.
Different architecture of ADCs include Flash, Sigma-Delta, Pipeline,
Successive Approximation and Dual Slope ADCs.
2.1. Design of the Flash ADC
Flash ADC’s have parallel architecture and is the fastest ADC [5]
among all the other types and are suitable for high bandwidth
applications.
A typical flash ADC block diagram is shown in Figure 1 and it
can be seen that 2 N – 1 comparators are required for an “N” bit
converter. The resistor ladder network is formed by 2 N resistors,
which generates reference voltages for the comparators. The reference
voltage for each comparator is one least significant bit (LSB) less
than the reference voltage for the comparator immediately above
it. When the input voltage is higher than the reference voltage of
comparator it will generate a “1”, otherwise, the comparator output
is “0”.
Figure 1: Block Diagram of Flash ADC.
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M. Madhavilatha, G.L. Madhumati and K. Rama Koteswara Rao
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Figure 2: Resistor Ladder.
The comparators will generate a thermometer code of an input
signal. This thermometer code will then decode into a binary form
by thermometer-to-binary decoder. “The comparators are typically
a cascade of wideband and low gain stages. They are low gain
because at high frequencies it’s difficult to obtain both wide bandwidth and high gain. They are designed for low voltage offset, such
that the input offset of each comparator is smaller than a LSB of the
ADC. Otherwise, the comparator’s offset could falsely trip the
comparator, resulting in a digital output code not representative of
a thermometer code. A regenerative latch at each comparator output
stores the result. The latch has positive feedback, so that the end
state is forced to either a “1” or a “0”.
2.2. Components of Flash ADC
In flash ADC an array of comparators compares the input voltage
with a set of increasing reference voltages. All flash ADCs comprises
of following three blocks:
1.
Resistor Ladder Block.
2.
Comparator Block.
3.
Decoder Block.
The next section deals with each block.
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2.2.1. Resistor Ladder
Resistor ladder is used to generate the reference voltages for the
comparators. It is assumed that the feed through at nodes ref-low
and ref-high is negligible due to proper decoupling. Maximum feed
through will occur on the mid node.
2.2.2. Comparator
A comparator is used to detect whether a signal is greater or smaller
than reference signal. Various comparator include multiple stage
comparators, Regenerative Comparators (positive feedback),
Resistive Driving Comparators and fully differential Dynamic
comparators.
Dynamic latch comparator can solve the power problem by
removing the pre-amplifying stage, while achieving a smaller area.
Although latch comparators typically have a high offset voltage in
the range of 100mV, their fast speed and low power make them
suitable for several applications.
2.2.3. Decoder
The Digital decoder is required to transform the thermometer output
code from the comparator block output to binary code. There are
many techniques to design a decoder, which convert thermometer
code into binary for example ROM decoder, Wallace Tree decoder,
FAT tree decoder, multiplexer decoder, etc.
3. COMPARATORS AND ITS TYPES
A comparator is a differential amplifier with no feedback loop,
whose function is to compare the analog signals presented at its
inputs. Depending on the polarity of the differential input the logic
output is produced. As it is the case with several types of ADCs,
usually one of the comparator’s input is connected to a constant
potential or reference. The circuit symbol and ideal transfer function
of a comparator is shown in Figure 3. It can be seen that if the voltage
difference Vin+ – Vin– is positive the comparator’s output will go high
(VOH), otherwise its output will go low (VOL).
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(a)
Figure 3: Comparator (a) Circuit Symbol
(b)
(b) Ideal transfer function
3.1. Performance Metrics
Due to fabrication limits and process variations, the comparator
performance is affected by non-ideal effects. As a result, the response
deviates from the ideal one. The main parameters that characterize
the performance of comparators are
Static Parameters: The static parameters describes the performance of a comparator under DC or steady-state conditions. The
main parameters are resolution, gain, offset, noise, and ICMR.
Resolution is the minimum input difference that can be resolved
by the comparator in order to switch between its binary states. When
employed in ADCs, the resolution specification must be equal or
lower than the least-significant-bit (LSB) defined by the converter.
The gain, Av, is one of the key limiting factors in achieving the
desired resolution for the comparator.
Offset is defined as the minimum amount of input voltage
required for the binary-state transition to take place. In a real comparator the offset adds to the minimum voltage for which the resolution
was designed reducing the resolution of the circuit.
Noise has great influence on the operation of the comparator,
thus affects the performance of an ADC. The effect of noise in the
circuit’s response can be seen as uncertainty in the time when the
comparator’s output switches between its two states.
Input common-mode range (ICMR) is the permissible voltage
range over which the input common-mode signal can vary while
all transistors remain biased in the saturation region.
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Dynamic Parameters: Three of the most important dynamic
parameters that determine the speed of a comparator are
Propagation Delay is the time that elapses between an input
transition and the corresponding output change. It is usually
measured at the midpoints between the input and output signals.
Settling Time is defined as the time needed for the output to be
settled within a specified percent of its final value.
Slew Rate is a large-signal behavior that sets the maximum rate
of output change. It is limited by the output driving capability of
the comparator.
3.2. Architectures
Comparators can be roughly classified into open-loop (continuoustime) comparators and regenerative comparators. The main difference
resides on whether or not feedback is applied to the op amp used.
To obtain the benefits offered by both types of comparators, many
configurations have been developed that employ a combination of
open-loop stages with regenerative stages that use positive-feedback.
3.2.1. Two Stage Open-loop Comparators
An open-loop comparator is an operational amplifier designed to
operate with its output saturated, close to the supply rails, based on
the polarity of the applied differential input. The op amp does not
employ the use of feedback and hence no compensation is required
to achieve stability in the system. This does not poses a problem
since the linear operation is of no interest in comparator design.
The main advantage of not compensating the op amp is that it can
be designed to obtain the largest possible bandwidth, thereby
improving its time response.
The circuit of open-loop comparator is shown in Figure 4. It is
based on the commonly used two-stage op amp. The first stage is a
NMOS differential-pair consisting of transistors M1 and M2, with
PMOS transistors M3 and M4 acting as a diode-connected active load.
NMOS Transistor M3 is used to bias the input pair. The output stage
is a current-sink inverter consisting of transistors M5 and M6.
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Figure 4: Two-Stage Open-Loop Comparator.
The advantage of open-loop comparators is that, if enough gain
is provided, the minimum detectable differential input can be very
small (< 1mV).
Av =
VOH – VOL
Vin+ – Vin–
Comparator with the largest gain provides infinite resolution.
However, increasing the gain also reduces the bandwidth of op
amps, i.e. If resolution will improves then the time response of the
comparator will degrade. Thus, a tradeoff between speed and resolution must be made. The absolute maximum resolution of open-loop
comparators is limited by input-referred noise and the offset voltage
present in the op amp used.
3.2.2. Regenerative Comparators
Unlike open-loop comparators, regenerative comparators make use
of positive feedback to realize the comparison between two signals.
These comparators operate in discrete-time rather than continuoustime form. They operate with a clock that divides the operation of
the circuit into two phases. During the first phase the comparator
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tracks the input and during the second phase the positive feedback
is enabled. Depending on the polarity of the input, the latch’s output
will go high as the other will go low [1].
Figure 5: Latch Comparator Circuit.
The basic principle of regeneration consists in employing a latch
circuit. In figure 5. the latch employs positive feedback through the
cross-coupled connection of the NMOS (or PMOS) transistors and
its operation is divided into two phases using a non-overlapping
clock circuit. During the first phase, the latch command is issued
and the circuit tracks the input voltage applied between its terminals
Vin+ and Vin–. During the second phase (latch), transistors M5 and M6
isolate the latch from the input as these are turned “off”. The regeneration occurs between the drain and gate terminals of transistors
M9 and M10, finalizing when one of its outputs turns high and the
other low. When a new comparison cycle begins (latch command),
the latch output is reset to VDD through transistors M7 and M8. Digital
inverters are usually connected at the outputs to raise the signals to
full digital logic levels. One of the advantages of using positive
feedback is that the time response can be very fast thanks to the
positive exponential transfer characteristic of the latch [3].
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Due to mismatch present in the transistors, the resulting offset
voltage limits the maximum resolution achievable with this circuit.
To operate latch in the exponential region of its transfer characteristic,
the minimum resolvable input must be large enough to overcome
the large offset voltage, typically in the range from 30 to 100 mV.
3.2.3. Resistive Driving Comparators
Figure 6 shows the structure of resistive driving latch. Transistor
M3 – M6 forms a cross-coupled latch and M7 – M8 forms an input
comparing circuit. As CLK is low, the circuit works in the reset mode.
It is disconnected from GND by M9 while M1 – M2 is on and precharge the outputs to VDD. During this time the power consumption
is only due to VDD charging the two output capacitors When CLK is
high, the circuit works in the regeneration mode. M1 and M2 are cut
off, and M9 is on. In this mode, the circuit can compare the input
voltages by using input transistors operated in the triode region.
Figure 6: Resistive Divider Comparator.
The comparing circuit which can be modeled has values of
resistors R1 and R2 can be described in the equations. Assume that
WA = W7 and WB = W8 and Vtn is the threshold voltage of the NMOS
transistor. If Vin = 1 and Vref = 0 then node Out-will try to discharge
through M5 and M7 but the transistor M3 try to charge up node Out.
Therefore it is very important to make transistor M3 and M4 very
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weak as compared to M5, M7 and M6, M8, so that the output will
discharge very fast and the propagation delay will decrease.
3.2.4. Fully Differential Dynamic Comparator
Fully differential circuit is useful in rejecting common-mode noise
in integrated circuits that do both analog and digital signal processing.
In such circuits, comparators provide a link between the analog and
digital domains. Fully differential comparators usually subtract a
differential reference voltage from a differential input voltage (or
vice versa).
A fully differential dynamic comparator based on two differently
sized cross coupled differential pairs is shown in Figure 7. In this
the current sources are switch able and the latch circuit is connected
directly between the source coupled pairs and the supply voltage.
Figure 7: Fully Differential Pair Comparator.
When the comparator is inactive the latch signal Vlatch is at OV,
which means that the current source transistors M5 and M6 are
switched off and no current path between the supply voltages exists.
Simultaneously the PMOS switch transistors Mg and M12 reset the
outputs by shorting them to Vdd. The NMOS transistors M7 and Mg
of the latch conduct and force also the drains of all the input
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transistors M1 – M4 to V & potential. When Vlatch is risen to Vdd the
outputs are disconnected from the positive supply and the switching
current sources M5 and Ms enter saturation and begin to conduct.
These two transistors determine the bias currents of the two
differential pairs M1 – M2 and M3 – M4, respectively. The threshold
voltage of the comparator is determined by the current division in
the differential pairs and between the cross coupled branches.
4. RESULTS AND CONCLUSION
The performance of the comparators are summarized in Table 1.
Among all comparators considered Fully Differential Dynamic
Comparators have low power dissipation. The layout [3] of the two
stage open loop comparator is shown in Figure 8. Two stage open
loop comparator occupies 160 µ2m. In this paper various types of
comparators have been considered. The propagation delay in all
cases and offset voltage measurements are to be found.
Table 1
Comparison of Simulation Results
Comparator Type
Two Stage Open-loop Comparators
Regenerative Latch Comparators
Resistive Driving Comparators
Fully Differential Dynamic Comparator
Power
0.301 mW
0.208 mW
7.031 µW
0.515 µW
Layout (WXH)
20µm × 8 µm
22µm × 15µm
22µm × 9µm
22µm × 13µm
Figure 8: The Layout of the two Stage Open Loop Comparator.
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December 1992.
[2] Christian Jesus B. Fayomi, Gordon W. Roberts’ and Mohammad Sawan,
“Low Power/Low Voltage High Speed CMOS Differential Track and Latch
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Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland.
[3] Baker R.A Li H. W, and Boyce D.E., “CMOS Circuits Design, Layout and
Simulation” IEEE Press Series on Microelectronic System.
[4] P. Cusimato et al., “Analysis of the Behavior of a Dynamic Latch Comparator”,
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pp. 294-298, Mar. 1998.
[5] Rudy Van De Plassche, “CMOS Integrated Analog-to-Digital and Digital-to Analog Converters”, Springer International Edition, 2005.
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