Download A Fast Simulation Approach for Inductive Effects of VLSI Interconnects










Abstract
Introduction
What is Interconnect?
Inductance effects on Bus wires
System overview
Modeling for accurate inductive effect
Simulation examples
Conclusion
References
A Fast Simulation Approach for Inductive
Effects of VLSI Interconnects
Meanwhile, ignoring the nonlinear
ABSTRACT:Modeling on-chip
behavior of drivers in a fast linear circuit
simulator results in large errors for the
inductive effects for interconnects of
inductive effect.
multiGHz microprocessors remains
In this paper, a fast and accurate time-
challenging. SPICE simulation of these
domain transient analysis approach is
effects is very slow because of the large
presented, which captures the non-
number of mutual inductances.
linearity of circuit drivers, the effect of
is characterized by reliability, low power
non-ideal ground and de-coupling
dissipation, extremely low weight and
capacitors in a bus structure. The
volume, and low cost with an ability to
proposed method models the non-
cope easily with a high degree of
linearity of drivers in conjunction with
sophistication
specific
integrated circuit has made possible the
bus
geometries.
Linearized
complexity.The
waveforms at each driver output are
design
incorporated
processor which provide high intelligent
into
an
interconnect
of
and
powerful
and
flexible
reduced-order simulator for fast transient
and adaptable devices for the user.
simulation.
non-ideal
The vast majority of present day
capacitor
electronics is the result of the invention
models enable accurate signal and
of the transistor in 1947.The very first
ground bounce simulations. Results
integrated circuit (IC) emerged at the
show that this simulation approach is
beginning of 1960 and since that time
upto 68x faster than SPICE while
there have already been four generations
maintaining 95% accuracy.
of ICs: small scale integration (SSI),
ground
and
In
addition,
de-coupling
medium scale integration (MSI), large
scale integration (LSI), very large scale
I: INTRODUCTION
There is no doubt that our daily lives
are significantly affected by electronic
integration
(VLSI).Now
we
are
beginning to see the emergence of the
fifth
generation,
ultra
large
scale
integration (ULSI).
engineering technology. This is true on
the domestic scene, in our professional
disciplines, in the workplace, and in
Year
1980
Technology
leisure activities.
1950
1990
1961
1966
1971
SSI
MSI
LSI
10
100-1000
20,000-
10
10,00,000
1,0
8bit
16
2000
Invention
Discrete
of the
components
transistor
The revolutionary changes have taken in
Approximate
this field in a relatively short time and it
number of
is also certain that even more dramatic
transistors
advances will be made in the next
per chip
Typical
decade.Electronics as we know it today
1947
1
-
1
Junction
Planar
Counters,
products
transistor
and diode
devices,
Multiplexers
logic
adders
gates,
effects:
12μm
-
7μm-10μm
feature size
processors
5μm
Virtual
effects.Interconnect
wire
reality
three types
machinesof parasitic
capacitive,
<2μm
resistive
<1μm
and
100nm
inductive. All three have a dual effect on
circuit behavior.
over years
Ease of
parasitic
introduces
RAM
flops
-
processor
ROM
flip-
Reduction in
micro-connectbitwire and
processors,
inter
in the associated
-
-
simple
medium
Interconnect
medium
complex
Very
1.
An introduction
of Very
noise, which
complex
complex
affects the reliability of the circuit.
2. An increase in propagation delay.
III: INDUCTANCE
EFFECTS ON BUS
WIRES
II: WHAT IS
INTERCONNECT
An
interconnect
in
VLSI
design
In
multi-gigahertz
consists of actual path between global
designs,
routs
While
inductance of on-chip interconnects may
interconnect the physical metal lines
cause inaccurate delay and noise
introduces R,L,C parameters that can
estimations. Inductive effects are quite
have a dominant influence on the circuit
evident in on-chip buses where signals
operation, also this parasitic effects
may switch simultaneously. Self- and
display a scaling behavior that is
mutual inductance between parallel bus
different from the active devices. Their
wires can cause additional timing delay
effect increases as device dimensions
variations, overshoots, and significant
are
the
inductive noise. This is due to the
submicron
additive inductive coupling from all
and
actual
reduced
and
performance
dominate
in
technologies.
aggravated
circuit.
This
by
the
situation
fact
is
that
improvements in technology make the
production of ever-larger die sizes
economically feasible, which results in
an increase in the average length of an
ignoring
microprocessor
parallel wires.
the
parasitic
lead to large simulation errors and
even result in an unstable circuit model.
Because of the in-efficiency of SPICE
simulation, a fast and yet accurate timedomain transient simulation including
inductance is desirable. This paper
focuses on fast and accurate inductance
figure 1. A stage-delay pushout is due to
inductance. There is no significant inductive
effect when only the victim switches.
modeling and transient simulation for
onchip buses.
Figure.1 shows a victim’s far-end
waveform in a bus structure on three
layers. When all the signals switch in the
IV:SYSTEM
OVERVIEW
same direction, there are delay push-out
and over-shoots compared with the case
There has been some previously reported
when only the victim signal switches.
work on improving the efficiency of
Due to the long-range nature of the
simulating
mutual
wider
inductance. The effective capacitance
inductive
method for RC interconnect simulation
buses
inductive
can
cause
coupling,
more
interconnects
including
noise.
has been extended to RLC interconnect
Therefore, the proposed return limited
simulation. The efficient Ceff model
assumption may not be valid for on-chip
works in terms of pre-characterizing the
bus simulations. In addition, if all the
parameters of a time varying Thevenin
wires in a bus are cut into n segments
voltage source model (in series with a
for the RLC distributed effect, the
fixed resistor) over a wide range of
number of mutual inductances is n (n-
effective capacitance load values.
problems
for
delays
and
1)/2. Because of the huge number of
mutual inductances in a bus, SPICE runs
To avoid the expensive procedure in the
very slowly and is not feasible for large
above
industry
the
approximation, Kashyap proposed a
simple truncation of mutual inductance
synthesis procedure for RLC circuits
couplings in an inductance matrix can
that guarantees a realizable reduced
examples.Meanwhile,
model
is
due
to
a
Padé
order circuit using the first four moments
precharacterization technique for on-
of the input admittance. While these
chip buses is proposed. The non-
methods work well with self-inductance,
linearity of drivers is one of the keys to
the mutual inductance is not included.
accurately model the inductive effect in
For on-chip buses, it is the mutual
a bus structure. In order to have a
inductance that makes signal cross-talk
realistic
worse
parasitics (i.e. non-ideal grounds) are
and
jeopardizes
the
signal
bus
with
simulation,
integrity.
included
on-chip
Pre-characterization needs to include the
capacitors (decaps).
packaging
de-coupling
mutual inductance for each specific bus
structure. In addition, the Ceff method
and its related techniques are based on
the timing analysis theory and may not
work properly with noise estimations.
Meanwhile, the non-linearity of devices
plays an important role in inductive
noise. There is no reported work on fast
simulation for the impact of device
nonlinearity on the mutual inductive
effects.
Figure 2. Flow chart of the RLC interconnect
simulation tool.
Figure 2 illustrates the flow chart of the
implemented tool. Based on the user-
In this paper, an efficient transient
analysis tool to model the RLC effect
on timing and noise is presented. It
captures the self-/mutual inductance
effect, the non-linearity of drivers, the
effect of non-ideal ground and decoupling capacitors (decaps), and the
3-D geometries of interconnects.
To accurately model the inductive effect,
a
fast
and
practical
specified bus geometries (i.e., signal
wires and shields on the top, victim and
bottom layers plus power/grounds on a
power layer), a complete multi-bus
structure is constructed automatically.
Fasthenry is used to calculate self- and
mutual inductance. Together with RC
wire models, a circuit netlist for a
reduce-order interconnect simulation can
be generated. A fast reduce-order circuit
simulator is used to generate the
Traditionally, a linear resistor model is
waveforms for timing and noise analysis.
used for a device in a linear circuit
Among the other parameters that users
simulator, which is sufficient for an RC
can input are drivers/receivers, taps
simulation. For inductance simulation, a
along each power/ground wire, decaps
linear driver model is unable to capture
and signal input waveforms.
the inductance
In Section V, a non-linear driver
inductance) interaction with the drivers.
modeling
accurate
Simulations show that a linear driver
inductive effect is proposed, which is
model leads to the underestimating of
one of the key contributions of this
the signal inductive noise by 70%
work.
(Figure 3).
approach
for
Incorporating the device non-
(especially the mutual
linear behavior in a reduce-order linear
circuit simulator significantly increases
inductance
simulation
speed
while
maintaining a good accuracy. The nonideal ground modeling with decaps is
also discussed.
In Section VI, simulation results from
the microprocessor designs are presented
to
validate
the
RLC
simulation
Figure 3. Cross-talk at a victim wire within a 16-bit
bus on M6:
linear driver models lead to the underestimating of
inductive noise by 70%.
capabilities.
In Section VII the conclusions are
In terms of delay simulation, although
present.
the linear model can predict delay with
about 15% error, the waveform is not
V: MODELING FOR
ACCURATE
INDUCTIVE
EFFECT
accurate - the overshoot/undershoot
A: Modeling for the Non-Linearity
of Drivers
the correct waveforms at the driver
and fast ramp-up time are not properly
captured. This is due to the fact that the
linear driver model does not capture the
fast di/dt behavior and can not produce
outputs.
the waveforms based on simplified
circuit models for the interconnects to
speed up the pre-characterization, but all
self- and mutual inductance between the
wires are preserved. For a transmission
line system, the impedance which a
driver sees is
Where R, G, L, C are the resistance,
conductance, inductance and capacitance
per length of the transmission line.
figure 4. A non-linear driver model results in a much
faster amp-up time and a waveform with a small
ledge.
Parameter n is the number of segments
used to model the distributed effects.
The simplified circuit model uses the
Figure
4
shows
output
total resistance, conductance, inductance
waveform of a 16-bit bus on M6. The
and capacitance values, respectively,
difference between the two waveforms is
instead of the values for per length. It
due
presents
to
the
a
driver
non-linearity
of
the
same
impedance
drivers/devices. The interaction between
information to the driver as a complete
the self-/mutual inductance and the
distributed wire model, but with fewer
driver output voltage are not properly
segments
captured by a linear driver model.
precharacterization using SPICE. The
To accurately model the waveforms at
to
have
a
fast
simplified model is accurate to calculate
the driver output and capture the non-
the near-end waveforms, but it is not
linearity
accurate enough to calculate the far-end
of
a
device,
a
fast
precharacterization is done based on the
signal waveforms.
actual interconnect geometries and the
Results show that the pre-characterized
driver models. A non-linear circuit
waveforms at the interconnect near-end
simulator, like SPICE, is used to extract
have a very good match against SPICE
simulation with wire models using n
on-board VSS/VDD (e.g., C4 bumps)
segments. Each active driver can have a
needs to be modeled for any inductance
different output waveform depending on
ground bounce. The non-ideal ground is
the wires which it connects to and their
modeled using RLC tap models.
coupling. In other words, drivers on
Decaps
different layers and at a different bit
discharging
currents
position within a bus will have different
frequencies
when
waveforms. A piece-wise linear (PWL)
ground/power can not draw enough
approximation is then used to represent
currents through the taps from the on-
the characterized waveforms for each
board power sources. In this work,
driver. A fast linear circuit simulator
decaps are modeled based on the area
uses these waveforms as interconnect
(that the bus structure covers) and the
inputs. With a complete wire circuit
estimated decap values per chip area.
model,
far-end
The decap values are distributed along
waveforms can be accurately obtained
the VSS/VDD wires. With the help of
(i.e., noise and delay). In Section VI, the
decaps, the local VSS/VDD
pre-characterized
piece-wise
linear
becomes more stable (i.e., less ground
waveforms
the
driver
bounce).
the
interconnect
and
real
provide
charging
at
and
very
the
high
on-chip
waveforms will be plotted for accuracy
comparison.
VI: SIMULATION
EXAMPLES
B: Modeling for the Non-Ideal
Ground and Decaps
Various examples from microprocessor
designs are simulated with typical values
Unlike an RC extraction/simulation
where power/ground wires may be
modeled as ideal voltage connections,
the ground/power wires should be
modeled by distributed RLC elements in
RLC
simulation.
The
connection
between any ground/power wires to the
to demonstrate the validity of the
proposed
scheme.
Using
0.18
μm
technology. Results from the new tool
are compared with the ones from the full
SPICE simulation which includes all the
non-linear drivers.
Figure 5. All the signals switch from low to high,
and only the ninth signal keeps low. The precharacterized driver PWL waveform is plotted
with the one from SPICE simulation for
accuracy comparison.
In Figure 5, a 16-bit same layer bus with
only two ground shields is constructed
in order to exaggerate the inductive
Fig. 6(a) Delay
Fig. 6(b) Noise
Figure 6. The delay and noise waveform of the
victim wire on M4 is compared with the ones
from the full SPICE simulation.
effects so that the accuracy can be better
compared. The waveforms show the
A more complicated example consists of
noise at the far end of the victim wire.
three-layer buses with 12 bits on M6,
The first peak noise is negative which is
48bits on M4 and M2. All signals are
mainly due to the inductive effect while
fully shielded, but the shield widths are
the first positive noise is largely due to
comparable to the signal wires and they
the capacitive coupling.
do not serve as completely effective
shields for inductive effects. In the
simulation, all the signals switch in the
same direction at the same time. The
victim wire is in the middle of the bus in
M4. The signal delay (Figure 6(a)) and
noise (Figure 6(b)) are plotted for the
victim wire. In Figure 6(b), the noise
waveform shows that the major noise is
from the inductive coupling since there
is no capacitive coupling between the
signals in a fully shielded co-planar
VII: CONCLUSIONS
structure. Both signal delay and noise
waveforms are almost indistinguishable
Due to parallel routing and possible
from the ones with the full SPICE
simultaneous switching of signals in a
simulation.
bus, mutual and self-inductance can
cause additional delays and inductive
noise for bus signals. A fast and
accurate
time-domain
transient
waveform simulation approach for RLC
interconnect is presented. The capability
to include the nonlinearity of drivers in a
reduced-order linear circuit simulator
enables a much faster yet accurate
simulation of on-chip interconnects with
Figure 7. A three-layer bus example: the noise
becomes larger due to the non-ideal ground.
The inductance in the tap model is 500 pH and the
resistance is 5 Ω
inductance.
With tap models and decaps, bus
simulation becomes more realistic, and
Figure.
7
shows
the
two
noise
waveforms of a signal wire within a bus
where an ideal and a non-ideal ground
tap model are used. Due to the parasitic
inductance and resistance associated
with the ground/power taps, a larger
ground bounce can also be observed.
Results from the proposed method are in
a very good agreement with the ones
from
SPICE
simulation
while
the
simulation is 68X faster for large
examples.
inductive noise is observed with a nonideal ground model. The signal on a
local ground wire on M6 is also plotted
to illustrate the ground bounce. For
VIII: REFERENCES
decap effect, one simulation shows the
delay of a bit in the center of a three
layer bus without decaps is 15% larger
than the one with decaps.
[1]: Basic VLSI design – Douglas
A.Pucknell, Kamran Eshraghian.
[2]: Modern VLSI design – Wayne
Wolf.
[3]: Digital integrated circuits –
Jan M.Rabaey.
[4]: IEEE Journal on ‘On-chip
wiring
design
challenges
for
gigahertz operation’, April 2001.