Download Current Sensing in Pass Transistor

Current Sensing in Pass Transistor-Based
Configurable Logic
Preliminary Report (March 14, 2005)
Louis Alarcon and Octavian Florescu
Abstract – In order to reduce leakage power, a configurable logic cell
based on pass transistor logic trees and current sense circuits is shown.
Different pass transistor tree topologies and current sense circuits are
examined and various design, performance and implementation issues
are presented.
I. INTRODUCTION
P
ower dissipation, both dynamic and standby, are
becoming dominant factors in the design of integrated
circuits [6]. Traditional design methodologies tend to
concentrate more on active power and often overlook
standby or leakage power. However, as transistors scale, it is
predicted that leakage power will at some point dominate the
overall power consumption [6].
To overcome leakage, new circuit topologies will have to
be adopted, such as the use of long strings of transistors, or
stacks. Stack-based circuits are known to significantly
reduce leakage [11]. However, the penalty of using large
fan-in stack-based circuits is a drop in performance, when
compared to conventional logic styles [10] [11].
One way to regain the performance in stack-based circuits
is to use current sensing. This is due to the fact that current
sensing does not require large voltage swings to maintain
acceptable noise margins [1]. Hence, bypassing the long
delay times associated with conventional voltage sense
logic.
Sensing small currents in stack-based circuits, with low
voltage swings present a big challenge in the face of process
variations, especially in the 90nm regime and below [7].
In this paper, we explore various current sensing
architectures combined with a pass transistor logic tree.
II. PREVIOUS WORK
Current-sensing amplifiers are prevalent in memories and
interconnect. There are various types of current amplifiers
specifically targeted for memory [1] [3] [8], and for
interconnect [4] [9]. We will evaluate their effectiveness in
detecting signals through pass transistor stacks, and based on
these topologies, we will design our own current sense
circuits specifically suited for pass transistor stacks.
FIGURE 1. The pass transistor-based, current sense configurable logic
block with N data inputs and 2N programming bits.
III. THE CONFIGURABLE PASS TRANSISTOR LOGIC BLOCK
We propose a configurable logic cell that can generate any
desired logic function of N inputs. The functionality of the
cell is similar to that of an N-input look-up table (LUT),
with 2N programming bits and can therefore be used to
create an FPGA-like fabric. This is desirable since LUT
synthesis techniques are well known and can easily be
integrated in existing design methodologies [5].
Our design consists of a transistor stack and a current
sense amplifier, shown in FIGURE 1. The transistor stack
processes this inputs and generates a path between the root
input and one of the outputs. The sense amplifier senses the
current at the output and generates a full swing CMOS
voltage signal.
A. The Pass Transistor Logic Tree
The transistor stack is a binary pass transistor logic tree
that directly implements a Binary Decision Diagram (BDD),
shown in FIGURE 2.
The N inputs select a path in the logic tree that connects
the root input of the tree to one of the stack outputs, either
S+ or S-. The last stage of the stack is used to program the
desired logic function by routing the appropriate minterms to
the S+ output, and the
(a)
(a)
(b)
(c)
FIGURE 2. (a) The basic pass transistor multiplexer (b) the corresponding
BDD element and (c) a pass transistor tree with two data inputs and 4
programming bits.
maxterms to the S- output. Note that this last stage presents a
large capacitance at both outputs.
Since the outputs S+ and S- are pseudo-differential, where
logic “1” can be interpreted as a current flowing out of the
S+ output and logic “0” as current flowing out of the Soutput, differential current sensing techniques can be
applied.
The the selected path, from the root input to the output can
be modeled by a (N+1)-stage distributed RC network as seen
in [10].One expression for the delay of the current signal
through this path can be found in [2] [4].
(b)
B. The Current Sense Circuit
The RC delay associated with the pass transistor path is
prohibitive for full CMOS voltage level signals. By using
current signals and current sense amplifiers, we can recover
part of the performance loss by regenerating a signal from
smaller voltage swings.
We investigated the sense-amplifier implementations
compared in [3] and proposed our own as well: (1) the
Resistance Sensing Amplifier, (2) the Current Starved
Inverter Amplifier and (3) the DCVSL Sense Amplifier.
The Resistance Sensing Amplifier (RSA)
The Resistance Sensing Amplifier, as seen in FIGURE 3a,
works by sensing the difference in resistance seen at its
inputs. The path with the least resistance will provide the
most current and therefore engender a stronger inverter. This
will deterministically switch the latch.
The Current Starved Inverter Amplifier
The current sources at the inputs of the RSA can be a
source of mismatch. This can lead to deteriorated noise
margins. The Current Starved Inverter amplifier in FIGURE
3b is similar to the Resistance Sensing Amplifier is similar
(c)
FIGURE 3. Proposed current sense amplifiers. (a) Resistance sensing
amplifier, (b) Current starved inverter amplifier and (c) DCVSL sense
amplifier.
to the RSA, except without the bias current source at the
base. Therefore, the two branches receive different currents,
which lead to deterministic latching. The noise margin is
improved but it is slower due to the absence of the current
source.
The DCVSL Sense Amplifier
To further reduce the complexity of the sense amplifier,
the DCVSL sense amplifier was proposed (FIGURE 3c). This
implementation offers the best noise margin but is also the
slowest since the pull down network consists only of the
stack on resistance at the inputs.
In all cases the resistive network at the input of the
proposed sense amplifiers correspond to the resistances of
the pass transistor stack. The root node of the tree is
grounded and the two outputs, S+ and S- are connected to
the two inputs of the sense amplifier. Each branch of the
sense amplifier will see either an on stack resistance or an
off stack resistance.
The proposed current sense amplifiers do not need multi
phase clocks like the sense amplifiers shown in [3]. This
greatly simplifies the clocking scheme and the routing to the
logic block. In this scheme, the pass transistor stack is not
preconditioned. Without preconditioning, the initial current
from the stack is largely due to charge sharing when the
stack capacitance is connected to the sense amplifier. In the
worst case, the initial charge sharing currents in both
branches of the sense amplifier are equal. This reduces the
reliability of the sense amplifiers since the signal current can
be smaller than the charge sharing current.
The duration of the charge sharing current is also
problematic. The RC delay of the pass transistor chain
determines the time it will take for the transient charge
sharing current to subside. Hence, this is the time the sense
amplifier must wait between preconditioning the pass
transistor chain and sensing the current.
IV. PROPOSED WORK
Other current sense topologies will be investigated; in
particular, topologies that increase performance and decrease
power consumption in the presence of variations. Sizing
optimizations will be done and techniques to vary the stack
threshold voltage will also be explored on the pass transistor
stack to improve its RC delay constant. Different stack
preconditioning schemes will be examined. This includes
injecting currents from either side of the stack and various
clocking schemes that provides a separate preconditioning
and sensing time.
The resulting configurable pass transistor logic blocks will
then be compared and characterized in terms of their active
and standby power consumption, performance and
reliability.
V. SUMMARY
In terms of leakage, current sensing pass transistor logic
clearly has an advantage over conventional topologies such
as static CMOS. However, the difficulty lies in trying to
recover the performance loss due to the RC delay constant of
the pass transistor tree.
Current sensing recovers some of the performance loss by
not requiring full swing voltages. Preconditioning of the
transistor stack seems necessary in further improving the
performance. By preconditioning, we would eliminate the
large transient charge-sharing currents that initially
overwhelm the inputs of the sense amplifier.
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