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Editing Technology Editing the standard MOCMOS technology of GNU Electric version 8.08 by Kazzz (a Japanese engineer) Revision: 0.5 Date: June 07th, 2009 1 Revision history Work periods ※ Revision 0.5 ① ② ③ March 16th - April 10th, 2009 May 11th - May 15th, 2009 June 5th – June 7th, 2009 Editing Technology Remarks Initial effort to invite some valuable feedbacks from the user community ※ Mostly spending after the office hours … 2 Objectives Editing Technology ① To enhance the standard MOCMOS technology so that it has two resistor types below for analog circuit design N-well resistor Poly-2 high-resistor ② To make the entire technology including the newly added resistors NCC tool applicable DRC tool applicable ③ To make the newly added resistor types SPICE-parameterextraction applicable 3 Acknowledgments Editing Technology Thanks to Dr. Steven M. Rubin and all the developers of this VLSI design suite for providing such a fascinating tool under GNU General Public License. Availability of this tool has made me decide to re-study integrated circuit design, especially CMOS, after about 2decade gap. More than 20 years ago, having this kind of tool on a personal computer was beyond dream, especially for those who were using the first generation of GE Calma® on a minicomputer having only 64-KByte of main memory! 4 Warnings Editing Technology ① Throughout this document, the physical parameters such as sheet resistance, parasitic capacitance per unit length, design rules, etc. are all artificial and do not aspire to any accuracy. ② As stated in the previous slide, the main aim of this document is to capture and clarify different steps that may be required to introduce a new technology to GNU Electric. ③ For more realistic design and simulation, we MUST consult our foundry or in-house process engineers about those parameters and need fine tunings. 5 References Editing Technology Please refer to : [1] [2] http://java.com/en/ for Java [3] http://www.eclipse.org/ for Eclipse [4] http://www.staticfreesoft.com/productsFree.html for GNU Electric ✔ 6 Java Runtime and SDK Editing Technology The tools listed below are assumed as Java runtime and development environment Tool Version Install location OS Windows XP SP3 Japanese Java Runtime Java 6 Update 13 Java 3D 1.5.2 C:\Program Files\Java\Java3D\1.5.2\ Java SDK Java SED Kit 6 Update 13 C:\Program Files\Java\jdk1.6.0_13\ C:\Windows this may look like C:\Program Files\Java\jre6\ The images were captured on Japanese Windows throughout this document. Therefore, wherever you see a Yen mark in a file path, please understand that it corresponds to a “back slash” character in the non-Japanese world. 7 Some icons used throughout this presentation 8.2 Editing Technology Section of the manual to be referred to Duplicate the N-well # 01 # 02 # 03 Micro-steps to be followed sequentially 8 The final course materials Editing Technology Here is the latest and final course materials as of June 07th, 2009. You will find some intermediate materials embedded in this document, which were created while studying about this theme. Return to this slide after reaching the end of this document; far more than 240 slides. 9 Editing Technology Index Part-I Editing the Technology Skeleton Part-II Testing the Technology Skeleton Part-III Tuning the Technology for LT-Spice Simulation Part-IV Editing the Design Rules Part-V Testing the Design Rules 10 Editing Technology 11 01. Convert the existing technology for editing Editing Technology 8.2 # 01 Assume use of 3 metal layers 12 Editing Technology # 02 # 03 OK Cancel ※ Images are captured on Japanese Windows XP 13 # 04 # 05 Editing Technology Let the new technology name be “mocmos-plus.” # 06 14 02. Editing layer cells for N-well resistor Editing Technology 8.4 The manual says … 15 The cross-sectional view of an N-Well resistor under its contact node will be … Editing Technology Physically the same as but logically different from N-Select layer Metal-1 Oxide Oxide N-Well-Resistor-Plus N-Well-Resistor P-Base Physically the same as but logically different from N-Well layer 16 Editing Technology 8.4 Duplicate the N-well to derive “N-Well-Resistor” # 01 # 02 # 03 17 Editing Technology # 04 Don’t change GDS-II layer as this has the same physical layer as “N-Well” 18 Editing Technology Let the boarder be “solid-thick” style # 05 # 06 19 Duplicate the N-select for better Ohmic contact # 07 Editing Technology # 08 # 09 20 # 10 Editing Technology Don’t change GDS-II layer as this has the same physical layer as “N-Select” 21 Change the layer function and boarder style Editing Technology # 11 # 12 # 13 22 03. Editing a layer cell for Polysilicon-2 resistor Editing Technology Polysilicon-2 resistor will be made as below Polysilicon-2-HighResistor prevents Polysilicon-2-Resistor from being highly doped, hence, high sheet resistance. Polysilicon-2-HighResistor Top view Polysilicon-2-Resistor = Polysilicon-2 Physically the same as but logically different from Polysilicon-2 layer Regions uncovered by Polysilicon-2-HighReistor will be highly doped, hence, low ohmic contact resistance 23 Editing Technology The cross-sectional view of a Polysilicon-2 resistor under its contact node will be … Physically the same as but logically different from Polysilicon-2 layer Metal-1 Oxide Polysilicon-2-Resistor Oxide P-Base 24 Editing Technology 8.4 Duplicate the polysilicon-2 # 01 # 02 # 03 25 Editing Technology # 04 Don’t change GDS-II layer as this has the same physical layer as “Polysilicon-2” Just a guess 26 Change the boarder style and color Editing Technology # 05 # 06 27 Editing Technology # 07 # 08 Confirm that these 3 layers have been added 28 04. Editing a layer cell for Polysilicon-2 high-resistor Editing Technology 8.4 Duplicate the polysilicon-2 # 01 # 02 # 03 29 # 04 Editing Technology Just a place filler Above Poly2 by 1.0 30 # 05 Editing Technology Confirm that these 4 layers have been added 31 05. Editing an arc cell for N-well resistor Editing Technology 8.5 Duplicate the N-well # 01 # 02 # 03 32 # 04 Editing Technology 33 Change the layer to “N-Well-Resistor” Editing Technology # 05 # 06 Notice that the boarder style has been changed 34 Change the min. y size of both the boxes to “5” Editing Technology # 07 # 08 Then optionally move them down so that the top ycoordinate be zero (at the origin) 35 06. Editing an arc cell for Polysilicon-2 resistor Editing Technology 8.5 Duplicate the Polysilicon-2 # 01 # 02 # 03 36 # 04 Editing Technology 37 Editing Technology # 05 # 06 Notice that the boarder style and color have been changed 38 Keep the min. y size of both the boxes to “3” Editing Technology # 07 39 Editing Technology # 08 Confirm that these 2 arcs have been added 40 07. Editing an arc cell for Polysilicon-2 high-resistor Editing Technology 8.5 Duplicate the Polysilicon-2 # 01 # 02 # 03 41 # 04 Editing Technology 42 Editing Technology # 05 # 06 Notice that the boarder style and color have been changed 43 Keep the min. y size of both the boxes to “3” Editing Technology # 07 44 Editing Technology # 08 Confirm that these 3 arcs have been added 45 08. Editing a pin node for N-well resistor Editing Technology 8.6 Duplicate the N-well pin # 01 # 02 # 03 46 # 04 Editing Technology 47 Change the layer of each of the four boxes to “N-Well-Resistor” Editing Technology # 05 48 Editing Technology Confirm the layer used # 06 # 07 49 Change the port name of each of the four examples Editing Technology # 08 # 09 50 Change the connectivity of the main example Editing Technology # 10 Only “N-Well-Resistor” layer can connect to this port 51 Confirm that the connectivity of the other examples is all disallowed Editing Technology # 11 52 09. Editing a pure node for N-well resistor Editing Technology 8.6 Duplicate the N-well node # 01 # 02 # 03 53 # 04 Editing Technology 54 Editing Technology Change the function # 05 # 06 Change the layer of each box of the four examples # 07 55 Editing Technology # 08 Notice that the boarder style has been changed 56 Delete the current port “well” from each of the four examples Editing Technology # 09 As this node is to be a resistor, there must be two ports! n-well-res-1 n-well-res-2 57 After deleting the ports, only two boxes should exist for each example Editing Technology # 10 58 Add new ports using “artwork technology” Editing Technology # 11 Name the port # 12 59 Change the size of port so that it fits the left-side edge Editing Technology # 13 60 Move the port onto the left-side edge Editing Technology # 14 Similarly create a port on right-side edge # 15 61 Repeat the steps to add ports to the other examples Editing Technology # 16 62 Confirm the layers used Editing Technology # 17 63 Confirm the ports created Editing Technology # 18 64 Set the connectivity of the ports for the main example Editing Technology # 19 65 Confirm that the connectivity of the other examples is all disallowed Editing Technology # 20 66 Check the number of objects contained in this cell Editing Technology # 21 1 x 4 examples 1 x 4 examples 2 ports x 4 examples 2 ports x 4 examples 67 10. Editing a contact node for N-well resistor Editing Technology 8.6 Duplicate the Metal-1-N-Well-Con node # 01 # 02 # 03 68 # 04 Editing Technology 69 Editing Technology Change the function # 05 # 06 70 Change the layer of each box of the four examples Editing Technology # 07 71 Editing Technology # 08 72 Editing Technology Change the outer-most box (N-well resistor) size as below # 09 12x12 29x12 12x29 29x29 73 Change the port name of the four examples Editing Technology # 10 # 11 74 Confirm the layers used Editing Technology # 12 75 Confirm the ports created Editing Technology # 13 76 Set the connectivity of the port for the main example Editing Technology # 14 77 Confirm that the connectivity of the other examples is all disallowed Editing Technology # 15 78 Check the number of objects contained in this cell Editing Technology # 16 79 11. Editing a pin node for Polysilicon-2 resistor Editing Technology 8.6 Duplicate the Polysilicon-2 pin # 01 # 02 # 03 80 # 04 Editing Technology 81 Change the layer of each of the four boxes to “Polysilicon-2-Resistor” Editing Technology # 05 82 Confirm the layer used Editing Technology # 06 # 07 83 Change the port name of each of the four examples Editing Technology # 08 # 09 84 Change the connectivity of the main example Editing Technology # 10 Only “Polysilicon-2-Resistor” layer can connect to this port 85 Confirm that the connectivity of the other examples is all disallowed Editing Technology # 11 86 12. Editing a pin node for Polysilicon-2 high-resistor Editing Technology 8.6 Duplicate the Polysilicon-2 pin # 01 # 02 # 03 87 # 04 Editing Technology 88 Change the layer of each of the four boxes to “Polysilicon-2-HighResistor” Editing Technology # 05 89 Confirm the layer used Editing Technology # 06 # 07 90 Change the port name of each of the four examples Editing Technology # 08 # 09 91 Change the connectivity of the main example Editing Technology # 10 Only “Polysilicon-2-HighResistor” layer can connect to this port 92 Confirm that the connectivity of the other examples is all disallowed Editing Technology # 11 93 13. Editing a pure node for Polysilicon-2 resistor Editing Technology 8.6 Duplicate the Polysilicon-2 node # 01 # 02 # 03 94 # 04 Editing Technology 95 Editing Technology Change the function # 05 # 06 Change the layer of each box of the four examples # 07 96 Editing Technology # 08 Notice that the boarder style and color have been changed 97 Delete the current port “polysilicon-2” from each of the four examples Editing Technology # 09 As this node is to be a resistor, there must be two ports! poly-2-res-1 poly-2-res-2 98 After deleting the ports, only two boxes should exist for each example Editing Technology # 10 99 Add new ports using “artwork technology” Editing Technology # 11 Name the port # 12 100 Change the size of port so that it fits the left-side edge Editing Technology # 13 101 Move the port onto the left-side edge Editing Technology # 14 Similarly create a port on right-side edge # 15 102 Repeat the steps to add ports to the other examples Editing Technology # 16 103 Confirm the layers used Editing Technology # 17 104 Confirm the ports created Editing Technology # 18 105 Set the connectivity of the ports for the main example Editing Technology # 19 106 Confirm that the connectivity of the other examples is all disallowed Editing Technology # 20 107 Check the number of objects contained in this cell Editing Technology # 21 1 x 4 examples 1 x 4 examples 2 ports x 4 examples 2 ports x 4 examples 108 14. Editing a pure node for Polysilicon-2 high-resistor Editing Technology 8.6 Duplicate the Polysilicon-2 node # 01 # 02 # 03 109 # 04 Editing Technology 110 Editing Technology Change the function # 05 # 06 Change the layer of each box of the four examples # 07 111 Editing Technology # 08 Notice that the boarder style and color have been changed 112 Delete the current port “polysilicon-2” from each of the four examples Editing Technology # 09 As this node is to be a resistor, there must be two ports! poly-2-hres-1 poly-2-hres-2 113 After deleting the ports, only two boxes should exist for each example Editing Technology # 10 114 Create different components for the main example modifying the existing ones Editing Technology # 11 115 Copy and edit the components for the main example to create the others Editing Technology # 12 116 Assemble the components for each example Editing Technology # 13 117 Confirm the layers used Editing Technology # 14 118 Confirm the ports created Editing Technology # 15 119 Set the connectivity of the ports for the main example Editing Technology # 16 120 Confirm that the connectivity of the other examples is all disallowed Editing Technology # 17 121 Check the number of objects contained in this cell Editing Technology # 18 1 x 4 examples 2 x 4 examples 2 ports x 4 examples 2 ports x 4 examples 122 15. Editing a contact node Polysilicon-2 resistor Editing Technology 8.6 Duplicate the Metal-1-Polysilicon-2-Con node # 01 # 02 # 03 123 # 04 Editing Technology 124 Editing Technology Confirm the function # 05 # 06 125 Change the layer of each box of the four examples Editing Technology # 07 126 Editing Technology # 08 127 Confirm the outer-most box (Polysilicon-2 resistor) size as below Editing Technology # 09 10x10 14x10 10x14 14x14 128 Change the port name of the four examples Editing Technology # 10 # 11 129 Confirm the layers used Editing Technology # 12 130 Confirm the ports created Editing Technology # 13 131 Set the connectivity of the port for the main example Editing Technology # 14 132 Confirm that the connectivity of the other examples is all disallowed Editing Technology # 15 133 Check the number of objects contained in this cell Editing Technology # 16 134 12. Delete two scalable transistors to avoid errors when converting the library to a new technology Editing Technology This is a tentative patch. There must be another solution. 135 13. Convert the library to technology Editing Technology 8.2 # 01 # 02 # 03 136 Editing Technology # 04 Edit the component menu as you like # 05 137 # 06 Editing Technology Edit the component menu as you like Save this menu into the library 138 Editing Technology # 07 Skeleton of components are ready to use These are newly generated resistors Save this library 139 Reload the library “mocmos-plus.jelib” then convert it to technology Editing Technology # 08 Generate an XML file for permanent use of this technology # 09 140 Add the newly generated technology file in XML format to the Project Settings so that the technology is automatically loaded and created at the invocation of the tool. Editing Technology # 10 Specify the XML file you created 141 Editing Technology 142 01. Creating a 10-kΩ resistor from N-well Editing Technology Let’s create a new library “MyCircuit00” and “10K_N_Well” cell for {schematic} # 01 143 Editing Technology Edit “10K_N_Well{sch}” # 02 ① ② ③ Choose “N-Well Resistor” from the schematic component menu. Set “length” attribute to 120.0; “width” attribute to 12.0. That is, the aspect ratio is 10:1, which yields about 10kΩ if the sheet resistance is about 1kΩ/□. Export “L” and “R” port as shown. 144 Let’s create a new “10K_N_Well{lay}” cell Editing Technology # 03 Place a N-Well-Resistor-Node # 04 145 Change the length to 120.0 using the property editor Editing Technology # 05 146 Editing Technology # 06 Gee! “Width” and “Length” are interchanged! Is this a bug of Electric? Or… See the next slide for a fix. 147 Graphically stretch the shape by using Ctrl-B then … Editing Technology # 07 n-well-res-1 n-well-res-2 Both “Width” and “Length” are properly set. This shape will be the body of the resistor. Two ports are at both side ends. 148 Add the two contact terminals at both the ends Editing Technology # 08 149 Run NCC expecting an obvious error Editing Technology # 09 150 Connect a contact and a port of the resistor body by an “N-Well-Resistor Arc” Editing Technology # 10 Adjust the position of the contact so that the inside edge of the contact cut coincides with the outside edge of the resistor body # 11 151 Export the two terminals as “L” and “R” respectively and name the node Editing Technology # 12 node name 152 Confirm existence of expected objects Editing Technology # 13 153 Rerun NCC to confirm consistency. Editing Technology # 14 Check the 3-D view # 15 154 02. SPICE simulation using the N-Well10-kΩ resistor Editing Technology Let create a new cell for SPICE simulation # 01 Voltage divider is simulated. 155 Write a SPICE deck file Editing Technology # 02 156 Run the SPICE simulation with the schematic Editing Technology # 03 157 Edit the layout and run NCC Editing Technology # 04 158 Write a SPICE deck file Editing Technology # 05 159 Run the SPICE simulation with the layout Editing Technology # 06 Obviously, subcircuit information is missing! Finer tuning is necessary! The main theme of Part-III. Web search for “rnwod” results some SPICE model files for H-SPICE for example, visit http://ecow.engr.wisc.edu/cgi-bin/get/ece/541/lal/mm0355v.l 160 Editing Technology 03. Creating a 2-kΩ resistor from Polysilicon-2 high-resistor Let’s create a “2K_Poly2” cell for {schematic} # 01 161 Editing Technology Edit “2K_Poly2{sch}” # 02 ① ② ③ Choose “N-Poly Resistor” from the schematic component menu. Set “length” attribute to 55.0; “width” attribute to 5.0. That is, the aspect ratio is 11:1, which yields about 2kΩ if the sheet resistance is about 180Ω/□. Export “L” and “R” port as shown. 162 Let’s create a new “2K_Poly2{lay}” cell Editing Technology # 03 Place a Polysilicon-2-HighResistor-Node # 04 163 Change the length to 50.0 using the property editor Editing Technology # 05 164 Editing Technology # 06 Gee! “Width” and “Length” are interchanged again! Is this a bug of Electric? Or… See the next slide for a fix. 165 Graphically stretch the shape by using Ctrl-B then … Editing Technology # 07 poly-2-hres-1 poly-2-hres-2 Both “Width” and “Length” are properly set. This shape will be the body of the resistor. Two ports are at both side ends. 166 Add the two contact terminals at both the ends Editing Technology # 08 167 Run NCC expecting an obvious error Editing Technology # 09 168 Connect a contact and a port of the resistor body by an “Polysilicon-2-Resistor Arc” Editing Technology # 10 Adjust the position of the contact so that the inside edge of the contact pad (Poly2) coincides with the outside edge of the resistor body # 11 169 Export the two terminals as “L” and “R” respectively and name the node Editing Technology # 12 node name 170 Confirm existence of expected objects Editing Technology # 13 171 Rerun NCC to confirm consistency. Editing Technology # 14 Check the 3-D view # 15 172 04. SPICE simulation using the Poly2 2-kΩ resistor Editing Technology Let create a new cell for SPICE simulation # 01 Voltage divider is simulated. 173 Write a SPICE deck file Editing Technology # 02 174 Run the SPICE simulation with the schematic Editing Technology # 03 175 Edit the layout and run NCC Editing Technology # 04 176 Write a SPICE deck file Editing Technology # 05 177 Run the SPICE simulation with the layout Editing Technology # 06 Obviously, subcircuit information is missing! Finer tuning is necessary! The main theme of Part-III. Web search for “rnpo1rpo” results some SPICE model files for H-SPICE for example, visit http://www.ax-09.ru/gruppa/materials/biblioteka/Shemotehnika/Chung-Yu%20Wu_Analog%20Integrated%20Circuits%20-%20II/025.l.txt 178 th, 2009 Technology 05. Modify technology for {lay} Added this section on May 11Editing When creating a new layout cell, I should have selected “mocmos-plus” technology but selected “mocmos” instead # 01 Then, whenever I select a {lay} cell, “Components” menu alters to “mocmos” Because of this mistake, some exceptions were thrown when ran DRC, which led to the motivation to prepare the reference [1]. In fact, I noticed this mistake while running Electric under the Eclipse debugger. 179 Modify the technology of each {lay} cell Editing Technology # 02 180 Confirm that the technology has been set normally Editing Technology # 03 181 Editing Technology 182 01. Editing layer cells for N-well resistor Editing Technology Let’s assume these parasitic values # 01 183 02. Editing a pure node for N-well resistor Editing Technology 9.4.4 Let’s add a SPICE template; more specifically for LT-Spice # 01 ① ② ③ ④ ⑤ ⑥ This resistor is to be modeled by a subcircuit in SPICE where URC (Uniform RC-line) will be used as a base element. The subcircuit instance name will be “X followed by the node name.” The subcircuit has three terminals. Two of them will be connected to the ports attached to this node. The last one is always connected to “node number 0” which is GND. The subcircuit will take two parameters, that is, “L” and “W” which further accesses the physical size of this node by substituting $(length) and $(width). Such substitution is Electric’s job while generating a SPICE deck. “LAMBDA” is a physical scale (like 500nm) that is to be given by a .param command in a SPICE deck. A pair of curly braces { } is required to evaluate a parameter expression in LT-Spice modeled as URC n-well-res-2 n-well-res-1 0; GND 184 How they are translated into a SPICE deck # 02 exported port name “L” is connected to $(n-well-res-1) by an arc $(node_name)= $(length)=120.0 Editing Technology $(width)=12.0 exported port name “R” is connected to $(n-well-res-2) by an arc the subcircuit has to be defined somewhere (e.g. in a library) 185 A sample subcircuit definition Editing Technology # 03 Refer to LT-Spice manual for more details. 186 03. Simulation with the modified technology Editing Technology Modify the SPICE statements for a transient analysis at different temperatures # 01 187 Write a SPICE deck file Editing Technology # 02 188 Run the SPICE simulation with the layout Editing Technology # 03 For high frequency, this is rather an LFP than a voltage divider 189 Manually modify the SPICE deck for a step response Editing Technology # 04 190 Rerun the SPICE simulation for a step response Editing Technology # 05 Ramp-up takes some time 191 Let’s reduce the capacitance to 1/10 then… Editing Technology # 06 192 Rerun the same simulation as #03 Editing Technology # 07 Improved a bit, but … 193 Let’s reduce both the capacitance and the sheet resistance to 1/10 then… Editing Technology # 08 194 Rerun the same simulation as #03 Editing Technology # 09 Now, this can be seen as a voltage divider for this freq. 195 04. Editing a pure node for Polysilicon-2 high-resistor Editing Technology 9.4.4 Let’s add a SPICE template; more specifically for LT-Spice # 01 ① ② ③ ④ ⑤ ⑥ This resistor is to be modeled by a subcircuit in SPICE where URC (Uniform RC-line) will be used as a base element. The subcircuit instance name will be “X followed by the node name.” The subcircuit has three terminals. Two of them will be connected to the ports attached to this node. The last one is always connected to “node number 0” which is GND. The subcircuit will take two parameters, that is, “L” and “W” which further accesses the physical size of this node by substituting $(length) and $(width). Such substitution is Electric’s job while generating a SPICE deck. “LAMBDA” is a physical scale (like 500nm) that is to be given by a .param command in a SPICE deck. A pair of curly braces { } is required to evaluate a parameter expression in LT-Spice modeled as URC poly-2-hres-2 poly-2-hres-1 0; GND 196 Editing Technology How they are translated into a SPICE deck # 02 $(node_name)= exported port name “L” is connected to $(poly-2-hres-1) by an arc $(width)=5.0 $(length)=55.0 exported port name “R” is connected to $(poly-2-hres-2) by an arc the subcircuit has to be defined somewhere (e.g. in a library) 197 A sample subcircuit definition Editing Technology # 03 Refer to LT-Spice manual for more details. 198 05. Simulation with the modified technology Editing Technology Modify the SPICE statements for a transient analysis at different temperatures # 01 199 Write a SPICE deck file Editing Technology # 02 200 Run the SPICE simulation with the layout Editing Technology # 03 Response is much faster than N-well resistor divider 201 Manually modify the SPICE deck for a step response Editing Technology # 04 202 Rerun the SPICE simulation for a step response Editing Technology # 05 Ramp-up is also much faster than N-well resistor 203 Let’s reduce the capacitance to 1/10 then… Editing Technology # 06 204 Rerun the same simulation as #03 Editing Technology # 07 Almost perfect! 205 06. Works done so far Editing Technology As of March 28, 2009, I reached here. 206 Editing Technology 207 01. Preparing the source files Editing Technology 8.7 Clearly understand the steps to be followed for editing the design rules # 01 As this technology has been derived from mocmos, we have to refer to the original technology file describing the same, which resides in the source code JAR file. mocmos-plus.jelib ✔➀ graphically edit ✔➁ convert mocmos-plus.xml ➂ copy relevant lines ➃ manually edit to finish mocmos.xml (the full-set description of mocmos technology existing in the source code) 208 Get the source code Editing Technology # 02 This jar file contains the source codes; not “Binary” Unpack the archive file using “jar” command available in JDK (for example) # 03 Files and holders shown below will be extracted # 04 209 The original XML file is here Editing Technology # 05 Copy this file as mocmos-source.xml to the currently working directory and set on R/O flag Copy mocmos-plus.xml as mocmos-plus-work.xml Copy mocmos-plus.xml as mocmos-plus-org.xml and set on R/O flag # 06 “r” for safety I’m going to edit this file. I’m going to rename/restore these files while testing. 210 02. Comparing the two XML files Editing Technology Using an appropriate tool, examine the differences one by one # 01 The source (reference) XML file The XML file being edited 211 Find major differences in mocmos-source.xml and attempt to interpret them Editing Technology # 02 Some keywords are self-explanatory like ruleName, layerName, and value. layerNames (plural) followed by curly braces { } may make combination of layers. type may specify different type of design rules but its value like UCONSPA is not easy to guess what it means. when may specify when the rule is applied to but its value like SC is not very clear. the vertical bar | may mean logical OR. If you search the Electric manual for UCONSPA, you will find none. On the other hand, you will find plenty of candidate sections for SC. 212 03. Hacking the source code Editing Technology Let’s hack the source code # 01 Going to search all the *.java files (including subdirectories) for UCONSPA This tool is @ http://www.ghisler.com/ 213 Found 9 suspicious files Editing Technology # 02 Examine these files one by one with a text editor then … 214 Tips: Using Eclipse software development environment Editing Technology # 03 If you have the Eclipse software development environment as explained in the reference [1], you can also use its File Search function as shown here. This tool is very smart and useful! 215 Bingo! DRCTemplate.java declares enumeration types as DRCRuleType Editing Technology # 04 216 Similarly DRCTemplate.java declares enumeration types as DRCMode Editing Technology # 05 217 The meaning of type in the DRC table # 06 Keyword / Enumeration type Editing Technology Meanings NONE nothing chosen MINWID a minimum-width rule MINWIDCOND a conditional minimum-width rule NODSIZ a node size rule SURROUND a general surround rule SPACING a spacing rule SPACINGE an edge spacing rule CONSPA a connected spacing rule UCONSPA an unconnected spacing rule UCONSPA2D a spacing rule for 2D cuts CUTSURX X contact cut surround rule CUTSURY Y contact cut surround rule ASURROUND arc surround rule MINAREA minimum area rule MINENCLOSEDAREA enclosed area rule EXTENSION extension rule FORBIDDEN forbidden rule EXTENSIONGATE extension gate rule SLOTSIZE slot size rule 218 The meaning of when in the DRC table # 07 Keyword / Enumeration type Editing Technology Meanings NONE None ALL always M23 only applies if there are 2-3 metal layers in process M2 only applies if there are 2 metal layers in process M3 only applies if there are 3 metal layers in process M456 only applies if there are 4-6 metal layers in process M4 only applies if there are 4 metal layers in process M56 only applies if there are 5-6 metal layers in process M5 only applies if there are 5 metal layers in process M6 only applies if there are 6 metal layers in process M7 / M8 / M9 / M10 / M11 / M12 only applies if there are 7 / 8 / 9 / 10 / 11 / 12 metal layers in process, respectively AN only applies if analog (npn-transistor) rules are in effect AC only applies if alternate contact rules are in effect NAC only applies if alternate contact rules are not in effect SV only applies if stacked vias are allowed NSV only applies if stacked vias are not allowed DE only applies if deep rules are in effect SU only applies if submicron rules are in effect SC only applies if scmos rules are in effect 219 04. Interpretation of the DRC descriptions Editing Technology Let’s compare each line with the MOSIS rules # 01 http://www.mosis.com/Technical/Designrules/scmos/scmos-well.html 220 More precisely … Editing Technology # 02 ① ② ③ The minimum width for P-Well layer is defined in Rule 1.1. The rule type is abbreviated as MINWID. when DEep or SUbmicron rules are in effect, the Lambda value should be 12.0. 221 Furthermore … Editing Technology # 03 ① ② ③ The minimum width for P-Well layer is defined in Rule 1.1. The rule type is abbreviated as MINWID. when SCMOS rules are in effect, the Lambda value should be 10.0. 222 05. Writing our own DRC descriptions Editing Technology It is right time to start writing our own DRC descriptions in mocmos-plus.xml Good luck! As of May 11, 2009, I reached here. 223 Editing Technology 224 01. Writing our own DRC descriptions Editing Technology Write well-commented XML file for better understanding # 01 After a few trials, I noticed that incrementally testing these rules using Export DRC Deck and Import DRC Deck is a right way instead of restarting Electric again and again after editing XML files for “Added Technologies.” In other words, a DRC deck can be dynamically replaced while keeping Electric active. 225 02. Exporting the design rules Editing Technology My own DRC descriptions in mocmos-plus.xml will be loaded once at invocation of Electric To enable dynamically change the rules without restarting Electric, export a DRC deck # 01 Let’s export as “testDRC.xml” 226 Open the XML file to check whether rules are described as intended Editing Technology # 02 In “mocmos-plus.xml” file, I have named the customized rule as MOSISP (call capital) for easy eye catch. 227 03. Checking the MINWID rule Editing Technology Run DRC for 10K_N_Well{lay} view # 01 12.0 228 Change the value to constitute a minimum width violation Editing Technology # 02 Import the modified DRC Deck # 03 229 Rerun DRC for 10K_N_Well{lay} view Editing Technology # 04 12.0 230 Examine each error Editing Technology # 05 Looks reasonable 231 Restore the initial value for further testing Editing Technology # 06 Confirm that there is no violation # 07 232 04. Checking the CONSPA rule Editing Technology Create a new DRC_N_Well{lay} cell # 01 Place two instances of 10K resistor too close to each other # 02 4.0 233 Run DRC Editing Technology # 03 234 Examine each error Editing Technology # 04 Looks reasonable 235 Move the top object by dY= +2.0 and rerun DRC Editing Technology # 05 6.0 236 05. Checking the SPACING rules Editing Technology Place a pure P-Well object and change its size interactively # 01 7.0 pure P-Well 237 Run DRC Editing Technology # 02 238 Examine each error # 03 Editing Technology pure P-Well Looks reasonable 239 Move the P-Well object by dY= +3.0 and rerun DRC Editing Technology # 04 10.0 pure P-Well 240 Place a pure N-Well object and change its size interactively Editing Technology # 05 pure P-Well 5.0 pure N-Well 241 Run DRC Editing Technology # 06 242 Examine each error # 07 Editing Technology pure P-Well pure N-Well Looks reasonable 243 Move the N-Well object by dY= -5.0 and rerun DRC Editing Technology # 08 10.0 pure N-Well 244 Summary Editing Technology ① Studied a flow to incorporate a new user-defined technology to Electric including: a. Adding new TECHNOLOGY LAYERS b. Adding new TECHNOLOGY ARCS c. Adding new TECHNOLOGY NODES d. Writing SPICE Template to work with LT-Spice ② Studied how to manually edit an XML file for user-defined DRC. 245 To Do Editing Technology ① More design rules have to be added and tested against different test cases. ② More realistic physical parameters are required to improve usefulness. ③ And many more whatever insufficient! [The End of File] 246