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Background Basics of semiconductor physics Basics of elementary linear circuit analysis Fundamental concepts will however be reviewed A. Rivetti – INFN Sezione di Torino Lecture I Lecture I: • Semicondunctor properties review • MOS transistor physics A. Rivetti – INFN Sezione di Torino Intrinsic silicon 28.086 14 Si Silicon properties at 300K +4 +4 +4 +4 resistivity: 2.3 ·105 W·cm electron mobility: 1500 cm2/V·s hole mobility: 475 cm2/V·s e- diffusion constant: 34 cm2/s h diffusion constant: 13 cm2/s intrinsic concentration: 1.45·1010 Energy gap: 1.12 eV A. Rivetti – INFN Sezione di Torino Silicon properties P-doped silicon +3 +4 +4 +3 It is possible to increase the hole population by introducing into the lattice atoms which have one valence electron less than the number needed to form complete bonds with the silicon atoms. Typical p-dopant (acceptors) are: boron, gallium and indium A. Rivetti – INFN Sezione di Torino Silicon properties N-doped silicon +5 +4 +4 +5 It is possible to increase the epopulation by introducing into the lattice atoms which have one valence electron more than the number needed to form complete bonds with the silicon atoms. Typical n-dopant (donors) are: phosphorus, arsenic and antimony A. Rivetti – INFN Sezione di Torino Silicon properties The pn junction p n W1 W2 A. Rivetti – INFN Sezione di Torino pn junction review Built-in potential p n W1 W2 N N ln V ni A 0 T 2 D V T kT q A. Rivetti – INFN Sezione di Torino pn junction review Depletion region V- V V V R W1 p n W1 W2 2 ( V R ) 0 q N A 1 N N D A W2 V+ 2 ( V R ) 0 q N D 1 N N A D A. Rivetti – INFN Sezione di Torino pn junction review Junction capacitance VV V V R ---- p - - + + W1 Cj A q N N 2( N N A A V+ n W2 1 D D ) V 0 R C 1 V j0 R 0 A. Rivetti – INFN Sezione di Torino pn junction review Lecture I Lecture I: • Semicondunctor properties review • MOS transistor physics A. Rivetti – INFN Sezione di Torino The nMOS transistor Gate Source Drain polisilicon silicon dioxide n+ diffusions p- substrate Bulk A. Rivetti – INFN Sezione di Torino The MOS transistor The nMOS transistor Source Gate G Drain S Bulk W D L A. Rivetti – INFN Sezione di Torino The MOS transistor Accumulation Source Gate Drain - - - - + + + + + + + +- - - - Bulk Keep VS =VB = VD = 0 and refer all the voltages to the source If VGS < 0, the device is off Positive mobile carriers (holes) accumulate underneath the gate Source and drain are separated from the bulk by a depletion region (negative fixed ions) A. Rivetti – INFN Sezione di Torino The MOS transistor Depletion Gate Source ---- Drain - - - - - - - ----- If VG > VS (VGS > 0), the holes are repelled and a depletion region is formed The charge on the gate is mirrored by negative ions Bulk A. Rivetti – INFN Sezione di Torino The MOS transistor Inversion Source Gate Drain -- --- -- --- -- --- -- -- - -- - - ---- If VGS > VTH0, electrons are attracted underneath the gate The charge on the gate is mirrored by negative free carries Source and drain still separated from the bulk by a depletion region Bulk If VDS > 0 current can flow A. Rivetti – INFN Sezione di Torino The MOS transistor The nMOS resistor Source Gate Drain Q -C -WL-(V - V ) -- - - ---ox Bulk GS TH 0 Charge in the channel: Q C ox WL(V GS V TH 0) Current: Q / t V DS v E t L/v n n L W (V V ) V C I DS ox GS TH 0 DS n L If VDS is very small, the device acts as a voltage controlled linear resistor A. Rivetti – INFN Sezione di Torino The MOS transistor NMOS I-V characteristic For the moment, Vsourse is kept at zero Vdrain Vdrain Vgate Vgate Vsource A. Rivetti – INFN Sezione di Torino The MOS transistor Linear region IDS (A) W/L = 100m/10m VGS = 2.5 V 150 130 VGS = 2 V 110 VGS = 1.5 V 90 70 50 VGS = 1 V 30 10 VGS = 0.5 V -10 0 10 20 30 40 50 VDS (mV) A. Rivetti – INFN Sezione di Torino The MOS transistor Extending the linear region IDS (A) W/L = 100m/10m 400 VGS = 1.25V 300 200 100 0 0 100 200 300 400 VDS (mV) A. Rivetti – INFN Sezione di Torino The MOS transistor Transistor test bench Vdrain Vgate Vsource A. Rivetti – INFN Sezione di Torino The MOS transistor A more accurate formula Source Gate Drain Channel is not uniform Consider a small section dL - - - - - - - - - - - - -- - - - Bulk dQ C OX WdL(V GS V V TH 0) IdL n COX W (V GS V V TH 0)dV 2 W DS V I DS n C OX V GS V TH 0 V DS L 2 In the “linear” region, the drain-source current is still a strong function of VDS. The device acts as a voltage controlled non-linear resistor A. Rivetti – INFN Sezione di Torino The MOS transistor Extending the linear region IDS (A) W/L = 100m/10m 400 This region is well predicted by: IDS = n COX W [(VGS -VTH0)VDS L VDS2 ] 2 300 200 100 0 0 100 200 300 400 VDS (mV) A. Rivetti – INFN Sezione di Torino The MOS transistor Full characteristic IDS (A) This region is not predicted by: IDS = n COX W [(VGS -VTH0)VDS L VDS2 ] 2 400 VGS = 1.25 V 300 200 100 0 0 1 2 2.5 VDS (V) A. Rivetti – INFN Sezione di Torino The MOS transistor Saturation region Source Gate Drain - - - - - - - - - - - - -- - - - When VDS=VGS – VTH0 the channel is pinched-off The maximum current is: 1 W I DS n C OX V GS V TH 0 2 L 2 Bulk In the saturation region (VDS > VGS – VTH ) the current is not controlled anymore by VDS . The device acts as a voltage controlled current source A. Rivetti – INFN Sezione di Torino The MOS transistor IDS (A) Saturation voltage 3 mA VGS = 2.5 V 1 mA - 1 mA 400 A VGS = 1.25 V 200 A 0 A 0 1 2 2.5 VDS (V) A. Rivetti – INFN Sezione di Torino The MOS transistor Effect of VDS in saturation 400A IDS (A) 0 355.75 0 2.5 355.71 355.67 355.63 355.59 355.55 2 2.1 2.2 2.3 2.4 2.5 VDS (V) A. Rivetti – INFN Sezione di Torino The MOS transistor Channel length modulation Source Gate Drain - - - - - - - - - - - - -- - - - In saturation, VDS still modifies the effective channel length The current is: 1 W I DS n C OX V GS V TH 0 2 L 1 V 2 Bulk In the saturation region VDS slightly modifies the effective channel length, modulating the current. The device acts as a voltage controlled current source with a finite output impedance A. Rivetti – INFN Sezione di Torino The MOS transistor DS Decreasing channel length IDS (mA) W/L = 100m/1m 3.6580 3.6500 3.6420 2 2.1 2.2 2.3 2.4 2.5 VDS (V) A. Rivetti – INFN Sezione di Torino The MOS transistor Effect of VGS IDS (mA) W/L = 100m/1m 30 20 10 0 -10 0 1 2 2.5 VDS (V) A. Rivetti – INFN Sezione di Torino The MOS transistor The threshold voltage VTH = fMS + 2fF + QB COX - QOX COX A. Rivetti – INFN Sezione di Torino The MOS transistor The body effect What happens to the current if we raise Vsource and Vgate simultaneously, keeping VGS and VDS constant? Vdrain Vgate Vsource A. Rivetti – INFN Sezione di Torino The MOS transistor The body effect A. Rivetti – INFN Sezione di Torino The MOS transistor The body effect Source Gate Drain - - - - - - - - - - - - -- - - - What happens if VSB is not zero ? If VS is increased, the depletion region becomes wider (more uncovered negative ions) Extra positive charge is needed on the gate to compensate for this negative ions and the threshold voltage is increased 1 W n C OX I DS V GS V TH 2 L Bulk 1 V 2 DS Still holds, but VTH is now: VTH = VTH0 + g ( VSB + 2fF - 2fF ) g= 2qSINA COX A. Rivetti – INFN Sezione di Torino The MOS transistor The pMOS transistor Gate Source Drain polisilicon silicon dioxide p+ diffusions n- substrate Bulk A. Rivetti – INFN Sezione di Torino The MOS transistor The pMOS transistor Source Gate G Drain S W D L Bulk Nwell A. Rivetti – INFN Sezione di Torino The MOS transistor CMOS technologies G G S W L D S W D L Nwell Both pmos and nmos devices on the same chip. This is fundamental for both digital and analog circuits A. Rivetti – INFN Sezione di Torino The MOS transistor CMOS technologies G S W L G D S W D L In a nwell process, NMOS devices share the same substrate which is the wafer substrate A. Rivetti – INFN Sezione di Torino The MOS transistor CMOS technologies G S W G D S L Nwell W D L Nwell Pmos devices need a local substrate, that may be shared by more pmos transistors A. Rivetti – INFN Sezione di Torino The MOS transistor Process trends in CMOS technologies Year 1992 1995 1999 2001 2003 Minimum size (m) Tox (nm) 0.5 0.35 0.25 0.18 0.13 9-12 7-10 5-7 3-4 2-3 Metal levels 4 5 6 7 8 Supply (V) 3.3-5 2.5-3.3 2.5-3.3 1.8-2.5 1.2-1.8 200 200 300 300 Wafer 200 diameter (mm) A. Rivetti – INFN Sezione di Torino The MOS transistor MOS in real life... A. Rivetti – INFN Sezione di Torino The MOS transistor Metal interconnections A. Rivetti – INFN Sezione di Torino The MOS transistor Passive components In IC technologies is relatively easy to fabricate resistor and capacitors Metal to metal capacitor Very linear Typical density: 0.6 – 0.8 fF/m2 A. Rivetti – INFN Sezione di Torino The MOS transistor Resistors t W L R =r A L R =r Wt r R= t L W L R = R• W R•ranges typically from 10 W/sq to 2000 W/sq A. Rivetti – INFN Sezione di Torino The MOS transistor