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EX 3 DIGITAL ELECTRONICS (CLASS 1BT4-1BM1)
G________
After completing the task and studying Unit 1.6, you will be able to (tick all that apply):
 Explain the concept of logic family to build digital circuits and the obsolescence curve associated to a given
logic family.
 Explain the evolution of integrated circuits, the scales of integration (SSI, MSI, LSI, etc.) and the Moore Law.
 Calculate the electrical characteristics of classic digital integrated circuits, such as:
o
power supplies and logic voltage levels,
o
noise margins (NML and NMH),
o
propagation delays and transition times,
o
quiescent currents and power dissipation,
o
maximum frequency of operation of a digital circuit,
o
tri-state gates.
 Use digital timing diagrams to specify or verify circuit operation.
 Explain the basics of CMOS technology for realizing basic gates. Using a transistor as a switch (ON/OFF).
 Capture a schematic in Proteus using devices from a given digital logic family, and run the simulation.
 Use the (SPICE based) virtual laboratory software Proteus-VSM1 to calculate electrical characteristics,
specially the transient graph based analysis type.
 Produce a written solution for the exercise using the instructions from:
http://epsc.upc.edu/projectes/ed/unitats/unitat_1_1/Criteris_Correccio_Exercici.pdf
 Work cooperatively in a team of 3 members using the method described in:
http://epsc.upc.edu/projectes/ed/problemes/metode_resolucio_cooperativa_recomanat.pdf
Write down the most significant questions you have had while or after completing the task:
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Proteus-VSM is the proprietary software in use for the whole course: http://www.labcenter.com for having effectively a
“digital circuits’ laboratory in the classroom”
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STATEMENT:
My signature below indicates that I have (1) made equitable contribution to EX 3 as a member of the group, (2) read
and fully agree with the contents (i.e., results, conclusions, analyses, simulations) of this document, and (3)
acknowledged by name anyone outside this group who assisted this learning team or any individual member in
completing this document.
Today’s date: __________________
Active members
Roles: (reporter, simulator, etc.)
(1) ___________________________
_______________
(2) ___________________________
_______________
(3) ___________________________
_______________
Acknowledgement of individual(s) who assisted this group in completing this document:
(1) _______________________
(2) _______________________
Group work
Study time
Sessions TGA,
TGB
Individual
Sessions
TGC
Student 1
(in hours)
Student 2
Student 3
A) First, figure out which is the internal electronic circuit of a logic
gate … How is possible to integrate millions of transistors into a
single chip?
Mixed signal integrated circuit which includes a built-in sensor for
DIDDQ testing and a standard cell DSP with 250000 transistors as
Circuit Under Test.
Technology: CMOS 0.18 m, size: 0.9 mm2
Designed by DEE engineers and fabricated by Philips
(2)
DIDDQ testing is a method able to detect defects producing small
increases in leakage current on top of high background
Fig. 1 From page photograph and explanation of the Department of Electronic Engineering web site at http://wwweel.upc.edu/. You can gather more information about microelectronics through the power point presentation from Prof.
Salvador Manich referenced in Unit 1.6 (http://tec.upc.es/SetCiencies/NanoElectronics.ppt)
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Department of Electronic Engineering, UPC, http://www-eel.upc.edu/
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a) Explain how the CMOS3 logic gates4 represented in Fig. 2 work. And determine which their equivalent logic
symbols are. Invent a CMOS circuit for the tri-state inverter in Fig. 2d.
b) Deduce the CMOS circuit for the gates used in the circuit in Fig. 3 (inverter, 3-input AND, 4-input NOR, etc.).
Count the number of MOS transistors in the chip.
CMOS gate
a)
b)
d)
c)
Fig. 2 Some internal circuitry for CMOS logic gates
B) Second, analyse the electrical characteristics of a given digital
circuit …
Circuit shown Fig. 3 represents the internal structure of the chip SN74LS280, a MSI (medium scale of integration)
chip as presented by ON Semiconductor in its datasheet. Let us to use it for understanding concepts as: power
dissipation; number of gate levels and transmission delays; transfer function and voltage levels; timing diagrams (a
graphical representation that shows the propagation of the signals as a function of time); and other important
electrical characteristics of digital circuits.
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http://www.opamp-electronics.com/tutorials/digital_theory_ch_003.htm
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Here you can find Java applets that will simulate the gate’s operation http://tams-www.informatik.unihamburg.de/applets/hades/webdemos/05-switched/40-cmos/chapter.html (HADES)
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Fig. 3 Gate network and input and output signals
c) Find the chip datasheet somewhere in the Internet and print only the 2 or 3 most significant pages which
contain the circuit description and electrical characteristics. Explain the chip’s features in half a sheet.
d) With respect to the output ODD, analyse the internal circuit in Fig. 3: deduce the algebraic equation, apply
Boole Algebra, and obtain its truth table as a function of the inputs (nothing new but copying the same EX2’s
methodology). Verify your results by simulation. NOTE: try to analyse first one of the internal blocks.
e) Deduce the timing diagram of ODD when applying the waveforms of Fig. 4 (evidently applying results from
above).
f)
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Redesign the function EVEN as a 3-level gate circuit (for instance, using only NAND, NOR, NOT-AND-OR or
NOT-OR-AND) using LSTTL logic.
Fig. 4 Input signals to deduce a timing diagram for output O2
g) Simulate these two circuits that implement the functionEVEN: (1) the one in Fig. 3 (for example, using the
Proteus model for this chip); and (2) the one designed in f) by you. Compare both simulations and determine
whether these two circuits have the same truth table and electrical characteristics.
C) And third, characterise electrically your own circuit …
h) Use one of your designs in EX2. Capture it in Proteus using chips of the same logic family, for instance LSTTL
or CMOS 4000 series. Obtain from the datasheets the characteristics of a single gate of the technology you
have chosen when powered at VCC = 5V: quiescent current IDD, propagation delay time tPLH and tPHL, input
voltage VIH and VIL, output voltage VOH and VOL. And simulate your circuit.
i)
Draw the input-output transfer function and obtain the noise margins high (NMH) and low (NML).
j)
Determine the static power consumption of your circuit.
k) Deduce the slowest output of your circuit and calculate the maximum frequency of operation of your circuit.
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l)
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Apply an up-to-the-limit square waveform to determine through a graphical digital simulation the maximum
frequency of operation and compare results with k)
D) What to do in you need a chip which is no
longer available in the market?
m) (demonstration) For example, the classic HEF4532B is practically obsolete, thus, it is not manufactured and
can not be found in the marketplace. Implement the HEF4532B chip functionality into a simple
programmable logic device (sPLD) GAL22V10 like the one partially reproduced in Fig. 5. See Units 1.14 and
1.15. The idea is:
(a) Start a VHDL-only project in the ispLEVER from Lattice Semiconductor targeted to a GAL22V10
device.
(b) Simulate it using Mentor Graphics ModelSim Student Ed. or ALDEC Active-HDL student Ed.
(c) Synthesise and generate the sPLD configuration JED file.
(d) Capture the schematic in Proteus and run the simulation.
n) (demonstration) Implement the HEF4532B chip functionality into a ROM memory. See Unit 2.11.
Fig. 5 Partial details of the GAL22V10 simple programmable logic device (sPLD)
GAL22V10
Parallel port to program the sPLD
using a PC and the ispVM System
software from Lattice
TopMax universal chip programmer
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Fig. 6 GAL22V10 training board to experiment with sPLD devices and a commercial
universal programmer (Unit 1.14 and Unit -15)
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DIGITAL ELECTRONICS
G________
Working plan5 for solving the exercise EX 3
Explain succinctly how the cooperative group has carried out the exercise: i.e., which was your working plan; in
which way did you divide the task fairly so that more or less all of you were doing a similar amount of work; how did
you learn each other’s materials; what was worked out in class time (sessions A and B) and what was resolved in
sessions C; and so on... write down also your impressions or opinions on the subject and how your group work is
going6 ...
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This document, filled before delivering the exercise, will be included in the group learning portfolio
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Check similar documents in http://epsc.upc.edu/projectes/ed/ED/unitats/ED_05-06_Q1_Autoavaluacio_Grup_Base.pdf and
http://epsc.upc.edu/projectes/ed/ED/unitats/que_va_malament_al_grup.pdf
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Active members’ signatures
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