Download Chapter 3 Special-Purpose Diodes

ET 162 Circuit Analysis
Series and Parallel Networks
Electrical and Telecommunication
Engineering Technology
Professor Jang
Acknowledgement
I want to express my gratitude to Prentice Hall giving me the permission
to use instructor’s material for developing this module. I would like to
thank the Department of Electrical and Telecommunications Engineering
Technology of NYCCT for giving me support to commence and complete
this module. I hope this module is helpful to enhance our students’
academic performance.
OUTLINES
 Introduction to Series-Parallel Networks
 Reduce and Return Approach
 Block Diagram Approach
 Descriptive Examples
 Ladder Networks
Key Words: Series-Parallel Network, Block Diagram, Ladder Network
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Series-Parallel Networks –
Reduce and Return Approach
Series-parallel networks are networks
that contain both series and parallel
circuit configurations
For many single-source, series-parallel
networks, the analysis is one that
works back to the source, determines
the source current, and then finds its
way to the desired unknown.
FIGURE 7.1 Introducing the
reduce and return approach.
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Series-Parallel Networks
Block Diagram Approach
The block diagram
approach will be
employed throughout
to emphasize the fact
that combinations of
elements, not simply
single resistive
elements, can be in
series or parallel.
FIGURE 7.2 Introducing the block diagram approach.
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Ex. 7-1 If each block of Fig.7.3 were a single resistive element, the
network of Fig. 7.4 might result.
FIGURE 7.4
FIGURE 7.3
6k I s 
1
1
 I s  9mA  3 mA
6k  12k 3
3
12k I s 
2
2
IC 
 I s  9mA  6 mA
12k  6k 3
3
IB 
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Ex. 7-2 It is also possible that the blocks A, B, and C of Fig. 7.2 contain
the elements and configurations in Fig. 7.5. Working with each region:
A : RA  4 
B : RB  R2 // R3  R2 // 3
R 4
 
2
N
2
C : RC  R4  R5  R4,5  2 
FIGURE 7.5
R 2
RB // C  
1
N
2
RT  RA  RB // C  4   1   5 
ET162 Circuit Analysis
FIGURE 7.6
E 10 V
Is 

2A
RT 5 
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I A  Is  2 A
I A Is 2 A
I B  IC 
 
1 A
2
2
2
IB
I R2  I R3 
 0.5 A
2
FIGURE 7.6
VA  I A RA  2 A4    8 V
VB  I B RB  1 A2    2 V
VC  VB  2 V
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Ex. 7-3 Another possible variation of Fig. 7.2 appears in Fig. 7.7.
RA  R1// 2


9  6  

9  6
54 
 3.6 
15
RB  R3  R4 // 5

9  3  
 4 
9   3
 4  2  6 
RC  3 
FIGURE 7.7
FIGURE 7.8
RT  RA  RB // C

6  3  
 3.6  
6   3
 3.6   2   5.6 
E 16.8V
Is 

3 A
RT 5.6 
ET162 Circuit Analysis – Series and parallel networks
I A  Is  3 A
8
Applying the current divider rule yields

RC I A
3  3 A
IB 

1 A
RC  RB 3   6 
By Kirchhoff ' s current law,
IC  I A  I B  3 A 1 A  2 A
By Ohm ' s law,
VA  I A RA  3 A3.6    10.8 V
V  I R  V  I R  2 A3    6 V
R2 I A
I1 
R2  R1

6  3 A

6  9
 1.2 A
I 2  I A  I1
 3 A  1 .2 A
 1.8 A
Series-Parallel Networks - Descriptive Examples
Ex. 7-4 Find the current I4 and the voltage V2 for the network of Fig. 7.2 .
E
E 12V
I4 


 1.5 A
RB R4 8 
RD  R2 // R3  3  // 6   2 
RD E
V2 
RD  RC

2  12V 

 4V
FIGURE 7.9
2  4
FIGURE 7.10
ET162 Circuit Analysis – Series and parallel networks
FIGURE 7.11
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Ex. 7-5 Find the indicated currents and the voltages for the network of Fig. 7.12 .
FIGURE 7.12
R 6
R1// 2  
3
N
2

3  2   6 
RA  R1// 2 // 3 

 1.2 
3  2 
5

8  12   96 
RB  R4 // 5 

 4.8 
8   12 
20
ET162 Circuit Analysis – Series and parallel networks
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FIGURE 7.13
11
RT  R1// 2 // 3  R4 // 5
 1 .2   4 .8   6 
E 24 V
Is 

4A
RT
6
FIGURE 7.13
V1  I s R1// 2 // 3  4 A1.2    4.8V
V2  I s R4 // 5  4 A4.8    19.2V
V5 19.2 V
I4 

 2.4 A
R4
8
ET162 Circuit Analysis – Series and parallel networks
V2 V1 4.8V
I2 


 0.8 A
R2 Boylestad
R2
6
12
Ex. 7-6 a. Find the voltages V1, V2, and Vab for the network of Fig. 7.14.
b. Calculate the source current Is.
a.
FIGURE 7.14
FIGURE 7.15
Applying the voltage divider rule yields Applying Kirchhoff ' s voltage law around
the indicated loop of Fig.
512V 

R1 E
V1 

 7.5 V
 V1  V3  Vab  0
R1  R2
5  3
Vab  V3  V1  9V  7.5V  15
.V
612V 

R3 E
V3 

 9V
R3  R4
6  2
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b.
By Ohm' s law,
V1 7.5V
I1 

 15
. A
R1
5
V3 9V
I3 

 15
. A
R3 6 
ET162 Circuit Analysis – Series and parallel networks
Applying Kirchhoff’s current law,
Is = I1 + I3 = 1.5A + 1.5A = 3A
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Ex. 7-7 For the network of Fig. 7.16, determine the voltages V1 and V2 and
current I.
FIGURE 7.17
FIGURE 7.16
V2 = – E1 = – 6V
Applying KVL to the loop
E1 – V1 + E2 = 0
V1 = E2 + E1 =18V + 6V = 24V
Applying KCL to node a yields
I  I1  I 2  I 3

V1 E1
E1


R1 R4 R2  R3
24V 6V
6V



6  6  12 
 4 A  1 A  0.5 A  55
. A
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Ex. 7-9 Calculate the indicated currents and voltage of Fig.7.17.
FIGURE 7.17.
E
72V
72V
I5 


 3mA
R(1, 2,3) // 4  R5 12k  12k 24k
V7 
9 kΩ
I6 
R7 //(8,9) E
R7 //(8,9)  R6
V7
R7 //(8,9)


4.5k 72V  324V


4.5k  12k
16.5
 19.6V
19.6V
 4.35mA
4.5k
Is = I5 + I6 = 3 mA +4.35 mA = 7.35 mA
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Ex. 7-10 This example demonstrates the power of Kirchhoff’s voltage law
by determining the voltages V1, V2, and V3 for the network of Fig.7.18.
FIGURE 7.17.
FIGURE 7.18.
For the path 1,  E1  V1  E 3  0
V1  E1  E 3  20V  8V  12 V
For the path 2,  E 2  V1  V2  0
V2  E 2  V1  5V  12V  7 V
For the path 3,  V3  V2  E 3  0
V3  E 3  V2  8V  ( 7V )  15 V
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Series-Parallel Networks – Ladder Networks
A three-section ladder appears in Fig. 7.19.
FIGURE 7.19. Ladder network.
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FIGURE 7.20.
RT  5   3   8 
240V
E
Is 

 30 A
RT
8
FIGURE 7.21.
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I1  I s
I s 30 A
I3 

 15 A
2
2
6  I 3
6
I6 
 15 A  10 A
6   3 9
V6  I 6 R6  10 A2   20 V
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