Download Multiple-gate SOI MOSFETs

Solid-State Electronics 48 (2004) 897–905
www.elsevier.com/locate/sse
Multiple-gate SOI MOSFETs
Jean-Pierre Colinge
*
Department of Electrical and Computer Engineering, University of California, Davis, CA 95616, USA
The review of this paper was arranged by Prof. S. Cristoloveanu
Abstract
In an ever increasing need for higher current drive and better short-channel characteristics, silicon-on-insulator
MOS transistors are evolving from classical, planar, single-gate devices into three-dimensional devices with multiple
gates (double-, triple- or quadruple-gate devices). The evolution and the properties of such devices are described and
the emergence of a new class of MOSFETs, called triple-plus (3þ )-gate devices offer a practical solution to the problem
of the ultimate, yet manufacturable, silicon MOSFET.
Ó 2004 Elsevier Ltd. All rights reserved.
Keywords: SOI; Silicon-on-insulator; MOSFET
1. Introduction
The first SOI transistor dates back to 1964. These
were partially depleted devices fabricated on siliconon-sapphire (SOS) substrates [1]. SOS technology was
successfully used for numerous military and civilian
applications [2] and is still being used to realize commercial HF circuits in fully depleted CMOS [3–5]. Once
the first SOI substrates (the insulator is now silicon
dioxide) were available for experimental MOS device
fabrication, partially depleted technology the natural
choice derived from SOS experience. Partially depleted
CMOS continues to be used nowadays and several
commercial IC manufacturers have SOI products and
product lines such as microprocessors and memory
chips. Variations on the partially depleted SOI MOSFET
theme include devices where the gate is connected to the
floating body. These devices, which have been called
‘‘voltage-controlled bipolar-MOS device’’ [6], ‘‘hybrid
bipolar-MOS device’’ [7,8], ‘‘gate-controlled lateral BJT’’
[9], ‘‘multiple-threshold CMOS’’ [10], ‘‘dynamic threshold MOS’’ [11], or ‘‘variable-threshold MOS’’ [12] have
ideal subthreshold characteristics, reduced body effect,
improved current drive, and superior HF characteristics
*
Tel.: +1-530-752-7968; fax: +1-530-752-8428.
E-mail address: [email protected] (J.-P. Colinge).
[13]. They are mostly used for very low-voltage (0.5 V)
applications [14]. The first fully depleted SOI MOSFET
date back to the early 1980’s where it was quickly
established that these devices exhibited superior transconductance, current drive and subthreshold swing
[15,16]. In addition to the ‘‘regular’’, inversion-mode
devices it was shown that accumulation-mode FD SOI
MOSFETs can be fabricated. These possess characteristics comparable to those of inversion-mode devices [17].
Fig. 1 shows the SOI MOSFETs ‘‘family tree’’. The first
publication describing a double-gate SOI MOSFET
dates back to 1984. The device received the acronym
XMOS because of the resemblance of the structure with
the Greek letter N [18]. This initial paper predicted the
good short-channel characteristics of such a device. The
first fabricated double-gate SOI MOSFET was the ‘‘fully
DEpleted Lean-channel TrAnsistor (DELTA, 1989)’’,
where the silicon film stands vertical on its side (Fig. 2)
[19]. Later implementations of vertical-channel, doublegate SOI MOSFETs include the FinFET [20], the
MFXMOS [21], the triangular-wire SOI MOSFET [22]
and the D-channel SOI MOSFET [23]. Volume inversion
was discovered in 1987 [24], and the superior transconductance brought about by this phenomenon were first
experimentally observed in 1990 in the first practical
implementation of a planar double-gate MOSFET called
the ‘‘gate-all-around’’ (GAA) device [25] (Fig. 3).
0038-1101/$ - see front matter Ó 2004 Elsevier Ltd. All rights reserved.
doi:10.1016/j.sse.2003.12.020
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J.-P. Colinge / Solid-State Electronics 48 (2004) 897–905
Fig. 1. SOI MOSFET family tree.
Fig. 3. Gate-all-around (GAA) MOSFET.
Fig. 2. DELTA/FinFET structure.
The triple-gate MOSFET is a thin-film, narrow silicon island with a gate on three of its sides. Implementations include the quantum-wire SOI MOSFET [26]
and the tri-gate MOSFET [27]. Improved versions feature either a field-induced, pseudo-fourth gate such as
the P-gate device [28] and the X-gate device [29] (Fig. 4).
The structure that theoretically offers the best possible control of the channel region by the gate is the surrounding-gate MOSFET. Such a device is usually
fabricated using a pillar-like silicon island with a vertical-channel. Such devices include the CYNTHIA device
(circular-section device, Fig. 5) [30] and the pillar surrounding-gate MOSFET (square-section device) [31].
J.-P. Colinge / Solid-State Electronics 48 (2004) 897–905
ID ¼ ID0
Fig. 4. Triple-gate SOI MOSFET.
W þ 2tsi
P
899
ð1Þ
where ID0 is the current of a unit-width, planar, singlegate device, and where W is the width of each individual
finger, tsi is the silicon film thickness, and P is the finger
pitch (Fig. 6). The FinFET device achieves high current
drive through the use of a relatively thick silicon thickness. In that device there is no current flow at the top of
the silicon island, such that ID ¼ ID0 ð2tsi =P Þ. In triplegate devices where tsi ¼ W the finger pitch needs to be
smaller than 3W to obtain a larger current drive than in
a single-gate, planar device occupying the same silicon
real estate.
3. Short-channel effects
It is possible to predict how small the silicon film
thickness should be in multiple-gate devices to avoid
short-channel effects (or, at least, to maintain a decent
subthreshold swing). Subthreshold swing degradation
and other short-channel effects are caused by the
encroachment of electric field line from the drain on the
channel region, thereby competing for the available
depletion charge, and reducing the threshold voltage.
The potential distribution in the channel of a fully depleted SOI MOSFET is governed by Poisson’s equation:
Fig. 5. CYNTHIA/surrounding-gate MOSFET structure.
2. Current drive of multiple-gate SOI MOSFETs
The current drive of multiple-gate SOI MOSFETs is
essentially proportional to the total gate width. For instance, the current drive of a double-gate device is
double that of a single-gate transistor with same gate
length and width. In triple-gate and vertical double-gate
structures all individual devices need to have the same
thickness and width. As a result the current drive is fixed
to a single, discrete value, for a given gate length. To
drive larger currents multi-fingered devices need to be
used. The current drive of a multi-fingered MOSFET is
then equal to the current of an individual device multiplied by the number of fingers (also sometimes referred
to as ‘‘fins’’ or ‘‘legs’’). Considering a pitch P for the
fingers, the current per unit device width is given by:
d2 Uðx; y; zÞ d2 Uðx; y; zÞ d2 Uðx; y; zÞ qNa
þ
þ
¼
dx2
dy 2
dz2
esi
ð2Þ
Fig. 7 shows how the gates and the drain compete for
the depletion charge. Gate control is exerted in the yand z-directions and competes with the variation of
electric field in the x-direction due to the drain voltage.
In the case of a wide single- or double-gate device,
dU
¼ 0, such that we can write:
dz
d2 Uðx; yÞ d2 Uðx; yÞ qNa
þ
¼
dx2
dy 2
esi
ð3Þ
The one-dimensional analysis of a fully depleted device
yields a parabolic potential distribution in the silicon
film in the y (vertical) direction. Assuming a similar
distribution in the y-direction for a two-dimensional
analysis we can write [32]:
Fig. 6. Cross-section of a multi-fingered triple-gate MOSFET (left) and SEM picture of the fingers (right).
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J.-P. Colinge / Solid-State Electronics 48 (2004) 897–905
Fig. 7. Definition of coordinate system in a multiple-gate
device. Gate-induced fields are in the x- and z-directions.
Drain penetration field is in the y-direction.
Uðx; yÞ ¼ c0 ðxÞ þ c1 ðxÞy þ c2 ðxÞy 2
ð4Þ
Let us first examine the case of a single-gate SOI device.
The boundary conditions to Eq. (4) are [33]:
1. Uðx; 0Þ ¼ Uf ðxÞ ¼ c0 ðxÞ where Uf ðxÞ is the front surface potential;
U ðxÞU
2. dUðx;yÞ
jy¼0 ¼ eeoxsi f tox gs ¼ c1 ðxÞ where Ugs ¼ Vgs VFBF
dy
is the front gate voltage, Vgs , minus the front gate
flat-band voltage, VFBF .
3. If we assume that the buried oxide thickness is so
large that the potential difference across any finite
distance in the BOX is negligible in the y-direction
we can write dUðx; yÞ=dy ffi 0 in the BOX. Therefore,
we have: dUðx;yÞ
jy¼tsi ¼ c1 ðxÞ þ 2tsi c2 ðxÞ ffi 0 and thus
dy
c2 ðxÞ ffi c2t1 ðxÞ
.
si
Introducing these three boundary conditions in
Eq. (4) we obtain:
Uðx; yÞ ¼ Uf ðxÞ þ
eox Uf ðxÞ Ugs
1 Uf ðxÞ Ugs 2
y
y
esi
tox
tox
2tsi
ð5Þ
Substituting Eq. (5) into Eq. (3), and setting y ¼ 0, at
which depth Uðx; yÞ ¼ Uf ðxÞ we obtain:
d2 Uf ðxÞ eox Uf ðxÞ Ugs qNa
¼
esi
tsi tox
esi
dx2
ð6Þ
Once Uf ðxÞ is determined from Eq. (6), Uðx; yÞ can be
calculated using Eq. (5). Eq. (6), however, can be used
for another purpose. If we write
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
esi
tox tsi
k1 ¼
ð7Þ
eox
and
uðxÞ ¼ Uf ðxÞ Ugs þ
qNa 2
k
esi 1
ð8Þ
then Eq. (6) can be written as follows:
d2 uðxÞ uðxÞ
2 ¼0
dx2
k1
ð9Þ
This equation is a simple differential equation with a
parameter, k1 , that controls the spread of the electric
potential in the x-direction. Note that uðxÞ differs from
Uf ðxÞ only by an x-independent term. Parameter k1 is
called the ‘‘natural length’’ of the device and it depends
on the gate oxide and silicon film thickness. Further
analysis and numerical simulations show that the effective gate length of a MOS device must be larger than 5–
10 times the natural length to prevent short-channel
effects and to produce a reasonable subthreshold
behaviour [33].
In the case of a double-gate device the boundary
conditions to Eq. (4) are:
1. Uðx; 0Þ ¼ Uðx; tsi Þ ¼ Uf ðxÞ ¼ c0 ðxÞ where Uf ðxÞ is the
front surface potential;
U ðxÞU
2. dUðx;yÞ
jy¼0 ¼ eeoxsi f tox gs ¼ c1 ðxÞ, where Ugs ¼ Vgs VFBF
dy
is the front gate voltage, Vgs , minus the front gate flatband voltage, VFBF .
U ðxÞU
3. dUðx;yÞ
jy¼tsi ¼ eeoxsi f tox gs ¼ c1 ðxÞ þ 2tsi c2 ðxÞ ¼ c1 ðxÞ
dy
and thus c2 ðxÞ ¼ ct1siðxÞ.
Substituting these boundary conditions into Eq. (4)
yields:
eox Uf ðxÞ Ugs
y
Uðx; yÞ ¼ Uf ðxÞ þ
esi
tox
1 eox Uf ðxÞ Ugs 2
y
ð10Þ
tsi esi
tox
The key difference between this expression and Eq. (5)
is that the term 1=2tsi has now been replaced by 1=tsi .
In other words it looks as if the double-gate device
was twice as thin as the single-gate transistor. The natural length of the double-gate device can be derived
the same way it was done for the single-gate case,
which yields:
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
esi
tox tsi
k2 ¼
ð11Þ
2eox
The natural length gives a measure of the short-channel
effect inherent to a device structure. It represents the
penetration distance of the electric field lines from the
drain in the body of the device or the amount of control
the drain region has on the depletion zone in the channel, as both the gate and the drain compete for that
control. A small k is desired to minimize short-channel
effects on the subthreshold slope. Numerical simulations
establish that a device is relatively free of short-channel
effects if k has a value smaller than 5–10 times the gate
length. The original publication of the natural length
concept [33] analyzes single- and double-gate structures.
It can be extended to surrounding-gate devices with
2
2
square cross-section by noting that ddyU2 ¼ ddzU2 in the center
of the device, where the encroachment of the electric
field lines from the drain on the device body is the
strongest. In that case the Poisson equation becomes:
d2 Uðx; y; zÞ
d2 Uðx; y; zÞ qNa
þ
2
¼
esi
dx2
dy 2
ð12Þ
J.-P. Colinge / Solid-State Electronics 48 (2004) 897–905
901
Table 1
Natural length in devices with different geometries
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
esi
tsi tox [33]
eox
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
esi
tsi tox [33]
k2 ¼
2eox
Single-gate
Double-gate
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
esi
tsi tox
k3 ffi
4eox
Surrounding-gate
and the natural length is equal to:
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
esi
tox tsi
k3 ¼
4eox
ð13Þ
Silicon thickness/width to gate length ratio
Ref. [34] analyzes the case of a double-gate device with
different boundary conditions than [33] and Ref. [35]
calculates the natural length in a cylindrical surrounding-gate device. The natural length corresponding to
different device geometries are summarized in Table 1.
The natural length concept can be used to estimate
the maximum silicon film thickness and device width
that can be used in order to avoid short-channel effects.
Fig. 8 shows the maximum allowed silicon film thickness
(and device width in a triple-gate device with W ¼ tsi ) to
avoid short-channel effects. The plot is based on Eqs.
(7), (11) and (13), and a gate oxide thickness of 1.5 nm.
It reveals that for a gate length of 50 nm, for instance,
the thickness of the silicon film in a single-gate, fully
depleted device needs to be 3–5 times smaller than the
gate length. If a double-gate structure is used, the silicon
film thickness is more relaxed and needs to be only half
the gate length. Further relaxation is obtained using a
surrounding-gate structure, where the silicon film
thickness/width/diameter can be as large as the gate
surrounding,
4 gates
1
0.8
2 gates
0.6
0.4
1 gate
0.2
0
0
10
–
k1 ¼
20
30
40
50
60
70
80
90
100
Gate length, nm
Fig. 8. Maximum allowed silicon film thickness and device
width vs. gate length to avoid short-channel effects in single-,
double- and quadruple-gate SOI MOSFETs.
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ffi
esi
eox tsi
1þ
tsi tox
k4 ¼
2eox
4esi tox
(square-section)
k5 ¼
[34]
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ffi
u
u2esi t2 ln 1 þ 2tox þ eox t2
si
si
t
tsi
16eox
(circular cross-section)
[35]
length. The film thickness requirements for triple-gate,
P-gate and X-gate devices are located between those for
double-gate and surrounding-gate devices. The use of
very thin silicon films is thus required for short-channel
single-gate devices. However, severe mobility reduction
effects have been reported in ultra-thin SOI devices [36–
38]. Furthermore, the use of ultra-thin films poses the
problem of high source and drain resistance and tight
etch selectivity budget. Quite clearly, the use of doublegate, and especially that of surrounding-gate structures,
relaxes the requirements on film thickness.
4. Triple-plus (3þ )-gate structures
It is quite clear from the above considerations, than
the surrounding-gate structure offers the best possible
characteristics in terms of current drive and shortchannel effects control. All surrounding-gate devices
reported in the literature have a vertical-channel and
have a non-planar nature, and the source and drain are
situated at different depths in the silicon film (Fig. 5). It
is, however, possible to design and fabricate quasi-surrounding-gate MOSFETs using a process similar to that
used to fabricate triple-gate SOI MOSFETs. Such devices are called either P-gate [39,40] or X-gate [41]
MOSFETs (Fig. 9). These devices are basically triplegate devices with an extension of the gate electrode
below the active silicon island, which increases current
drive and improves short-channel effects. The gate
extension can readily be formed by slightly overetching
the buried oxide (BOX) during the silicon island patterning step. The gate extension forms a virtual, fieldinduced gate electrode underneath the device that can
block drain electric field lines from encroaching on the
channel region at the bottom of the active silicon. Instead the lines terminate on the gate extensions. This
gate structure is very effective at reducing short-channel
effects. Such devices can be called 3þ (triple-plus)-gate
devices because their characteristics lie between those of
triple- and quadruple-gate devices. Fig. 10 presents the
equipotential line distribution in (A) a triple-gate, (B) a
quadruple-gate, and (C) Pi-gate device. The gate length,
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J.-P. Colinge / Solid-State Electronics 48 (2004) 897–905
Fig. 9. P-gate (Pi-gate) and X-gate (Omega-gate) MOSFET cross-sections.
Fig. 11. Subthreshold slope in double-, triple-, quadruple-/
surrounding-gate and P-gate MOSFETs as a function of gate
length. W ¼ tsi ¼ 50 nm, tox ¼ 3 nm, VDS ¼ 0:1 V.
Fig. 10. Contour plot of potential in a triple-gate device (A),
a quadruple-gate device (B) an a Pi-gate device (C).
silicon film thickness, and width are 30, 50, and 50 nm
respectively. The gate voltage and substrate (back gate)
voltages are 0V, while the drain voltage is 1 V.
Encroachment of electric field from drain on the channel
region can be seen in the triple-gate device, but not in the
Pi-gate and quadruple-gate devices. These contour plots
illustrate the effectiveness of the field-induced, pseudo
back gate created by the gate extension. Fig. 11 compares the subthreshold swing of transistors with 2–4
gates with that of a P-gate device. Increasing the number of gates improves the subthreshold swing because
the control of the channel region by the gate(s) becomes
more effective and because multiple gates offer more
shielding plates protecting the channel region from the
electric field lines from the drain. It should be noted that
the performances of the P-gate structure are very close
to those of a 4-gate device.
These 3þ -gate devices offer high current drive and
reduced short-channel effects. Unlike classical single- or
J.-P. Colinge / Solid-State Electronics 48 (2004) 897–905
double-gate MOSFETs these devices present a nonplanar silicon/gate oxide interface involving four corners. Here we will study the influence of these radii of
curvature on the device electrical characteristics. It is
important to realize that in classical SOI MOSFETs
corners appearing at the edge of the device can give rise
to parasitic currents which are usually undesirable, while
in multiple-gate devices the corners are part of the
intrinsic ‘‘active’’ transistor structure. Therefore it is
worth understanding the relationship and interaction
between currents in the corner and currents in the planar
surfaces of the device.
The cross-section of 3þ -gate device is shown in Fig.
12. The thickness and width of the device are tsi ; and W ,
and the radii of curvature of the top and the bottom
corners are noted rtop and rbot , respectively. The gate
oxide thickness is 2 nm, and tsi ¼ W ¼ 30 nm. The depth
of the gate extension in the buried oxide, text , is 10 nm.
The gate material is Nþ polysilicon with UMS ¼ 0:9 V.
Because the gate material is Nþ polysilicon and the device thickness and width are small, high doping concentrations have to be used to achieve useful threshold
voltage values. Fig. 13 presents the dgm =dVG characteristics of the device at VDS ¼ 0:1 V for different doping
concentrations and a top and bottom corner radius of
curvature of 1 nm. The dgm =dVG characteristics have
been used by several authors to identify the different
threshold voltage(s) in accumulation-mode and doublegate SOI devices. The humps of the dgm =dVG curve
correspond to the formation of channels in the device
(i.e. they correspond to threshold voltages). The devices
with the lowest doping concentrations exhibit a single
hump, indicating that both corners and edges build up
channels at the same time. The devices with the more
heavily doped channels have two humps. The first of
these two humps corresponds to inversion in the top
corners, and the second one to top and sidewall channel
formation. The dVG =dðlogðID ÞÞ curves of the same devices are shown in Fig. 14. Below threshold the
dVG =dðlogðID ÞÞ values correspond to the subthreshold
Fig. 12. Cross-section of P=X-gate devices. The radii of curvature of the top and bottom corners are rtop and rbot , respectively; rtop ¼ rbot (left) and rtop 6¼ rbot (right).
903
Fig. 13. dgm =dVG in a 3þ -gate MOSFET for rtop ¼ rbot ¼ 1 nm.
Gate material is Nþ polysilicon.
Fig. 14. dVG =dðlogðID ÞÞ (subthreshold swing) for rtop ¼ rbot ¼
1 nm.
swing. The more lightly doped devices reach a 60 mV/
decade swing for most of the subthreshold current
range, while the highly doped MOSFETs barely reach
that value. Fig. 15 presents the dgm =dVG characteristics
in a device with a top and bottom corner radius of
curvature of 5 nm. In this case a single peak is observed
for all doping concentrations, which indicates that premature corner inversion has been eliminated. In that
case all devices reach a subthreshold swing of 60 mV/
decade over a significant range of their subthreshold
current. Further analysis shows that the dgm =dVG curves
of a device with top and bottom corner radii of curvature of 5 and 1 nm, respectively, presents a hump for the
highest doping concentrations. This hump is not due to
current in the top corners, but rather in the bottom
904
J.-P. Colinge / Solid-State Electronics 48 (2004) 897–905
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
Fig. 15. dgm =dVG for rtop ¼ rbot ¼ 5 nm.
[11]
[12]
corners, where inversion channels form at a lower gate
voltage than on the other Si/SiO2 interfaces of the device. The corner effect can thus be eliminated by using
either a midgap gate material and low doping concentration in the channel, or corners with a large enough
radius of curvature [42,43].
[13]
[14]
[15]
5. Conclusion
Silicon-on-insulator MOS transistors are evolving
from the classical, planar, single-gate device into threedimensional devices with multiple gates (double-, tripleor quadruple-gate devices). These devices offer a higher
current drive per unit silicon area than conventional
MOSFETs. In addition they offer optimal short-channel
effects (reduced DIBL and subthreshold slope degradation). A new class of MOSFETs, called triple-plus (3þ )gate devices offer a practical solution to the problem of
the manufacturing surrounding-gate silicon MOSFET.
Such structures are triple-gate transistors with fieldinduced, pseudo-fourth gate that emulates a real back
(4th) gate underneath the device.
[16]
[17]
[18]
[19]
[20]
[21]
[22]
[23]
[24]
[25]
Acknowledgements
[26]
The author wishes to thank Drs. X. Baie, C.A. Colinge, J.T. Park, J.W. Park and W. Xiong for their help
and collaboration.
[27]
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