Download Lab 2

CEC 222 Digital Electronics Lab
Spring 2015
Lab 2: Logic Levels and Logic Gates
Learning Objectives:

Reinforce concepts relating to logic levels, Boolean values, binary values, and voltages

Gain exposure to the logic behavior of the four main gate types and the Laws of Boolean Algebra
Lab Overview:
In this lab, you will drive an inverter (7404) with an analog voltage, monotonically increasing the input from
0 to 5 Volts, and observe the behavior of the output. The second experiment involves determining the types of
four unknown gates by applying all possible input combinations and observing the corresponding outputs. The
last part of the lab empirically tests the validity of the Dual of the Distributive Law.
The extra credit experiment seeks to determine if inversion is a linear operator (i.e., is the inverse of the
output of an AND gate the same as the AND of the inverted inputs ( A  B  A  B ? )).
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Lab 02
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CEC 222 Digital Electronics Lab
Spring 2015
Pre-Lab (10%)
Question 1. Review the data sheet of the 74LS04 Hex inverter
and determine the meanings of VIL and VIH. From this
understanding for what range of input voltages would you
expect the inverter’s output to be HIGH?
Input range = _____ to ____ in Volts
Question 2. Similarly, for what range of input voltages would
you expect the inverter’s output to be LOW?
Figure 1 The 74LS04 Hex Inverter
Input range = _____ to ____ in Volts
Question 3. What is the Dual of the Distributive Law: (A + B)  C ? __________________________
Task 1.
Fill in the predicted output column in Table 3 (i.e., given x, y, and z what is x  ( y z ) ?).
Task 2.
Watch the two part “Getting Started Video” entitled “Creating your first schematic in ISE.”
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CEC 222 Digital Electronics Lab
Spring 2015
Experiments (90%)
EXPERIMENT 1.
INVERTER INPUT / OUTPUT CHARACTERISTICS
In this experiment, you will be determining the input / output characteristics of an inverter, specifically, the
7404 Hex Inverter. You shall discover the range of input Voltages that are interpreted as logic LOW (i.e., Boolean
FALSE or binary ‘0’) by observing when the output is high and conversely the range of input Voltages that are
interpreted as HIGH (i.e., Boolean TRUE or binary ‘1’) by observing when the output goes LOW. The Analog
Discovery will be used to power our circuit, generate a variable input voltage, and measure the output.
Step 1.a: Build the circuit and make the necessary connections from the Analog Discovery.

Place the 7404 chip on your breadboard straddling the center channel

Make the following connections from the Analog Discovery to your
breadboard:
 Power Supply: Connect the V+ Power Supply (Red) lead to pin 14
of your 7404 inverter chip and a ground (Black) lead to pin 7.
 Input Signal: Connect the Waveform Generator 1 (Yellow) lead to
the input of the inverter on pin 1.
 Measurement: Connect Scope Channel 1 Positive (Orange) lead to the output of the inverter on pin
2 and the Scope Channel 1 Negative (Orange/White) lead to ground (i.e., pin 7).

Start the Digilent -> WaveForms software (
):
 Click on the “Voltage” icon in order to start the power supply. The power supply
should initially be OFF (
). Click on the “Power is OFF” tab to
turn the power on.
 Click on the WaveGen icon (
), then
select the straight line icon on the left pane.
The center pane should be set at 0 V. Click on
the “Run AGW 1” button on the left, which
will commence signal generation.
 Finally, from the “More Instruments” pulldown, select “Voltmeter”. The DC row of the
Channel 1 column corresponds to your inverter’s output.
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CEC 222 Digital Electronics Lab
Spring 2015
Step 1.b: Record the input and output voltages.

From within the Waveform Generator, starting from 0 Volts, increase the voltage in 0.5 volt increments
and measure the inverter’s output voltage with the Voltmeter. Record your results in Table 1.
Table 1 Inverter Input / Output Characteristics
Input Voltage
Measured Output
Output Logic Level
in Volts
Voltage in Volts
0V
HIGH
0.5 V
1V
1.5 V
2V
2.5 V
3V
3.5 V
4V
4.5 V
5V
LOW
Task 3.
Using the values from Table 1, plot the measured output voltage (vertical axis) against the input
in Figure 2.
Figure 2 Inverter Input / Output Characteristics (using an voltmeter).

Close the Voltmeter window as we no longer need it.

Leave your circuit intact, but, Turn OFF the power supply (
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).
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CEC 222 Digital Electronics Lab
Spring 2015
Step 1.c: Perform an alternative method of plotting the input / output characteristics by driving the inverter’s
input with a triangular waveform.

Generate a triangular waveform:
 In the left pane of the “Waveform Generator” select the triangle waveform.
 Set the Frequency to 100 Hz.
 Set the Amplitude to 2.5 V.
 Set the Offset to 2.5 V.
 Click on the “Run AWG 1” button to generate a “ramp” waveform.


NOTE that the waveform magnitude goes from 0 to 5 Volts!!
Add a second oscilloscope channel to monitor the inverter’s input by connecting Scope Channel 2
Positive (Blue wire) to the inverter’s input on pin 1 of the 7404 and the Scope Channel 2 Negative
(Blue/White wire) to ground.

Turn ON the power supply.

Start the oscilloscope by clicking on the Scope icon and set the scope to
trigger on channel 1 on a rising edge with a level of 1V.
Task 4.
Take a screenshot of the oscilloscope window showing more than one, but, less than two
periods of the waveform and past it into Figure 3.
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CEC 222 Digital Electronics Lab
Spring 2015
Figure 3 Inverter Input / Output Characteristics (using an oscilloscope).

Both Figure 2 and Figure 3 represent the Input / Output Characteristics of the inverter, however, Figure
3 may provide better fidelity.
Question 4. Considering either plot of the inverter’s Input / Output Characteristics, over what range of input
voltages (i.e., input LOW) would you expect the inverter’s output to be reliably HIGH?
Input LOW Range = __________ Volts to ____________ Volts

The upper end of this range corresponds to VIL.
Question 5. Considering either plot of the inverter’s Input / Output Characteristics, over what range of input
voltages (i.e., input HIGH) would you expect the inverter’s output to be reliably LOW?
Input HIGH Range = __________ Volts to ____________ Volts

The upper end of this range corresponds to VIH.
EXPERIMENT 2. DETERMINING THE TYPES OF FOUR
UNKNOWN GATES
In this part of the lab you will download a new “bit” file to your
SW0
SW1
Gate #0
LED0
Gate #1
LED1
Gate #2
LED2
Gate #3
LED3
FPGA corresponding to a circuit design which contains four basic two
input gates all driven by the same inputs. These inputs are controlled
by SW1 and SW0. The outputs from these four gates drive LED3 to
LED0, respectively (see Figure 4). If the output from a given gate is
HIGH, then the corresponding LED will be illuminated.
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Figure 4 Configuration of four gates.
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CEC 222 Digital Electronics Lab
Spring 2015
Step 2.a: Load the file “Lab2_Experiment2.bit” into your BASYS 2 FPGA board

Connect your board to a PC (via USB cable) and turn on the board’s power

Download the “Lab2_Experiment2.bit” file onto your desktop, start the “Adept” software (
), and on
the row labeled “PROM” browse to select the “lab2.bit” file and then program the board with this file.

After programming, you may need to turn the power to your FPGA board OFF and back ON in order to
load the new design.
Step 2.b: Test the gates with every possible binary input combination.

By varying SW1 and SW0, generate every possible combination of the two inputs and observe the four
LEDs to determine the output for each gate and fill in the Output columns of Table 2. Note that the
switch (or LED) being ON, can be represented by logic HIGH, or binary 1.
Inputs
SW1
0 = LOW = OFF
0 = LOW = OFF
1 = HIGH = ON
1 = HIGH = ON
Table 2 Truth Table for Four Unknown Gates
Outputs
SW0
LED0
LED1
0 = LOW = OFF
1 = HIGH = ON
0 = LOW = OFF
1 = HIGH = ON
LED2
LED3
Question 6. Based on the results obtained from completing Table 2, what type of basic logic gate is Gate #0
(see Figure 4)? Gate #0 is a _________ logic gate
Question 7. What type of basic logic gate is Gate #1? Gate #1 is a _________ logic gate
Question 8. Based on the assumption that Gate #2 is a close relative of gate #0 (or #1), how would you
describe Gate #2? Gate #2 is a _________ logic gate
Question 9. Based on the assumption that Gate #3 is a close relative of gate #0 (or #1), how would you
describe Gate #3? Gate #3 is a _________ logic gate
EXPERIMENT 3.
PROVING THE DUAL OF THE DISTRIBUTIVE LAW
The Distributive Law states that
x  y  z   ( x y)  ( x z )
(1.1)
Thus, the Dual1 of the Distributive Law becomes
x  ( y z )  ( x  y)  x  z 
1
(1.2)
Principle of Duality  Replace AND by OR (and vice versa), also replace “0” by “1” (and vice versa).
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CEC 222 Digital Electronics Lab
Spring 2015
By building (in your FPGA) logic circuits to implement the Dual of the Distributive Law you will attempt to
empirically confirm its validity. Given a logic circuit that represents the left-hand-side (LHS) of the Dual of the
Distributive Law (i.e., Eqn. (1.2)) you will construct a second circuit to represent the RHS and then compare the
outputs of both circuits in response to all possible input combinations.
Step 3.a: Build a circuit to represent the RHS of the Dual of the Distributive Law.

Download the file “Lab2_Experiment3.zip” and uncompress it on your desktop.

In the folder “Lab2_Experiment3” double click on the project file “Lab2_Experiment3.xise,” this will start
the Xilinx ISE software (be patient it may take a few seconds).

In the “Hierarchy” pane (left), double click on “experiment_3” to display a schematic. You may want to
zoom in on the schematic.

In the bottom left corner, select the “Symbols” tab.

Now you are ready to add gates to the schematic in order to realize the RHS of Eqn. (1.2).

Note that the inputs of both circuits are connected to the switches and the outputs to the LEDs:
 Inputs: SW2 = x, SW1 = y, and SW0 = z.
 Outputs: LED1 = LHS and LED0 = RHS.
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CEC 222 Digital Electronics Lab

Spring 2015
Using the switches, input all possible combinations of the three inputs x, y, and z and fill in the output
for both the LHS circuit and the RHS circuit.
Table 3 Truth Table for Four Unknown Gates
Inputs
Measured Outputs
y (=SW1)
RHS (=LED0)
z (=SW0)
LHS (=LED1)
0
0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
x (=SW2)
0
0
0
0
1
1
1
1
Question 10.
Predicted O/P
x  ( y z)
0
Are all three of your output columns the same? ___________
Report Requirements
Question 11.
When developing a large and complex circuit, should you first build it all and then test it
all at once, or should you build and test smaller sub-circuits as you go?
_____________????
Optional Exercise(s) (+10% Extra Credit)
EXPERIMENT 4.
IS THE NOT OF THE AND THE SAME AS THE AND OF THE “NOTS”?
The extra credit experiment seeks to determine if inversion is a linear operator (i.e., is the inverse of the
output an AND gate the same as the AND of the inverted inputs: A  B  A  B ? ).
Step 4.a: Develop a schematic to test if A  B  A  B ? .

Recycle your schematic from Experiment 3 to build the new schematic.
 Use SW1 and SW0 as the A and B inputs and retain LHS and RHS as
your outputs.
 You will need to delete the unused input line from your “experiment3.ucf” file.
Question 12.
Is A  B  A  B true or false and why?
A  B  A  B is _______________
Explanation:______________
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CEC 222 Digital Electronics Lab
Spring 2015
Reference Material
APPENDIX A: PIN NUMBERING CONVENSION
The view from the top of a 7404 Hex inverter is shown in Figure 5.
“Top” indent
Figure 5 Pin numbers for a 14-pin DIP package.
APPENDIX B: CREATING YOUR ISE SCHEMATIC DESIGN
B1) CREATING YOUR FIRST SCHEMATIC IN ISE (VIDEOS)

Part 1: Schematic design

Part 2: Pin assignamnt and programming the FPGA
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