Download Low Pass Filter (Ideal Block)

Chronic Implant signal Acquisition IC
for ECEN 5007 Mixed Signal IC
December13, 2002
S. Johnson
V. Ganesan
Chronic Implant Signal Acquisition IC
Introduction
Research in the area of neuronal signaling is constrained by the test electronics readily
available. Large, inflexible neural probes are implanted into test animals, requiring bulky
cabling configurations to connect to the recording equipment. Such a test setup hampers
the test subject's movement and thus greatly changes the way in which the test subject
would normally interact with its environment. This change in normal behavior effects the
way in which they learn and in turn can skew desired test results. A proposed solution is
to place the microelectronics used for recording neural signals onto a small chip, which
rides on top of the mechanical probe. Such a device would be small enough to be
implanted, and allow the test animal to recover from the surgery and soon after interact
normally with its environment.
Key system requirements






No chronic external wiring - External wiring interferes with the natural
movement and hence behavior of the test subject
The probe must be able to "float" with the tissue in which it is implanted - The
brain moves inside the skull, an implant that is rigid and anchored to the skull
does not allow for such movement, hampering normal function.
The electronics must be integrated with the mechanical probe - Proximity to the
acquired signal helps keep noise low (short transmission path) and aids in a
higher resolution of data.
Low power consumption - Must keep power consumption low to minimize
energy storage (battery) 1mW goal.
Low power dissipation - Must keep power dissipation low to reduce heat load on
tissue. (A rise in temperature of 0.5C causes stress in the tissue disrupting
normal function, a 2C rise causes tissue death).
Small size - Chip must be small so as not to interfere with normal function. For
this application the area of tissue is 3mm2, and the mechanical probe and
acquisition electronics must fit within a 1mm2 footprint.
System Description
The block diagram of the complete system is shown in Figure 1. The chronic implant
signal acquisition IC encompasses a significant portion of the probe module which
includes the analog front end, multiplexer, clock and a limited amount of configuration
and control circuitry. The Surface Module is a larger chip where the majority of signal
processing will take place. It is attached to the outside of the scull of the test animal
where constraints of size, power consumption and power dissipation are not as great. The
Surface Module provides an interface to the researcher to access data, charge the on-chip
battery cell, and send simple control commands to the electronics. A flexible wire tether
bundle would provide the interconnections between the two modules . The Surface
Module is shown only for completeness of the system.
Dual Module Approach
Probe Module
Surface Module
Analog Front End
Demultiplexer
Probe
Interfaces
ADC
.
.
.
Clock
Configuration
& Control
Pow er
Mgmt
Serial Interface
Multiplexer
LNA IA
Signal
Process
.
.
.
Signal
Storage
.
.
.
Clock
Rcvr.
Configuration
& Control
Pow er
Mgmt
Initiation
Signal
(w ireless)
User
Interf ace
(w ired)
Energy
Storage
Figure 1 Complete System
The signal acquisition portion of the Probe Module is comprised of an analog front end,
and a multiplexer. The analog front end interfaces with four probe lines, and amplifies
the incoming neural signals. The first amplification stage is the LNA (low noise
amplifier) and is shown in Figure 2.
Figure 2 LNA
The LNA is comprised of the following:
 An AM (amplitude modulation) block which shifts the low frequency, low
voltage signal up in frequency above the flicker noise of the preamp,
 A low noise pre-amp
 A Selective Amplifier (acting as a bandpass filter with gain, which filters out the
low frequency noise component, leaving the modulated signal component)
 A second AM block which demodulates the original signal back to its baseband
frequency.
 An LPF filter which filters out the additional, high frequency, modulation
components.
(A detailed description of the LNA utilizing the chopper technique as described above
can be found in Appendix A)
(A detailed description of the Selective Amplifier as described above can be found in
Appendix B).
Once the signal is amplified, it is multiplexed with the other amplified probe lines. The
multiplexer's purpose is to sample each of the lines at a minimum of 25kHz. This
satisfies the Nyquist criterion where the sampling rate must be at least twice that of the
signal being sampled. For this application, the neural signal bandwidth is less than
5kHz. Since the system can obtain good data from up to four probes at one time, the
switching frequency of the multiplexer must be a minimum of 100kHz to achieve a
25kHz sampling rate for each line.
The last portion of the system is the Clock and the Configuration and Control and
blocks. The clock is supplied to the analog front-end for the modulators, and the
multiplexer for the switching frequency. The Configuration/Control block operates as
follows:




Upon initial power-up and data acquisition, the researcher will determine which
probe signals are useful.
The researcher sends a code to the Configuration and Control block on the
Surface Module, telling it which channels are good.
The "good" channel information is sent as a binary stream to the Configuration
and Control block on the Probe Module. The Control block then powers down
the amplifier stages whose signals are too weak or non-existent, thus saving on
power consumption and lowering power dissipation.
The multiplexer is directed to sample only those lines that are powered. The
control block will be in control of the sequencing of the amplified probe lines, and
the frequency at which they are sampled.
General IC Operation
CHopper LNAs
The chip contains four CHopper LNAs which are multiplexed onto a common output bus.
Each LNA requires a 2V supply and a 1V reference. A 40kHz non-overlapping clock
drives the AM modulation/demodulation circuitry. The chip is fabricated to interface to a
mechanical biocompatible probe. The nominal input signal range of the chip is up to
5kHz in frequency and 100uV in amplitude. The signal arrives at the first modulator
block via the probe, and is translated up in frequency on a 40kHz carrier signal. The
modulated signal is then amplified by the pre-amp, which gives it 36dB of gain. The
amplified, modulated signal is then routed through a selective amplifier which passes
signals in the frequency range of 30 - 50kHz, adding an additional 24dB of gain. The
signal is then demodulated with the second modulation block, bringing it back down to
the original baseband frequency. It is then passed through the low pass filter where any
remaining noise and/or harmonics are removed.
Probe
Interface/
Signal
Input
Modulator
Pre-Amp
Selective
Amp
(BPF)
Modulator
Low Pass
Filter
LNA
Output
Figure 3 CHopper Amplifier Block Diagram
Probe Selection and Multiplexing
The IC has four input pins that simulate the amplifier enable function of the
Configuration and Control block. To enable each of the input LNAs, a voltage of 2 volts
is applied to the corresponding pin. This closes a switch, routing power to the amplifier.
To disable the amplifier, the pin is grounded, opening the switch. Once the amplifiers are
selected, the clock driving the multiplexer switching logic is enabled by applying 2 volts
to the clock enable pin. The multiplexer then cycles through each of the amplifier lines
at a frequency of 100kHz. The multiplexer switching is controlled using a binary counter
and a combination of logic gates. As the counter goes to each state, a voltage is applied
to a corresponding switch that closes, momentarily connecting the output of a particular
LNA to the multiplexer output bus.
Probe
Interfaces
Multiplexer
Chopper LNA
ch0
Muxed Signals Out
Chopper LNA
ch1
Chopper LNA
ch2
Chopper LNA
ch3
MUX Switch
Control Logic
mod/demod
Clock
en0 en1 en2 en3
LNA enable
commanding
2 Bit
Binary
Counter
Count Enable
MUX
Clock
Figure 4 System Overview
Vdd
Bus Out
SW0 in +
SW0 in
>
SW1 in
>
SW0 in -
SW2 in
>
SW1 in +
SW3 in
>
SW1 in MULTIPLEXER
SW2 in +
SW2 in SW3 in +
SW3 in -
MSB >
LSB >
MSB
LSB
Bus Out +
Bus Out GND
Figuren5 Multiplexer Circuitry and Block Diagram
Vdd
>Clk (100kHz)
BINARY
COUNTER
MSB
>Reset
LSB
GND
Clk
Reset
Figure 6 Binary Counter Circuit and Block Diagram
Specifications
Modulator/Demodulator


Each contains 4 nmos transistor switches
Two 2V, 40kHz non-overlapping clock signals are applied to the gates with
phases as shown

In +
Out +
Signal In +
Signal Out +

MODULATOR
In -

Out -
>  (Clk In 2V)
 (Clk In 2V) <
Signal In -
Signal Out -
Figure 7 Modulation/Demodulation Circuitry

Pre-Amplifier








V
d
dVout1
O
u
t
1
Rail-to-rail fully differential Miller compensated amplifier
Supplies: 2V and GND
Input Range: 0 - 200uV
Output Range 0-12.6mV
3dB/corner frequency 60kHz
Gain 36dB
Bias current: 2uA
Power dissipation: 700uW
CMFB
CMFB
Vin1
I
n
1
Vin2
I
n
2
Vout2
O
u
t
2
Common Mode Feedback
Vdd
In 1
In 2
Fully Differential Pre-Amp
Ref
DIFFERENTIAL
PRE-AMP
Out 1
Out 2
GND
Figure 8
Selective Amplifier/Band Pass Filter










Rail-to-rail fully differential Gm-C amplifier
Supplies: 2 V and ground
Input Range:0-200mV
Center Frequency: 40kHz
Pass Band: 30-50kHz
Gain: 24dB
20uA bias current Gm1
25uA bias current Gm2
50uA bias current Gm3
Power dissipation 400uW
Vdd
In 1
In 2
Ref
SELECTIVE
AMPLIFIER
(BPF)
Out 1
Out 2
GND
Figure 9 Gm-C Selective Amplifier/BPF
Low Pass Filter (Ideal Block)

Frequency Range: 0-20kHz
Vdd
In 1
In 2
LPF
Out 1
Out 2
GND
Figure 10 Ideal LPF
Clock Circuitry



2V supply voltage
200uA initialization pulse
Output: 1 - 100kHz clock, 2- 40kHz clocks non-overlapping
Clock In
Clock 
Vdd
Clock Out
Reset
Clock 
non-overlapping clock logic
Vdd
Clk (100kHz)
Clock Circuit
CLOCK
>Reset
GND
Figure 11
Clk (40kHz) 
Clk (40kHz) 
Test Plan
Test Setup
See Figures 12 through 14 and pin-out table
1. Make supply and ground connections as shown in Figure 14
(Vdd1=2V , and Vref1=Vref2=1V)
2. Apply 2 Volts to en0 (pin 6) en1 (pin 7) en2 (pin 8) and en3 (pin 9) via jumper
connections
3. Apply 2V to en clk (pin 10)
4. Apply momentary initialization pulse (2V) to the Counter Reset (pin 5) and Clk
Reset (pin 4)
5. Apply a 5kHz, 100uV sinewave to the probe 0 input (pin 11 and 12)
6. Verify 5kHz, 100uV sinewave on a 40kHz carrier at the mod1 output pins of
modulator 1 on the CHopper LNA 0 (pins 13 and 14)
7. Verify 5kHz, 6.3mV sinewave on a 40kHz carrier at the Out 1 and Out 2 output
pins of the pre-amp on CHopper LNA 0 (pins 17 and 18)
8. Verify 5kHz, 100mV sinewave on a 40kHz carrier at the Out 1 and Out2 output
pins of the Selective Amplifier on CHopper LNA 0. (pins 21 and 22)
9. Verify all signals outside the 30-50kHz frequency range are at least 20dB lower
than those within the 30-50kHz frequency range. (pins 21 and 22)
10. Verify 5kHz, 100mV sinewave at the mod2 output pins of modulator 2 on
CHopper LNA 0 (pins 25 and 26)
11. Verify 5kHz, 100mV sinewave at the Out 1 and Out 2 output pins of the Low
Pass Filter (LPF) on CHopper LNA 0 (pins 29 and 30)
12. Repeat steps 5 - 11 for CHopper LNAs 1 - 3. (see table for pin-out)
13. Apply 5kHz, 100uV sinewave to each probe 0 - 3 input lines (see table for pinout)
14. Verify four 5kHz, 100mV, multiplexed sinewaves at the Multiplexer Bus Out
output (pins 99 and 100)
15. Apply a ground to en0 (pin 6) , verify no signal at the Multiplexer SW0 input pins
and no signal in time slot one on Multiplexer Bus output (pins 99 and 100)
16. Apply 2V to en0, verify 5kHz, 100mV sinewave at SW0 input pins and at
Multiplexer Bus Out output (pins 99 and 100)
17. Repeat steps 15 and 16 for en1, en2, en3 and SW1 SW2 SW3 pins and timeslots
1, 2 and 3 (see table for pin-out)
Vdd
Vref2
Vref1
CHopper LNA enable
c ommanding
en 0
CHopper LNA
Prob e
Sig nal
0
Vdd
In +
Out +
MODU LATOR
In -
In 1
In 1
Out -
Ref
DI FFE RE NT IA L
PRE -A MP
Vdd
In 1
In 2
Out 1
Out 2
>  (Cl k In 2V)
 (Cl k In 2V) <
GND
Ref
SE LE CTI V E
A MPLI FIE R
(BP F)
Vdd
In +
Out +
In 1
MODU LATOR
Out 1
Out 2
In -
LP F
Out 1
Out 2
>  (Cl k In 2V)
 (Cl k In 2V) <
GND
GND
Vdd
Vdd
CH OPPER
LNA
Vdd
Vref 1
Clk (1 00kHz )
CLOCK
Clk ( 40kHz )
Clk ( 40kHz )
GND
MUX
In 2
Out -
Vref 2


In + (mo d1)
Out + (mod1)
In - (mod 1)
Out - (mod1)
In1 (Amp)
Out 1 (Amp)
In2 (Amp)
Out 2 (Amp)
In1 (BPF )
Out 1 (BPF)
In2 (BPF )
Out 2 (BPF)
In + (mod2)
Out + (mod2)
In - (mod2)
Out - (mod2)
In 1 (LPF)
Ou t 1 (LPF)
In 2 (LPF)
Ou t 2 (LPF)
CL K 
CL K 
GN D
Figure 12 CHopper LNA Functional Block Diagram
Vdd=2V
en 0
c md
Vdd
C HOPPER
LN A 0
Vdd=2V
en 1
c md
Vref=1V
Vdd
C HOPPER
LN A 1
Vref 1
Vr ef 2
probe 0
inputs

In + (m od1)
Out + (mod1)
In - (mod1)
Out - ( mod1)
In1 (Amp)
In2 (Amp)
Vdd
Vr ef 2
SW0 in +
probe 1
inputs
In + (m od1)
Out + (mod1)
In - (mod1)
Out - ( mod1)
Out 1 ( Amp)
In1 (Amp)
Out 1 ( Amp)
SW1 in +
Out 2 ( Amp)
In2 (Amp)
Out 2 ( Amp)
SW1 in -
In1 (BPF)
Out 1 (BPF)
In1 (BPF)
Out 1 (BPF)
In2 (BPF)
Out 2 (BPF)
In2 (BPF)
Out 2 (BPF)
In + ( mod2)
Out + (mod2)
In + ( mod2)
Out + (mod2)
In - (mod2)
Out - (mod2)
In - (mod2)
Out - (mod2)
In 1 (LPF)
Out 1 (LPF)
In 2 (LPF)
Out 2 (LPF)

C LK

Vref=1V
Vref 1

C LK
In 1 (LPF)
Out 1 (LPF)
In 2 (LPF)
Out 2 (LPF)
SW0 in -
MU LTIPLEXER
SW2 in +
SW2 in SW3 in +
SW3 in -
C LK
MSB
C LK
LSB
GND
GND
Bus Out +
Bus Out GN D
Vdd=2V
en 2
c md
Vdd
C HOPPER
LN A 2
Vdd
C HOPPER
LN A 3
Vref 1
Vr ef 2
probe 2
inputs
In + (m od1)
Vdd
CLOCK
>Reset
Cl k (40kHz)
probe 3 In + (m od1)
inputs
Out - ( mod1)
In - (mod1)
Out - ( mod1)
In1 (Amp)
Out 1 ( Amp)
In2 (Amp)
Out 2 ( Amp)
In2 (Amp)
Out 2 ( Amp)
In1 (BPF)
Out 1 (BPF)
In1 (BPF)
Out 1 (BPF)
Out 2 (BPF)
In2 (BPF)
Out + (mod2)
In + ( mod2)
Out + (mod2)
In - (mod2)
Out - (mod2)
In - (mod2)
Out - (mod2)
In 1 (LPF)
Out 1 (LPF)
In 1 (LPF)
Out 1 (LPF)
In 2 (LPF)
Out 2 (LPF)
In 2 (LPF)
Out 2 (LPF)
C LK

BINAR Y
C OU NTER
MSB
>Reset
LSB
GND
Vdd
C LK
C LK
GND
GND
>Cl k (100kH z)
Out 2 (BPF)
In + ( mod2)

Vdd
Out + (mod1)
Out 1 ( Amp)
Cl k (40kHz)             
Vd d=2V
Vr ef 2
In1 (Amp)
C LK
Vref=1V
Vref 1
In - (mod1)
In2 (BPF)
Clk (100kHz)
Out + (mod1)
Vdd=2V
en 3
c md
Vref=1V
GND
Clk (100kHz)
Clk
Enable
CLOCK
GND
Figure 13 IC Block Diagram
Cl k (40kHz)

Cl k (40kHz)
             
>Reset
Vdd = 2V
Vref = 1V
V=
2V
1
2
3
4
5
6
7
8
9
10
11
12
Wa ve form
Gene rator
31
32
Vdd
Vref1
Vref2
Clk Reset
Counter Reset
en0
en1
en2
en3
en c lk
In+ m10
In- m10
Out+ m10
Out- m10
In1 p0
In2 p0
Out1 p0
Out2 p0
In1 s0
In2 s0
Out1 s0
Out2 s0
In+ m20
In- m20
Out+ m20
Out- m20
In1 L0
In2 L0
Out1 L0
Out2 L0
In+ m11
In- m11
Out+ m11
Out- m11
In1 p1
In2 p1
Out1 p1
Out2 p1
In1 s1
In2 s1
Out1 s1
Out2 s1
In+ m21
In- m21
Out+ m21
Out- m21
In1 L1
In2 L1
Out1 L1
Out2 L1
51
In+ m12
52
In- m12
Out+ m12
Out- m12
In1 p2
In2 p2
Out1 p2
Out2 p2
In1 s2
In2 s 2
Out1 s 2
Out2 s2
In+ m22
In- m22
Out+ m22
Out- m22
In1 L2
In2 L2
Out1 L2
Out2 L2
71
In+ m13
In- m1372
Out+ m13
Out- m13
In1 p3
In2 p3
Out1 p3
Out2 p3
In1 s3
In2 s3
Out1 s 3
Out2 s3
In+ m23
In- m23
Out+ m23
Out- m23
In1 L3
In2 L3
Out1 L3
Out2 L3
SW 0 +
SW 0 SW 1 +
SW 1 SW 2 +
SW 2 SW 3 +
SW 3 99
Output Bus +
Output Bus100
101
GND
Figure 14 Test Setup
O' sco pe
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Name
Vdd
Vref1
Vref2
Clk Reset
Counter Reset
en0
en1
en2
en3
en clk
In+ m10
In - m10
Out + m10
Out - m10
In1 p0
In2 p0
Out1 p0
Out2 p0
In1 s0
In2 s0
Out1 s0
Out2 s0
In + m20
In - m20
Out + m20
Out - m20
In1 L0
In2 L0
Out1 L0
Out2 L0
In+ m11
In - m11
Out + m11
Out - m11
In1 p1
In2 p1
Out1 p1
Out2 p1
In1 s1
In2 s1
Out1 s1
Out2 s1
In + m2
In - m2
Description
Supply input 2V
Common mode input 1V
Common mode input 1V
Initializes/starts clock
Resets T- flip flops in counter
enables/disables amps in LNA 0
enables/disables amps in LNA 1
enables/disables amps in LNA 2
enables/disables amps in LNA 3
enables/disables clock to counter
probe 1 input+ modulator 1
probe 1 input - modulator 1
modulator 1 output +
modulator 1 output pre-amp input 1
pre-amp input 2
pre-amp output 1
pre-amp output 2
selective amp input 1
selective amp input 2
selective amp output 1
selective amp output 2
modulator 2 input +
modulator 2 input modulator 2 output +
modulator 2 output low pass filter input 1
low pass filter input 2
low pass filter output 1
low pass filter output 2
probe 1 input+ modulator 1
probe 1 input - modulator 1
modulator 1 output +
modulator 1 output pre-amp input 1
pre-amp input 2
pre-amp output 1
pre-amp output 2
selective amp input 1
selective amp input 2
selective amp output 1
selective amp output 2
modulator 2 input +
modulator 2 input -
Sub-block
LNA op amps
LNA selective amps
Internal clock
Binary Counter
LNA 0 / modulator1
LNA 0 / pre-amp
LNA 0 /selective amp
LNA 0 /modulator 2
LNA 0 / LPF
LNA 1 / modulator1
LNA 1 / pre-amp
LNA 1 /selective amp
LNA 1 /modulator 2
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Out + m2
Out - m2
In1 L1
In2 L1
Out1 L1
Out2 L1
In+ m12
In - m12
Out + m12
Out - m12
In1 p2
In2 p2
Out1 p2
Out2 p2
In1 s2
In2 s2
Out1 s2
Out2 s2
In + m22
In - m22
Out + m22
Out - m22
In1 L2
In2 L2
Out1 L2
Out2 L2
In+ m13
In - m13
Out + m13
Out - m13
In1 p3
In2 p3
Out1 p3
Out2 p3
In1 s3
In2 ss3
Out1 s3
Out2 s3
In + m23
In - m23
Out + m23
Out - m23
In1 L3
In2 L3
Out1 L3
modulator 2 output +
modulator 2 output low pass filter input 1
low pass filter input 2
low pass filter output 1
low pass filter output 2
probe 1 input+ modulator 1
probe 1 input - modulator 1
modulator 1 output +
modulator 1 output pre-amp input 1
pre-amp input 2
pre-amp output 1
pre-amp output 2
selective amp input 1
selective amp input 2
selective amp output 1
selective amp output 2
modulator 2 input +
modulator 2 input modulator 2 output +
modulator 2 output low pass filter input 1
low pass filter input 2
low pass filter output 1
low pass filter output 2
probe 1 input+ modulator 1
probe 1 input - modulator 1
modulator 1 output +
modulator 1 output pre-amp input 1
pre-amp input 2
pre-amp output 1
pre-amp output 2
selective amp input 1
selective amp input 2
selective amp output 1
selective amp output 2
modulator 2 input +
modulator 2 input modulator 2 output +
modulator 2 output low pass filter input 1
low pass filter input 2
low pass filter output 1
LNA 1 / LPF
LNA 2 / modulator1
LNA 2 / pre-amp
LNA 2 /selective amp
LNA 2 /modulator 2
LNA 2 / LPF
LNA 3 / modulator1
LNA 3 / pre-amp
LNA 3 /selective amp
LNA 3 /modulator 2
LNA 3 / LPF
90
91
92
93
94
95
96
97
98
99
100
101
Out2 L3
SW0+
SW 0 SW 1+
SW 1 SW 2+
SW 2 SW 3+
SW 3 Bus Out +
Bus Out GND
low pass filter output 2
Mux input from LNA 0 + output
Mux input from LNA 0 - output
Mux input from LNA 1 + output
Mux input from LNA 1 - output
Mux input from LNA 2 + output
Mux input from LNA 2 - output
Mux input from LNA 2 + output
Mux input from LNA 2 - output
Mux output bus +
Mux Output bus ground
Multiplexer
Improvements
The goal was to achieve a small sized circuit with low power dissipation. The proposed
topology can easily fit within the 1mm2 footprint, but the power dissipation numbers
were way off. One fully differential amplifier dissipated 700uW of power. To reduce
this number and the overall power dissipation the following steps can be taken:
1.
2.
3.
4.
Use a smaller process - currently 0.5u process is being used.
Reduce the bias current
Reduce the phase margin from 86 deg to 76 deg to trade off for gain
Lower the CHopper frequency to approx 30kHz
- This in turn would decrease the required corner frequency of the pre-amp
- Optimize per-amp for larger gain at lower corner frequency
5. Remove the selective amplifier
6. Move to lower power amplifier topologies (i.e. telescopic, bulk driven
Oscillator - Right now it develops oscillations so the idea works. It needs to be improved
in terms of amplitude of the output signal because now it is in the order of mV which is
not sufficient. The things to do differently to achieve this
1. There has to be a right half plane zero which is that gn1 >= 2go which is what it
presently is. This needs to be designed such that gn1 is much higher than 2go.
2. Secondly try to improve the current flowing through the nonlinear conductance
cell so that it has more components at the desired chopper frequency so that stable
higher oscillations build up.
(A detailed description of the Oscillator as described above can be found in Appendix C).
Filter/Selective Amplifier - Right now it filters signals around the center frequency and
has a low power consumption .
1. In terms of the product where we are aiming at 1mW of total power consumption
we need to have devices which take really less current and still perform the above
functionality .So the things to do are to work out a design such that they still
satisfy .This requires iterative analysis.
2. Secondly try to reduce the bandwidth of accepting frequencies so that we amplify
a narrower bandwidth of signals.
Appendix A: CHopper Stabilization Technique (CHS)
Brief Background
The CHopper amplifier is commonly used to sense ultra low amplitude signals in
implantable sensors, and is based on amplitude modulation of desired signal
The CHS technique overcomes the dominant noise of differential amplifier input stage
including 1/f flicker noise, thermal noise and DC offset.
The CHopper Stabilization Technique (CHS)






The signal is amplitude modulated at a minimum of 2 times its frequency.
Amplitude modulation translates the signal to a frequency above the noise and the
voltage offset of the preamp stage.
The modulated signal is then input into a preamp where it is added with the offset
voltage and noise, and then amplified.
The amplified output is amplitude modulated with the same carrier signal as the
original low power, low frequency signal.
The second modulation stage demodulates the amplified neural signal back to its
baseband frequency, while modulating the noise and offset voltage signals up to
the carrier frequency.
The combined signal is then passed through a low pass filter eliminating the
unwanted higher frequency components.
T
T
c2(t)
c1(t)
t
t
c1(t)
+
++
A(f)
X
VOS+VN
VA
1 2 3 4 5 6
1 2 3 4 5 6
VOUT
pre-amp
Modulation
VIN
VA
X
VIN
c2(t)
1 2 3 4 5 6
Noise & Offset
1 2 3 4 5 6
VOUT
2nd Modulation
(Demodulation)
1 2 3 4 5 6
Figure A1 CHopper Technique
1 2 3 4 5 6
Appendix B Selective Amplifier/Band Pass Filter
Internal filter operation : The charge injection of CMOS switches in the modulator
generate the spikes leading to a residual offset in the output. To allow for CHS
performance we need to remove this. The second stage of the selective amplifier is a 2nd
order band pass gm-C filter .The Input transconductor Gm1 converts input signal from
voltage to current mode.Gm2 and Gm3 constitute resonant stage which determines the
center frequency of the filter.GM4 is responsible for converting back the signal from
current to voltage mode.
Gm Cell - Linearity transconductor using 2 triode region transistors as source
degeneration resistor is used in the filter.
Gm = Io / ( v1 – v2 ) = 1 / ( Rs1 + Rs2 + ( Rds3 || Rds4 )
Rs1 and Rs2 are output impedances of input transistors viewed from source
Rs1 = 1/ gm1 where gm = √ ( 2 up Cox (W/L)Id )
Rds3 = 1/ gds3 where gds3 = up Cox (W/L) Veff
Taking gm1 = gm2 and gds3 = gds4
Gm = gm1 / 2 || 2 gds3 = 4 gm1 gds3 / ( gm1 + 4 gds3 )
A0 = gm1 / gm A(s) = Ao wo s / ( s2 + wo s / Q + wo2 ) is the filter gain
wo = √(( gm2 + gm4 gmo2) / c2 ) is the resonance frequency
Q = gm / gm4 is the quality factor
C is larger than the parasitic caps
Q is chosen around 4 and 5
Va = ( gm1 Vin + gm3 Vb – gm4 Va ) / (sC + g01 + g03 + g04 )
Vb = -gm2 Va / (sC + g02 ) where goi represents the output impedance of the device.
A(s) = Va / Vin = gm1 ( sC + g02 ) / ( s2 C + sC (gm4 + g02 + go ) + gm3gm2 + gm4g02 +
g0g0` where g0` = g01 + g03 + g04
This has a complex pole and a zero and we simplify it taking the 2 and 3 cell to be the
same .
Figure B1 Small Signal Circuit
Design followed :
1) Got the small signal circuit and got the expressions to normal standard forms and
got expressions for filter parameters.
2) Started with reasonable value of Gm and then for the given gain designed Gm1
3) For quality factor of 4 designed the Gm4
4) Designed each individual cell such that all the transistors required operated as
needed and got the functionality .
5) Designed a CMFB to control the biasing points to keep the system well balanced
and maintain the DC operating points.
Figure B2 Gm-C Selective Amplifier
Figure B3 Gm-Cell
Figure B4 CMFB Circuit
Appendix C Matching Oscillator
Matching Oscillator Operation :
The GNL block is a nonlinear negative transconductor to ensure the oscillation and
regulate the signal amplitude. To obtain the desired nonlinear characteristic a cross
couples pair is added to the cell. This is equivalent to a negative conductance thereby
causing oscillations to build up when connected to the 2 integrator loop which behaves
like a LC resonant circuit. The amplitude of the oscillations increases until the current
flowing through the GNL has no more components at the resonant frequency .
The center frequency of the BPF Fc is assumed to be locked at the chopper frequency.
But in reality there is a tuning error between fchop and fc. This error
Design :
 Supplies: 2V and GND
 Bias current: Gn1 50uA
Gm 80uA
 Power dissipation: 280uW
Va = gm Vb / ( sC + go – gn1 )
Vb = -gm Va / ( sC + go ) where go is the output impedence of each transconductor.
Vout = Va = -gm2 Vout / ( sC + go – gn1 ) ( sC + go )
Vout = {s2 C2 + s(Cgo + C(go – gn1)) + go(go – gn1 ) + gm2 } * ⌂V
Where ⌂V represents the deviation appeared in the signal path causing oscillations .
The GNL block ensures oscillations and regulates the signal amplitude.
W = √ (gm2 – ( gn1 / 2 ) 2 ) / C
GNL
Figure C1 Proposed Oscillator Configuration
Figure C2 Oscillator Circuit
Figure C3 Small Signal Circuit
References
1. C.C. Enz, G.C. Temes "Circuit Techniques for Reducing the Effects of Op-Amp
Imperfections: Autozeroing, Correlated Double Sampling, and Chopper
Stabilization," in Proc. IEEE Vol. 84. pp 1584-1614 November 1996
2. Y. Hu, M. Sawan "CMOS Front-end Amplifier Dedicated to Monitor Very Low
Amplitude Signla from Implantable Sensors", Proc. 43rd Midwest Symposium on
Circuits and Systems, Aug. 8-11, 2000
3. C. Menolti, Q Huang, "A Low-Noise CMOS Instrumentation Amplifier for
Thermoelectric Infrared Detectors", IEEE J. Solid-State Circ. Vol. 32, pp. 968976, July 1997
4. F. Krumenacher, N. Joehl, "A 4-MHz CMOS Continuous-Time Filter with OnChip Automatic Tuning", IEEE J. Solid-State Circuits, vol. 23, pp. 750-758, June
1988
5. Harb, Yana Hu, M. Sawan, "New CMOS Instrumentation Amplifier Dedicated to
Very-Low Amplitude Signal Application", ICECS, 1999
6. Jose Silva-Martinez, M. Steyaert, W. Sansen, “High-Performance CMOS
Continuous –Time Filters”,1994
7. Paul R.Gray, Robert G.Meyer, “ Analysis and Design of Analog Integrated
Circuits”,1993
8. Jaime E. Kardontchik, “ Introduction to the design of Transconductor-Capacitor
Filters”,1992
9. M. Banu, Y. Tsividis, “ An Elliptic Continuous-Time Filter with On-Chip
Automatic Tuning”,IEEE J.Solid-State Circuits, vol. Sc-20,pp 1114-1121,Dec
1985
10. C.Yoo,SW Lee, W.Kim, “ A 1.5-V,4Mhz CMOS Continuous-Time Filter with a
Single-Integrator Based Tuning”, IEEE J. Solid State Circuits, vol 33,pp18-27,Jan
1998
11. R.H. Zele, D.J. Allstot, “ Low-Power CMOS Continuous Time Filters”,IEEE J.
Solid State Circuits,vol.31,pp 157-168,Feb1996