Download [0711-000053][2016 C..

The Demonstration and Characterization of In-situ SiNx/AlGaN/GaN HEMT on
6-inch Silicon on Insulator (SOI) Substrate
Hao-Yu-Wang, Li-Yi Peng, Yuan-Hsiang Cheng, Hsien-Chin Chiu
Department of Electronics Engineering, Chang Gung University
Taoyuan, Taiwan, R.O.C
e-mail: [email protected] Phone:+886-3-2118800 FAX:+886-3-2118507
Keywords: Semiconductor Devices , Gallium Nitride, Silicon on Insulator (SOI) Substrate, Silicon Nitride
Abstract
In this work, AlGaN/GaN high electron mobility transistors (HEMTs) with an unintentionally doped (UID)
u-GaN buffer and 15nm of In-situ SiNx on silicon-on-insulator (SOI) substrates were presented for RF
applications. In order to investigate the effects of the SOI
substrates to device characteristics, HEMT devices on SOI
were fabricated alongside with same structure on high
resistance Silicon (HR-Si) substrate and also alongside
with the conventional devices without In-situ SiNx on high
resistance Silicon (HR-Si) substrate to clarify the influence
of the in-situ SiNx . Experimentally, the SOI substrate
device showed better DC, breakdown voltage and RF
characteristics compared to devices on HR-Si. These advantages suggest that the SOI substrate device is suitable
for high speed and high-power integrated circuit applications.
INTRODUCTION
The wide bandgap, high breakdown field, and saturation
electron velocity of gallium nitride (GaN) make it an ideal
candidate for a high-power and high-speed transistor application. As has been demonstrated, high-electron-mobility transistors (HEMTs) realized on GaN have far higher output
power density as compared with Si-based laterally diffused
MOS transistors and GaAs MESFETs. In recent years, there
has been an increasing attention to GaN-on-Si integration,
leveraging the low-cost Si substrate to provide a cost economical solution for large-scale GaN wafer production [1].
epitaxial structure. The structure consisted of 1.7 μm UID
GaN buffer, 18 nm UID Al0.24Ga0.76N barrier and 15nm in-situ
SiNx. Two different types of substrates, 500μm SOI substrate
and 1000μm HR-si (>6000 /) substrate were used to grow
the same device structure. A third device variation—identical
to the HR-Si device but without 15nm in-situ SiNx was also
investigated.
During the fabrication of the device, the active region was
protected by a photoresist and the mesa isolation region was
removed in a reactive ion etching (RIE) chamber, using BCl 3
+ Cl2 mixed gas plasma. At ohmic contacts area, we used the
CF4 + O2 mixed gas plasma to remove the SiNx. Then ohmic
contacts were prepared using electron beam evaporation for a
multilayered Ti/Al/Ni/Au (30 nm/125 nm/50 nm/200 nm) sequence, followed by rapid thermal annealing (RTA) at 850 ℃
for 30s, in a nitrogen-rich ambient.
After ohmic formation, the Ni/Au gate electrodes with a
gate width of 50μm and gate length of 2μm were deposited
on 15 nm-thick SiNx (MOS-HEMT) and Ni/Au pad electrodes
were formed layer. The devices have a gate-to-source spacing
of 2μm, and a gate-to-drain distance varying from 3μm.
Lastly, 150 nm of SiO2 was deposited for passivation.
Driven by the market demanding continual innovation
and new mobile emerging standards, selection of the right
substrate technology can provide strategic advantages for
the high speed digital circuits, analog, and RF front end
modules on the same chip. Due to the lossy nature of the
silicon common handle substrate, digital switching noise
can be easily injected into and propagate through the entire
silicon substrate and affect the sensitive on-chip analog and
RF circuitry. [2] In this work, we have investigated AlGaN/GaN HEMTs utilizing on silicon-on-insulator (SOI)
substrates as well as traditional high resistance Silicon
(HR-Si) substrates. Measured the DC and the RF characteristic of both types of devices are reported.
DEVICE STRUCTURE AND FABRICATION
Figure 1 shows the cross-sectional schematic and scanning
electron microscope (SEM) profile of the fabricated device
Fig. 1 The cross-sectional structure (SEM)
(b) Raman
AlGaN
Intensity (CPS)
1M
567.13cm-1
566.38cm-1
3x104
Si3N4 (201)
100k
565.25cm-1
SiO2 (101)
10k
2x104
Si3N4 (200)
tensile stress
1k
1x10
Intensity(a.u.)
Si (111)
4x104
Si-HR Non in-situ
Si-HR w/o in-situ
SOI
w/o in-situ
GaN(0002)
4
100
540
20 22 24 26 28 30 32 34 36 38 540
40 550
2-theta (deg)
560
570
0
590
580
Raman shift (cm-1)
Drain to Source current, IDS (mA/mm)
(a) XRD
10M
700
600
500
SOI with-insitu
300K
500K
RDS,ON= 8.38 mΩ-mm
RDS,ON= 11.3 mΩ-mm
Si-HR with-insitu
300K
500K
RDS,ON= 11.1 mΩ-mm
RDS,ON= 18.7 mΩ-mm
Si-HR Non-insitu
300K
500K
RDS,ON= 8.47 mΩ-mm
RDS,ON= 27.1 mΩ-mm
VGS= 2~-6V
Step=-2V
400
300
200
100
0
Fig. 2 (a) 2θ-ω X-ray diffraction (XRD), (b) Raman characteristics of
both devices
0
5
10 15 20
0 5 10 15 20
0 5 10 15 20
Drain to Source Voltage, VDS (Volts)
Fig. 4 IDS-VDS characteristics for devices
DEVICE CHARACTERISTICS AND DISCUSSIONS
Drain to Source current, IDS (mA/mm)
105
104
103
300K
500K
VDS = 10 V
300K
500K
VDS = 10 V
300K
500K
VDS = 10 V
10-2
102
10
1
10
0
10
-1
10
-2
S.S.=0.27 V/dec
10
S.S.=0.48 V/dec
S.S.=0.30 V/dec
VBR= 160V
VBR= 270V
-3
VBR= 315V
10-5
10-6
10-4
10-6
VGS = -12 V
10-4
S.S.=0.64 V/dec
10-3
10-5
Si-HR
Si-HR SiNx
SOI
SiNx
10-1
S.S.=0.34V/dec
S.S.=0.44 V/dec
The three-terminal breakdown voltages (VBR) of devices with a 4 μm drain-to-source spacing were measured using an Agilent B1505A measurement system and the both
substrates were floating during the measurement. Figure 5
plots the measurements thus made. In this study, VBR is defined as the voltage at which a drain leakage current between
the drain and the source terminals reaches 1 mA/mm at a V GS
of − 12 V. The drain-to-source (IDS) leakage current of AlGaN/GaN HEMT on HR-Si substrate increases rapidly following an increase of VDS and its VBR is 270 V. The SiO2 layer
in SOI substrate provides an energy barrier that blocks the
electrons conduction vertically and significantly improves the
VBR values to 315 V. Moreover, the low substrate leakage
current due to current blocking effect provided by SiO2 layer
in SOI substrate was also beneficial for improving the ideality
factor and Schottky barrier height (SBH) of the device on SOI
substrate.
100
Drain-to-Source current, IDS (mA/mm)
Fig. 2(a) shows 2θ-ω X-ray diffraction (XRD) profiles
for AlGaN/GaN heterostructures on SOI and HR-Si substrate,
respectively. The curves of these two samples have clear SiO2,
GaN, AlGaN,SiNx peaks and fringes, indicating that the samples have flat surfaces and abrupt heterointerfaces. In order to
guarantee the stress release phenomenon of 6 inch SOI substrate caused by large lattice mismatch at the GaN/Si interface,
Micro-Raman spectroscopy was performed on both wafers. As
shown in Fig. 2(b), the E2 peak for the wafer on SOI substrate
was found to be 565 cm−1 and measured results is similar to
the standard freestanding GaN film value (567.4 cm−1). As
compared to the device on HR-Si substrate (567.1 cm−1), an
obvious tensile stress in the GaN was observed for the samples on HR-Si substrate. The films on SOI substrate exhibits a
better stress release performance which is beneficial for improving long-term operation reliability .
10-7
Si-HR
-8 -6 -4 -2 0
Si-HR with SiNx
2 -8 -6 -4 -2 0
SOI with SiNx
2 -8 -6 -4 -2 0
2
Gate to Source Voltage, VGS (Volts)
10-8
-50
0
50
100
150
200
250
300
350
Drain-to-source voltage, VDS (Volts)
Fig.3 the subthreshold swing slope of devices.
Fig. 5 Off-state breakdown measured of both devices.
As to the transistor DC performance shown in Fig. 3 for
HEMTs on SOI substrate, the subthreshold swing slope (S.S)
was also improved from 340mV/dec to 270mV/dec at 300K
compared to the device on HR-Si substrate. Fig. 4 plots the
measured IDS-VDS characteristics for devices. The pinch-off
voltage and maximum IDS are −5.4 V and 465 mA/mm for the
device on HR-Si substrate and these values are −5.2 V and
528mA/mm for the device on SOI substrate. The higher current density in the device on SOI substrate was concluded to
the lower epitaxy film stress.
In order to analyze the trapping/de-trapping phenomena in
these HEMTs, the 1/f noise spectra for the three devices were
measured at various gate bias voltages. The mobility fluctuation mechanism dominates the drain current noise spectra
(SID=I2D) when the slope of the gate overdrive voltage (VGS–
Vth), which depends on (SID=I2D) density approaches –1.
Fig.6(a) plots the frequency-dependent SID=I2D density at various VGS–Vth bias points, at VDS = 10 V and 300 K. The differences between the SID=I2D densities of the three devices
25
α q
= fWLC |VH
GS −Vth |
where f is the frequency, Ci is the unit capacitance of the
gate insulator, W is the gate width of the device , L is the gate
length of the device, q is the elementary electronic charge and
H is the Hooge constant, which is another noise parameter
that is used to discriminate the 1/f noise. As shown in Fig. 7,
the measured noise supports Hooge’s mobility model and the
H value for the device on SOI substrate is lower than that of
the other devices, at 300 K. Furthermore, the device on SOI
substrate exhibits a smaller variation in H than the other devices, at various temperature from 300 K to 500 K.
10-6
20
80
5
10
-8
10
-8
-9
Si-HR
Si-HR with SiNx
SOI
with SiNx
-5
20
-10
-25
-20
10
-2
-5
0
0
10
5
40
SOI
HR
50
35
30
40
25
30
20
15
20
10
1
10-10
5
0
8
12
16
20
Drain-to-source voltage, (Voltage)
0
Fig. 8 Output power and PAE versus input power at 900 MHz of SOI
substrate and HR-Si substrate.
40
FMax
Si-HR
FT
Gain(dB)
10-4
Si-HR with SiNx
10-2
Si-HR with SiNx
VDS = 10V
VGS = -4.2V
Si-HR
VDS = 10V
VGS = -1.1V
30
10-3
10-1
-10
Input Power (dBm)
Fig. 6 (a) Normalized SID=I2D density with various VGS–Vth operations (b)
SID=I2D versus VGS–Vth at a fixed frequency of 100 Hz for three devices at
300 K.
10
-15
10
20
40 60 80 0.1
VGSVTH (V)
Freqency (Hz)
-1
40
PAE
60
Slope = -1.232
@100 Hz
@VGSVTH = 0.8V
60
Output Power
0
Output Power(dBm)
-7
10-9
Hooge Constant (H)
SOI
HR Si
-15
-30
SiD/IDS2 @100Hz (Hz-1)
SiD/IDS2 (Hz-1)
Substrate
10
10-7
Slope = -0.962
10
Gain
15
Slope = -1.073
10
100
Power Add Efficieny (%)
i
Output Power(dBm) & Gain (dB)
SID
I2 D
The films on SOI substrate exhibits a better stress release
performance which is beneficial for improving long-term operation reliability .When VGS–Vth is low, the noise mechanism
is influenced by fluctuation on the number of carriers, due to
the carrier noise. Based on this analysis, the carrier trapping
between the metal gate and AlGaN results in an increase in H
for the traditional HEMT, especially in the sub-threshold region, but a flat distribution of H at various overdrive voltages
is observed for the the device on SOI substrate, which demonstrates that the GaN on SOI substrate device has a better interlayer, lower gate leakage current and greater linearity.
Power Add Efficieny (%)
increases as the gate overdrive value increases.
Fig.6(b) shows the slope at 100 Hz to be –1.073 for the
traditional HEMT and –1.232 and –0.962 for the device on
HR-Si substrate and the device on SOI substrate, respectively.
These experimental results show that the fluctuation in the
device on SOI substrate is mobility fluctuation, because the
curve of VGS–Vth as a function of SID=I2D density is close to –1.
The tunneling of charge carriers in the channel toward the
Schottky junction is one of the main determinants for the single-gate switch device. When 1/f noise is primarily due to
mobility fluctuations, SID=I2D can be expressed by the following equation :
10.1GHz
20
SOI with SiNx
VDS = 10V
VGS = -4.1V
21.2GHz
15.6GHz
10-3
300K
400K
500K
10-4
10
-1
10
-2
SOI with SiNx
10
3.2GHz
0
10-3
100M
1G
5.2GHz
10G100M
1G
9.1GHz
10G100M
1G
10G
Frequency(Hz)
10-4
0.1
0.2
0.3
0.4
VGSVTH (V)
0.5
0.6
Fig. 7 The Hooge factors versus VGS–Vth at 300 K to 500 K
Fig.9 Measured S parameters of both structures
The power performances of the SOI and HR-Si two sub-
strates with in-situ SiNx devices were measured at 900 MHz
and tuned for maximum PAE match. The RF performances of
SOI and HR-Si two substrates devices. From Fig.8, it can be
clearly observed that the SOI substrate device is the outstanding one. The output power is 18 dBm with 30.17% PAE and
15 dB linear gain for SOI substrate device. In contrast to the
HR-Si substrate device, the PAE and gain were both improved.
The RF performance of these devices was characterized
from 0.1 to 20 GHz using an Agilent Technologies E8364C
network analyzer. The system was calibrated with a
short-open load-through calibration standard. The calibration
was verified by insuring that both S12 and S21 of the through
standard are less than ± 0.01 dB and that both S 11 and S22 are
less than −45 dB within the measured frequency range after
the calibration [4]. On-wafer open and short patterns were
used to subtract the effect of parasitic pad capacitances and
inductances from the measured S-parameters [5].
Fig.9 shows the RF performance for the 2μm gate length
device at VDS = 10 V and VGS = −4.4 V the current gain cutoff
frequency (fT) of 9.1 GHz and fmax of 21.2 GHz for the were
calculated for SOI substrate device. A fT of 5.2 GHz and fmax
of 15.6 GHz of the HR-Si substrate device.
CONCLUSION
In summary, we use of the SOI substrate technology on
the fabrication of the AlGaN/GaN HEMT was realized successfully. The fabrication HEMT device on SOI substrate
showed superior DC and RF performance improved. Due to
the RF characteristic properties, SOI substrate is a promising
technology for highly reliable and high performance HEMT
devices and circuits.
REFERENCES
[1] T. Li, M. Mastro, and A. Dadgar, III–V Compound Semiconductors:Integration With Silicon-Based Microelectronics. Boca Raton, FL,
USA:CRC Press, 2010.
[2] C. Soens, G. Van der Plas, P. Wambacq, S. Donnay, and M. Kuijk, “Performance degradation of LC-tank VCOs by impact of digital switching
noise in lightly doped substrates,” IEEE Solid-State Circuits, vol. 40, no.
7, pp. 1472–1481, Jul. 2005.
[3] Chiu H.C, Wu JH, Yang CW, Huang FH, Kao HL. Low-frequency noise
in enhancement-mode GaN MOS–HEMTs by using stacked Al2O3/Ga2O3/
Gd2O3 gate dielectric. IEEE Electron Dev Lett 2012;33(7).
[4] D.-H. Kim and J. A. del Alamo, “30-nm InAs pseudomorphic HEMTs on
an InP substrate with a current-gain cutoff frequency of 628 GHz,” IEEE
Electron Device Lett., vol. 29, no. 8, pp. 830–833, Aug. 2008.
[5] H. Matsuzaki, T. Maruyama, T. Koasugi, H. Takahashi, M. Tokumitsu, and
T. Enoki, “Lateral scale down of InGaAs/InAs composite-channel HEMTs
with tungsten-based tiered ohmic structure for 2-S/mm gm and 500-GHz
fT ,” IEEE Trans. Electron Devices, vol. 54, no. 3, pp. 378–384, Mar.
2007.
ACRONYMS
SOI :Silicon on Insulator
HR-Si : high resistance Silicon
SiNx :Silicon Nitride
GaN : Gallium Nitride