Download The MOS-transistor The Diode

Advanced Digital IC-Design
The MOS-transistor
This lecture will
Refresh the MOS-transistor
function and models
Especially short channel effects
Especially,
Digital IC-Design
The Diode
The Diode in an IC-device
Diodes appears in all MOS-transistors
(the drain & source area)
They have parasitics that affects the
performance (speed, power)
Diodes should always
y be backward
biased (negative VBS)
1
Diode - The Simplest IC-device
Advanced Digital IC-Design
ICstructure
Discrete
component
p
SiO2
Metal
p+
n+
Semiconductor
n+
p+
The MOS Transistor
p-
pn-junctions
The MOS-transistor: An Old Invention
In 1925, Julius Edgar Lilienfeld described the
first MOSFET structure
What is a MOS-transistor?
MOS = ”Metal Oxide Semiconductor”
Polysilicon
- U.S.
U S Patent in 1930
In early thirties, a similar structure was shown
by Oskar Heil
- British Patent in 1935
None of them built a working component
The first working MOS-transistor was shown in
the early sixties
SiO2
Metal
Oxide
Silicon, doped
Semiconductor
2
The MOS-transistor (or MOSFET)
N-MOS Transistor
Most important device in digital design
Gate
Bulk
Source
Drain
n+
n+
V
Very
good
d as a switch
i h
Relatively few parasitics
Each box in the
layout represents
a mask or a step
in the process
Rather low power consumption
High integration density
++
pp
Thin
Oxide
p
-
Simple manufacturing
Mask
Layout
Economical for large complex circuits
P-MOS Transistor
How does it Work?
Technologies
Gate
Bulk
Source
Drain
N-Well
N W ll
VGS must be
Opens a
lager than a
channel
threshold VT
P-Well
++
np
p
+
p
Twin-Tub
p
VDS drives
a current ID
VDS
VGS
+
n-
Silicon
St
Structure
t
ID
N-Well
The gate length
sets the name of
the technology
Gate
Source
Drain
3
What is a MOS Transistor?
MOS – a Four Terminal Device
Gate voltage controls the current from drain to source
A Switch
VGS
Circuit Symbol
VGS
G
Ron
eq
S
D
Source connected to higher potential for p-channel devices
(often to VDD)
G
S
Source connected to lower potential for n-channel devices
((often to GND))
D
Bulk keeps the substrate at a stable potential. If not shown
– it is assumed to be connected to the supply/GND.
Source
Gate
Gate
Drain
Infinite resistance when VGS < VT
Source
Req when VGS ≥ VT
VT = Threshold voltage
Bulk (Body)
Important Dimensions
How does the Transistor Work?
Technology
development:
Gate
Drain
Source
W
tox
Drain
Bulk (Body)
1993: 0.6 um
2003: 65 nm
2013: 18 nm?
When VGS is slightly increased
g
g are attracted
Negative
charges
A depletion region is formed
VGS > 0
L
n+
The technology is
named after the
gate length L
“Diode area”
n+
p-
Depletion
Region
4
How does it Work?
Linear Region (Resistive Operation)
When VGS is increased above VT
VDS is increased slightly
More negative than positive charges are attracted
close to the gate (turns to n-type material)
Horizontal E-field from drain to source
A channel is formed (Strong inversion)
A current ID is established
VGS > VT
VGS > VT
VDS<VGS-VT
ID
n+
n+
n+
n-channel
-
p
Depletion
Region
Linear Region (Resistive Operation)
ID is proportional to the vertical E-field
n-channel
p-
ƒ i.e. to the charge velocity caused by the drain voltage VDS
I D = k´n
VGS forms a
vertical E-field
n+
n+
ID
VDS establish a
horizontal E-field p-
V
W
(VGS − VT − DS )VDS
2
L
Depletion
Region
Linear Region (Resistive Operation)
I D = μn Q ξ W
μn = Electron mobility
ξ = E-field over the channel
Q ∼ VGS −VT
# of charges attracted by the gate
Q ∼ VDS
Less charges in drain region
ƒ i.e. to the # of charges attracted by the gate voltage VGS
ID is proportional to the horizontal E-field
n+
V
ξ = DS
L
I D = k´n
V
W
(VGS - VT - DS ) VDS
2
L
From charge conc.
(k 'n = μnCox )
From Horizontal E-Field
5
Saturation Region
Saturation Region
VDS = VGS – VT
Strong inversion reached precisely (i.e. VGD = VT)
No channel close to the drain
VGS > VT
ID
n+
”VDS /2"
p-
Channel Length Modulation
VDS > VGS-VT
V
W
(VGS − VT − DS )VDS
L
2
W
V −V
I D = k´n (VGS − VT − GS T )(VGS − VT )
L
2
k´ W
I D = n (VGS − VT ) 2
2 L
I D = k´n
VDS=VGS-VT
n+
Insert VDS = VGS - VT in the linear equation
Channel Length Modulation
⇒ Pinch off
Saturation
The effective channel length
g is modulated by
y VDS
VDS > VGS-VT
Electrons are injected through the depletion region
VGS>VT
VDS>VGS-VT
ID
n+
n+
L´
I D = k´n
W
(VGS − VT ) 2 (1 + λVDS )
L
Pinch off
λ = Empirical constant
L
6
The Threshold Voltage VT
The Bulk (Body) Potential
The substrate is slightly doped (p- for NMOS)
The bulk is most often connected to GND (VDD for PMOS)
There are always free electrons in the substrate
Negative VSB opens the diode; Not Allowed
T fform a channel,
To
h
l we need
d to
t attract
tt
t these
th
negative
ti
charges
h
Positive
P
iti
VSB makes
k it h
harder
d tto attract
tt
t negative
ti
charges
h
tto
the channel
The threshold is when the number of negative and positive
charges are equal
That is, the threshold voltage will increase
The value of VT is thus set by the p-doping concentration
VSB
VGS > VT
p+
+
n
VGS
n+
n+
+
n
n-channel
p-
Strongly p-doped
Depletion
Region
p-
The Threshold Voltage VT
MOS Model for Long Channels
VT = VT 0 + γ ( − 2φF + VSB − − 2φF )
Widely used model for manual calculations
2
φF = Fermi potential
W
V
((VGS − VT )VDS − DS )(1 + λVDS )
L
2
k´n W
2
≥ VGS − VT ; I D =
(VGS − VT ) (1 + λVDS )
2 L
VDS ≤ VGS − VT ; I D = k´n
γ increases with the acceptor concentration
VDS
Low threshold ⇒ Low voltage transistors but
they
y are leaky
y
k´n = μ n Cox
Two threshold voltage technologies can be used
for low power
VT = VT 0 + γ ( − 2φF + VSB − − 2φF )
Added to avoid
discontinuity
y
7
Velocity & Mobility
Velocity & Mobility
The electron (hole) velocity is related to the mobility
(μ )
The electron (hole) velocity is related to the mobility
The velocity is also dependent on the E-field
m2
= Electron mobility
Vs
m2
μ p = 0.013
= Hole mobility
Vs
μn = 0.038
Typical
0.35μm
technology
(μ )
(ξ )
m
s
m
υ p = μ pξ
s
υn = μnξ
The mobility is dependent on doping concentration …
Often determined empirically
Note that the electron mobility is about 3 times higher
Velocity Saturation (υ sat )
VDS forms a horizontal E-field
Velocity Saturation (υ sat )
(ξ )
υn = μn ξEDS
An increased E-field leads to higher electron velocity
However at a critical E-field
E field (ξ c ), the velocity saturates due
to collisions with other atoms
Constant Velocity
it y
m
≈ 105
for both electrons and holes
s
Drain
n+
n+
ξ
ns
Source
ta
nt
Mo
b il
νsat = 105 m/s
Co
υsat
ν n (m/s)
The mobility is
not constant
when velocity
saturation is
reached
EDS [V/um]
VDS establish a horizontal E-fieldp
0
ξE c
sat
8
ID versus VDS
ID versus VGS
ID (mA)
0.5
-4
6
Long channel
Long-channel
model
0.4
5
2
4
For both
1
2
0
0
0
0.5
1.0
1.5
2.0
quadratic
d ti
0.5
1
1.5
2
2.5
0
0
0.5
1
VGS(V)
VDS (V)
0
0.5
1
VDSAT = 0.63 V
0.1
1.5
3
Short-channel
model
0.2
linear
quadratic
ID (A)
VGS = VDD = 2.5
0.3
-4
x 10
2.5
ID (A)
VGS-VT = 2.5 - 0.43 = 2.07 V
x 10
Long Channel
1.5
2
2.5
VGS(V)
Short Channel
2.5
ID versus VDS
Model for Manual Analysis
Linear ID(VGS)
Quadratic ID(VGS)
VDS = VGS - VT
06
0.6
A first order model of the velocity
0 25
0.25
ID (mA)
0.5
VGS= 2.5
ID (mA)
VGS= 2.5
0.2
VGS= 2.0
0.15
0.3
0.2
VGS= 1.5
0.1
VGS= 1.0
0
⎧υ = μn ξ
⎪
⎨
⎪υ = υ = μ ξ
sat
n
c
⎩
VGS= 2.0
0.4
0.1
VGS= 1.5
0 05
0.05
VGS= 1.0
0
0
0.5
1
1.5
VDS (V)
Long Channel
2
2.5
0
0.5
1
1.5
2
for ξ ≤ ξ c
f ξ ≥ ξc
for
2.5
VDS (V)
Short Channel
9
Model for Manual Analysis
A first order model of the velocity
y
saturated region:
I DSAT
VDSAT 2
W
= μn Cox ((VGS −VT )VDSAT −
)
2
L
A Unified Model for Manual Analysis
I D = kn'
A Unified Model for Manual Analysis
Vmin 2
W
I D = k ((VGS −VT )Vmin −
)(1+ λVDS )
L
2
'
n
Vmin = min(VGS −VT , VDS , VDSAT )
Three Regions
VDSAT
V 2
W
((VGS −VT )VDS − DS )(1+ λVDS ) Resistive
2
L
0.63 V
0 15
0.15
ID =
kn' W
(VGS −VT )2 (1+ λVDS ) Saturated
2 L
I D = kn'
V 2
W
((VGS −VT )VDSAT − DSAT )(1+ λVDS ) Velocity saturated
L
2
VGS = 2 V
I D (mA)
Velocity
saturated
Linear
0.1
VGS = 1.5 V
0.5
VGS = 1 V
VGS-VT
0
0
Saturated
1
VDS (V)
2
10
The PMOS Transistor
Sub-threshold Region
Velocity saturation is less pronounced for PMOS
due to lower mobility
The sub threshold drain current have an exponential
relation to the gate voltage (compare to bipolar)
-4
0
x 10
VGS = -1.0V
Assume that
all variables
are negative!
VGS = -1.5V
ID (A)
-0.4
-0.6
-0.8
-1
-2.5
VGS = -2.0V
2 0V
Super-threshold
region (Super-VT)
ln(ID)
-0.2
Sub-threshold
region (Sub-VT)
VGS = -2.5V
-2
-1.5
-1
-0.5
VT
0
VDS (V)
MOS Dynamic Behavior
Junction Capacitance
- Diode areas
- Divided in two parts - area and side wall
2
Gate
Drain
CGS
CGD
n+
n+
CG
CSB
CDB
tox
Channel Cap.
Junction Cap.
p
Gate Capacitance
- Gate to Bulk
- Gate to Source/Drain
3
VGS (V)
MOS Capacitances
Source
yp of Capacitance
p
Two Types
1
Overlap Cap.
Xd
11
Junction Capacitance
Junction Capacitance
Drain/Source Diffusion
CDiff = CBot + CSW
G
at
e
Bottom
Ch To
an wa
ne rds
l
Don’t count the wall
towards the channel
CDiff = CBot + CSW
CBot = Cj × Area
CSW = CjSW × Perimeter
Cj in F/um2
CjSW in F/um
Nonlinear: dependent on the diode voltage
W
Side
Wall
Ls
Gate Capacitance
Channel Capacitance
Gate
Source
Drain
Cut off
Xd
CG = Cox × W × Leff
Leff
CGS
CG depends
p
on the region
g
COX in F/um2
n+
Linear
n+
n+
n+
CGD
Saturation
CGB
n+
n+
12
Overlap Capacitance
Conclusions - Static Behavior
Gate
CGD = Cox × W × Xd
CGS = Cox × W × Xd
Source
Xd
Cox in F/um2
Or
CGD = Co × W
CGS = Co × W
Drain
I D = kn'
ID =
Leff
CGS
CGD
CGB
V 2
W
((VGS −VT )VDS − DS )(1+ λVDS ) Resistive
2
L
kn' W
(VGS −VT )2 (1+ λVDS ) Saturated
2 L
I D = kn'
V 2
W
((VGS −VT )VDSAT − DSAT )(1+ λVDS ) Velocity saturated
L
2
Threshold
Voltage
Co in F/um
VT = VT 0 + γ ( −2φF + VSB − −2φF )
A Unified Model for Manual Analysis
Conclusions - Dynamic Behavior
Vmin 2
W
ID = k
((VGS −VT )Vmin −
)(1+ λVDS )
L
2
'
n
Vmin = min(VGS −VT , VDS , VDSAT )
CG = Cox × W × Leff
CGD = CGS = W × Cox
× Xd
CDiff = CBot + CSW
CBot = Cj × Area
VT = VT 0 + γ ( −2φF + VSB − −2φF )
Gate
Capacitance
CSW = CjSW × Perimeter
JJunction
ti
Capacitance
13