Download Driving circuit with high accuracy and large driving capability for

Vol. 35, No. 12
Journal of Semiconductors
December 2014
Driving circuit with high accuracy and large driving capability for high voltage
buck regulators
Li Yajun(李亚军)1; Ž , Lai Xinquan(来新泉)1 , Ye Qiang(叶强)2; Ž , and Yuan Bing(袁冰)2
1 Institute
2 Key
of Electronic CAD, Xidian University, Xi’an 710071, China
Laboratory of High-Speed Circuit Design and EMC, Ministry of Education, Xidian University, Xi’an 710071, China
Abstract: This paper presents a novel driving circuit for the high-side switch of high voltage buck regulators.
A 40 V P-channel lateral double-diffused metal–oxide–semiconductor device whose drain–source and drain–gate
can resist high voltage, but whose source–gate must be less than 5 V, is used as the high-side switch. The proposed
driving circuit provides a stable and accurate 5 V driving voltage for protecting the high-side switch from breakdown
and achieving low on-resistance and simple loop stability design. Furthermore, the driving circuit with excellent
driving capability decreases the switching loss and dead time is also developed to reduce the shoot-through current
loss. Therefore, power efficiency is greatly improved. An asynchronous buck regulator with the proposed technique
has been successfully fabricated by a 0.35 m CDMOS technology. From the results, compared with the accuracy of
16.38% of the driving voltage in conventional design, a high accuracy of 1.38% is achieved in this work. Moreover,
power efficiency is up to 95% at 12 V input and 5 V output.
Key words: high voltage; buck regulator; PLDMOS; driving circuit; dead time
DOI: 10.1088/1674-4926/35/12/125009
EEACC: 2570
1. Introduction
In recent years, high voltage buck regulators are widely
used in application fields such as displays, car chargers and
GPS devices owing to their low quiescent current, wide range
of input voltage, high efficiency and excellent driving capabilityŒ1; 2 . In high voltage buck regulators, P-channel lateral
double-diffused metal–oxide–semiconductor (PLDMOS) devices are usually used as the high-side switchŒ3 8 in order
to avoid using the bootstrap capacitor CBST Œ9; 10 and thus decrease the size and cost of printed circuit board (PCB). Nowadays, some silicon foundries offer process variants suitable for
devices with higher voltage ratings. Typically, however, the
gate–source breakdown voltage of a high voltage (HV) LDMOS device is well below its drain–source and drain–gate
breakdown voltagesŒ11 13 . Table 1 shows the operating voltages of some HV processes. From the table, it should be noted
that the operating voltages of drain–source and drain–gate are
both above 40 V while the gate–source operating voltage is
only 5 V. If we use ground as the gate voltage when the HV Pchannel high-side switch is on, the switch will be broken down
because of the high gate–source voltage, which would not happen in the design of low voltage buck regulators. Thus, in high
voltage design, a driving circuit with proper driving voltage for
high-side switch is very important. Moreover, because of the
large parasitic capacitance of the high-side switch for the consideration of power efficiency, the driving circuit should have
enough driving capability.
Figure 1 illustrates the transistor-level schematic of the
conventional PLDMOS driving circuitŒ14 , which consists of
a driving voltage generator, a level shifter and a buffer. In the
driving voltage generator, 3jVgs jŒ14; 15 is provided as the driv-
ing voltage VDV . But the voltage 3jVgs j has low accuracy due
to the variations of process parameters. Figure 2 illustrates the
simulation results of VDV under process corners FF, TT and SS
and temperature from 40 to 125 ıC. Compared with the target value of 5 V, VDV varies from 4.181 (–16.38%) to 5.730 V
(14.60%). The driving voltage decides the on-resistance of the
MP and the large variation of on-resistance makes the loop stability design of the regulator more difficult. Moreover, the driving capability of VINL is commonly not big enough to pull down
the driving signal VDRV for the consideration of area consumption, resulting in the slow speed of turning on the MP and thus
the switching loss is increased. At the same time, a large shootthrough current loss may occur in the buffer because M15 and
M16 with large scales may switch on simultaneously when the
gate driving signal VG goes high or falls down. Therefore, the
power efficiency is limited.
In this paper, a buck regulator with developed PLDMOS
driving circuit is presented. By this technique, an accurate and
stable driving voltage regulated by a feedback loop is obtained.
Furthermore, large driving capability with an auxiliary pull-
Table 1. Operating voltages of some HV processes.
Allowed operating voltage (V)
Technology
jVds j
jVgs j
jVdg j
Nuvoton 0.6 m 2-poly
40
5
40
3-metal CDMOS process
UMC 0.35 m 2-poly
40
5
40
5-metal CDMOS process
Dongbu HiTek 0.18 m
85
5
85
1-poly 6-metal BCD process
* Project supported by the National Natural Science Foundation of China (No. 61106026) and the Fundamental Research Funds for the
Central Universities of China (No. K50511020028).
† Corresponding author. Email: [email protected]; [email protected]
Received 19 August 2014, revised manuscript received 13 October 2014
© 2014 Chinese Institute of Electronics
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Li Yajun et al.
Fig. 1. Schematic of the conventional PLDMOS driving circuit.
Fig. 2. Simulation results of the driving voltage VDV .
down transistor and dead time control ensure high efficiency
is achieved. Section 2 introduces the working principle of the
proposed method thoroughly. Section 3 analyzes the loop stability of the proposed buck regulators. Experimental results are
presented in Section 4 and the conclusions are given in Section
5.
2. Proposed PLDMOS driving scheme for buck
regulators
2.1. Architecture
Figure 3 shows the architecture of a buck regulator with the
proposed PLDMOS driving scheme. VIN represents the power
supply and VO is the output voltage. L is an energy transferring
inductor and CO is an output filtering capacitor. RFB1 and RFB2
are feedback resistors for setting the output voltage. D is a freewheeling diode and RL is the load resistor. EA is the error amplifier and the compensation blockŒ16 18 ensures the stability
of the regulator. The soft-start module minimizes the inrush of
current and the output overshoot during normal startupŒ19; 20 .
The OSC module provides the operating frequency of the buck
regulator and the pulse width modulator (PWM) module provides the duty cycle. The logic block generates switching timing for the PLDMOS driving circuit to drive the high-side
switch MP. During normal operation, the buck regulator operates in fixed-frequency PWM mode. Each clock pulse from
Fig. 3. Architecture of a buck regulator with the proposed PLDMOS
driving scheme.
the OSC module turns on the MP. The current through the MP
is equal to the inductor current IL , which increases in a certain positive slope according to the inductor value and converter voltages. When the voltage-sense signal VRAMP becomes
higher than VCOMP , the MP is turned off and the freewheeling
diode D is turned on to attenuate inductor current until the beginning of the next clock cycle.
Figure 4 shows the schematic of the proposed PLDMOS
driving circuit. VIN is up to 36 V and VCC is the internal 5 V
power supply. Reference voltage VREF is 1.25 V in this design.
The bias voltage generator provides bias voltages for the driving voltage generator, which generates an accurate and stable
driving voltage, for the MP is regulated by a feedback loop.
A simple level shifter is used to achieve the conversion from
VCTL to VLS . The buffer with dead time control and high driving capability drives the MP to transfer energy from the input
VIN to the output VO .
2.2. Bias voltage generator
The proposed bias voltage generator, as shown in Fig. 4,
consists of an error amplifier A, a feedback resistor R1 and a
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Fig. 4. Schematic of the proposed PLDMOS driving circuit.
resistor divider composed of R2 and R3 . The error amplifier A
is powered by VCC . M1 is an NLDMOS device, which protects
itself from breakdown because its drain–source should resist
high voltage. In this design,
Thus
R2 D R3 D 2R1 D 2R:
IREF D
VA D VIN
VB D VIN
(1)
VREF
VREF
D
;
R1
R
R3 IREF D VIN
(2)
2:5 V;
.R2 C R3 / IREF D VIN
5 V:
(3)
(4)
VA and VB provide the bias voltages and ensure the normal
operation of the driving voltage generator.
Fig. 5. Linearized model of the proposed driving voltage generator.
8
<gm.EA/ D gm2 D gm3 ;
2.3. Driving voltage generator
In order to overcome the drawbacks in the conventional
PLDMOS driving scheme and provide an accurate and stable
driving voltage, a novel driving voltage generator is proposed.
As shown in Fig. 4, the circuit consists of a differential pair
using input PMOS devices M2 and M3 with the same aspect
ratios, a current source IB1 , a feedback network composed of
resistors R4 and R5 with the feedback voltage VC , a current
mirror constituted by M6 and M7 with the same aspect ratios
and a compensation network, which consists of resistor RC and
capacitor CC , in order to ensure the stability of the loop. M4,
M5 and M8 are LDMOS devices. M4 and M5 biased by VB are
used to protect M2 and M3. M8 is required to protect itself from
breakdown because of its high drain–source voltage. M2–M7
and current source IB1 compose an error amplifier.
There is a negative feedback loop to control the driving
voltage VDV . If VDV goes lower, feedback voltage VC becomes
larger than VA , leading to the gate voltage VD of M8 increases,
thus the current through M8 goes larger, resulting in the decrease of VINL and an increase of VDV .
Linearized model of the proposed driving voltage generator is shown in Figure 5. gm.EA/ and RO.EA/ are the transconductance and the equivalent output resistance of the error amplifier, respectively.
:
RO.EA/ D .gm4 RO4 RO2 / k RO6 ;
(5)
where gmx and ROX are the transconductance and the smallsignal output resistance of MX in Fig. 4, respectively.
The transfer function from VC to VD is
H1 .s/ D
D
gm.EA/ RO.EA/ .1 C sRC CC /
1 C s RO.EA/ C RC CC
gm.EA/ RO.EA/ .1 C sRC CC /
;
1 C sRO.EA/ CC
RO.EA/ RC :
(6)
The transfer function from VD to VC is
gm.M8/ RO.M8/ k .R4 C R5 /
R4
H2 .s/ D
R4 C R5 1 C s RO.M8/ k .R4 C R5 / CO
D
gm.M8/ R4
;
1 C s .R4 C R5 / CO
RO.M8/ R4 ; R5 ;
(7)
where gm.M8/ and RO.M8/ are the transconductance and the
small-signal output resistance of M8, respectively.
The total open loop transfer function of the whole system
is given by
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Fig. 7. Simulation results of the feedback loop.
Fig. 6. Bode diagrams of the feedback loop.
H.s/ D H1 .s/H2 .s/:
(8)
There are two poles and one zero in H.s/. Each pole and
zero can be expressed as follows:
8
1
ˆ
;
fp1 D
ˆ
ˆ
ˆ
2RO.EA/ CC
ˆ
ˆ
<
1
fp2 D
;
ˆ
2
.R
C
R5 / CO
4
ˆ
ˆ
ˆ
ˆ
1
:̂fz1 D
:
2RC CC
(9)
Compensation capacitor CC and large RO.EA/ make fp1
the dominant pole. Output capacitor CO and small resistors
R4 and R5 make fp2 the high frequency pole, which is used
to lower the crossover frequency fc and filter high frequency
noise. Zero fz1 is always located around fp2 in order to improve the phase margin and ensure the stability of the circuit.
Therefore, as shown in Fig. 6, there is only one pole within the
crossover frequency and the loop is stable.
Gain and crossover frequency of the loop are, respectively
Av D gm.EA/ gm.M8/ RO.EA/ R4 ;
fc D Avfp1 D
gm.EA/ gm.M8/ R4
:
2 CC
(10)
(11)
Fig. 8. Simulation results of the driving voltage VDV .
Moreover
VIN C VINL
:
(15)
2
From Eqs. (3), (14) and (15), the driving voltage can be
expressed as follows:
VC D
VDV D VIN
Moreover, let
fz1 D fp2 ;
(12)
we can get the compensation resistor RC as follows:
RC D .R4 C R5 /
CO
:
CC
(13)
By designing the values of the parameters shown in
Eqs. (9)–(11) reasonably, we can get the stable feedback loop.
In this work, as shown in Fig. 7, a DC-gain of 71-dB and a
phase margin of 62ı are achieved, making sure the stability of
the circuit.
According to the analysis above, in steady state,
VC D VA :
(14)
VINL D 5 V:
(16)
Figure 8(a) illustrates the simulation results of VINL with
VIN from 8 to 36 V and the driving voltage is typically 5 V.
Figure 8(b) shows the simulation results of driving voltage under the condition of VIN D 24 V with the variations of process
corners and temperature. Compared with the 5 V target value,
VDV varies from 4.977 ( 0:46%) to 5.069 V (1.38%) and the
maximum variation in this design is only 8.45% of the conventional scheme. Therefore, high accuracy is achieved.
2.4. Level shifter
As shown in Fig. 4, a high voltage level shifter is developed in this design to achieve the conversion of different voltage levels. Compared with the complicated scheme proposed
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Li Yajun et al.
Fig. 9. Simulation results of the level shifter.
in Ref. [21], the developed method is very compact and the
circuit consists of a NMOS switch MS, a current source IB2 ,
a current mirror constituted by M10 and M11 with the aspect
ratios of 1 : K, a pull-up resistor R6 and a NLDMOS transistor
M9 to protect M11.
When VCTL D GND, the MS is off. M11 mirrors the current
through M10 and
I D KIB2 :
(17)
Therefore,
Fig. 10. Simulation results of the proposed buffer.
VLS D VIN
IR6 D VIN
KIB2 R6 :
(18)
By designing the values of the parameters shown in
Eq. (18) reasonably, we can get the proper lever shifter voltage we need. In this design,
VLS D VIN
5 V:
(19)
When VCTL D VCC , the MS is on and the node voltage VE
is pulled down to GND. M10 and M11 are both off and I D 0.
VLS is thus pulled up to VIN by R6 .
According to the analysis above, VCTL is converted to VLS ,
which can be expressed as follows:
8
<VIN ; VCTL D VCC ;
(20)
VLS D
:V
5 V; VCTL D GND:
IN
Figure 9 shows the simulation results of the proposed level
shifter. VLS with the information of the duty cycle is then
buffered to get the driving signal VDRV to control the MP.
2.5. Buffer
In order to avoid M12 and M13 conducting at the same
time and the large shoot-through current degrading the power
efficiency, a buffer with a dead time control is developed in
this paper. During the dead time, both M12 and M13 are off.
As shown in Fig. 4, the buffer consists of a NAND gate, a NOR
gate, six inverters, two time delay modules, a pull-up transistor
M12 and a pull-down transistor M13. The delay time produced
by the delay module is TD . The basic principle of the dead time
control is to use the feedback signals VP and VN to control the
gate driving signals such that M12 and M13 do not turn on simultaneously. It is important to note that, the driving capability of VINL is commonly not big enough for the consideration
of area consumption. Therefore, in this design, the PLDMOS
transistor M14, whose drain terminal is connected to GND, is
used to enhance the driving capability of pulling down the driving signal VDRV . There are two main stages when the regulator works normally, and the simulation results are illustrated in
Fig. 10.
(1) When VLS rises from low to high, as shown in
Fig. 10(a), the gate voltage VP is pulled up to high quickly,
turning off the pull-up transistor M12. After the delay time TD ,
signal VPD turns high to set the gate voltage VN1 low and the
gate voltage VN high, turning on the pull-down transistors M13
and M14. Then, driving signal VDRV deceases to low by the
pull-down currents IM13 and IM14 and the MP is switched on.
Because M12 is turned off before M13 and M14 are turned
on, there is no period when both the pull-up and pull-down
transistors are turned on simultaneously and thus no shootthrough power consumption. Moreover, the large pull-down
current through M14 flows to GND instead of VINL and therefore, the driving capability of VINL is greatly improved.
(2) When VLS falls from high to low, as shown in
Fig. 10(b), the gate voltage VN1 is pulled up to high and the
gate voltage VN is pulled down to low quickly, turning off the
pull-down transistors M13 and M14. After the delay time TD ,
signal VND turns low to set the gate voltage VP low, turning on
the pull-up transistor M12. Then, driving signal VDRV increases
to high by the pull-up current IM12 and the MP is switched off.
Because M13 and M14 are turned off before M12 is turned on,
there is no period when both the pull-up and pull-down transistors are turned on simultaneously and thus there is no shootthrough power consumption in this case, as well.
3. Loop stability
In order to ensure stable operation of the proposed buck
regulator, the voltage loop should be carefully designed. As
shown in Fig. 11, the linearized model of the regulator is com-
125009-5
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Li Yajun et al.
Fig. 12. Simulation results of the voltage loop.
Fig. 11. Linearized model of the proposed buck regulator.
posed of a resistor divider, an error amplifier and a modulator.
RESR is the equivalent series resistance of the output capacitor CO . RO and gm.EA/ are the equivalent output resistance
and the transconductance of the error amplifier, respectively.
gm.MOD/ is the transconductance of the modulator, which can
be expressed as followsŒ3; 8 :
gm.MOD/ D
IO
;
VCOMP
(21)
where IO is the change of load current and VCOMP is the
corresponding output voltage swing of the error amplifier.
The compensation network is composed of resistor RC and
capacitors CC and CC1 . Assuming RL RESR , RO RC and
CC CC1 , then each transfer function can be derived as follows:
H1 .s/ D
H2 .s/ D gm.EA/ RO
RFB2
;
RFB2 C RFB1
1 C sRC CC
;
.1 C sRO CC / .1 C sRC CC1 /
H3 .s/ D gm.MOD/ RL
1 C sRESR CO
:
1 C sRL CO
Fig. 13. Micrograph of the proposed buck regulator.
(22)
(23)
(24)
Total open loop transfer function of the regulator is given by
H.s/ D H1 .s/H2 .s/H3 .s/:
(25)
Gain and crossover frequency of the loop are, respectively
Av D gm.EA/ gm.MOD/ RO RL
fc D
RFB2
;
RFB1 C RFB2
gm.EA/ gm.MOD/ RC
RFB2
:
2 CO
RFB1 C RFB2
(26)
(27)
By designing the values of the parameters shown in
Eqs. (22)–(27) reasonably, we can get the stable voltage loop.
In this work, as shown in Fig. 12, DC-gain of 62-dB and phase
margin of 86ı are achieved, ensuring the stability of the proposed buck regulator.
4. Experimental results
A current-mode buck regulator with the proposed PLDMOS driving circuit has been fabricated using the 0.35 m
CDMOS process, and Figure 13 shows the micrograph of the
chip. The regulator is able to provide a maximum load current
of 3 A at input voltage ranging from 8 to 36 V. The output
voltage can be externally set from 1.18 to 12 V with a resistor divider. The operating frequency is 120 kHz and the energy
transferring inductor is 68 H. A 220 F output filtering capacitor is used to reduce the output ripple voltage and achieve
an excellent load transient response.
Figure 14(a) shows the measured driving voltage under the
condition of VIN D 12 V, VO D 5 V and TA D 40 to 125 ıC.
The variation of VDV is 13 mV under a wide range of temperatures, which is only 0.26% of the 5 V target value.
Figure 14(b) shows the line regulation of the driving voltage under the condition of VIN D 8–36 V, VO D 5 V and TA D
25 ıC. The variation of VDV is only 1.4 mV and the line regulation is less than 0.03% under a wide range of input voltages.
Figure 15(a) shows the load transient response under the
condition of VIN D 12 V, VO D 5 V and the load current steps
from 100 mA to 2.8 A. The undershoot voltage and overshoot
voltage are 150 and 160 mV, respectively. Figure 15(b) shows
the load transient response under the condition of VIN D 36 V,
VO D 5 V and the load current steps from 100 mA to 2.8 A. The
undershoot voltage and overshoot voltage are both 190 mV.
Figure 15(c) shows the load transient response under the condition of VIN D 12 V, VO D 1.8 V and the load current steps
from 100 mA to 2.8 A. The undershoot voltage and overshoot
125009-6
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Li Yajun et al.
Fig. 14. Experimental results.
Fig. 15. Experimental results of load transient response.
voltage are both 75 mV. Figure 15(d) shows the load transient
response under the condition of VIN D 36 V, VO D 12 V and
the load current steps from 100 mA to 2.8 A. The undershoot
voltage and overshoot voltage are both 400 mV. From the results, the proposed regulator works stably under a wide range
of input voltages and load currents.
Figure 16 shows the power efficiency of the proposed buck
regulator under different input voltages. Maximum efficiencies of 95%, 93.5% and 91.5% are obtained at the input voltages of 12, 24 and 36 V, respectively. Table 2 shows the performance comparison of the proposed buck regulator and the
EUP3466Œ22 under room temperature. From the comparison
results, high efficiency is achieved by using the proposed tech-
nique.
5. Conclusions
In this paper, an asynchronous buck regulator with the proposed driving technique is analyzed and implemented. By this
method, a stable and accurate 5 V driving voltage is provided to
protect the high-side switch. Low on-resistance minimizes the
conduction loss and a simple loop stability design is achieved.
Moreover, the high driving capability increases the switching
speed and thus the switching loss is reduced. Dead time is also
developed to avoid the shoot-through current loss. Therefore,
the power efficiency is maximized. From the simulation and
125009-7
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Li Yajun et al.
[6]
[7]
[8]
[9]
[10]
Fig. 16. Measured efficiency.
Table 2. Performance comparison summary of the chips.
Parameter
Ref. [22]
This work
Input voltage (V)
8–36
8–36
Output voltage (V)
1.18–12
1.18–12
Maximum output current (A)
3
3
Peak current limit (A)
4.5
4.8
Inductor L (H)
100
68
Capacitor CO (F)
220
220
On-resistance of MP (m/
90
90
Switching frequency (kHz)
80
120
Power efficiency (peak) @ VIN 91.5
95
D 12 V, VO D 5 V (%)
Power efficiency (peak) @ VIN 89.5
93.5
D 24 V, VO D 5 V (%)
Power efficiency (peak) @ VIN 88
91.5
D 36 V, VO D 5 V (%)
[11]
[12]
[13]
[14]
[15]
[16]
experimental results, the maximum variation of driving voltage in this design is only 1.38%, which is 8.45% of the conventional scheme. Meanwhile, high efficiency is achieved and
the proposed technique is suitable for high voltage buck, boost
and buck-boost regulators with heavy load.
[17]
[18]
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