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ESE534
Computer Organization
Day 6: September 21, 2016
Energy, Power, Reliability
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Today
• Energy tradeoffs
• Voltage limits and leakage
• Variations
• [more of the gory transistor equations…]
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Penn ESE534 Fall 2016 -- Mehta & DeHon
At Issue
• Many now argue energy will be the
ultimate scaling limit
– (not lithography, costs, …)
• Proliferation of portable and handheld
devices
– …battery size and life biggest issues
• Cooling, energy costs may dominate cost
of electronics
– Even server room applications
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Preclass 1
• 1GHz case
– Voltage?
– Energy per Operation?
– Power required for 2 processors?
• 2GHz case
– Voltage?
– Energy per Operation?
– Power required for 1 processor?
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Preclass 1 Lesson
• What does Preclass 1 result tell us?
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Energy and Delay
1
2
E  CV
2
tgd=Q/I=(CV)/I
Id,sat=(mCOX/2)(W/L)(Vgs-VTH
2
)
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Energy/Delay Tradeoff
• EV2
• tgd1/V
1
E  CV 2
2
tgd=(CV)/I
Id,sat (Vgs-VTH)2
• We can trade speed (latency) for energy
• E×(tgd)2 constant
Martin et al. Power-Aware Computing, Kluwer 2001
http://caltechcstr.library.caltech.edu/308/
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Area/Time Tradeoff
• Also have Area-Time tradeoffs
– HW2 spatial vs temporal multipliers
– See more next week
• Compensate slowdown with additional
parallelism
– For throughput problems
• …trade Area for Energy  Architectural Option
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Question
• By how much can we reduce energy?
• What limits us?
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Challenge: Power
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Origin of Power Challenge
• Limited capacity to remove heat
– ~100W/cm2 force air
– 1-10W/cm2 ambient
• Transistors per chip grow at Moore’s Law rate
= (1/F)2
• Energy/transistor must decrease at this rate
to keep constant power density
• P/tr  CV2f
• E/tr  CV2
– …but V scaling more slowly than F
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Penn ESE534 Fall 2016 -- Mehta & DeHon
ITRS Vdd Scaling:
More slowly than F
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Penn ESE534 Fall 2016 -- Mehta & DeHon
ITRS CV2 Scaling:
More slowly than (1/F)2
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Origin of Power Challenge
• Transistors per chip
grow at Moore’s
Law rate = (1/F)2
• Energy/transistor
must decrease at
this rate to keep
constant
• E/tr  CV2
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Penn ESE534 Fall 2016 -- Mehta & DeHon
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Intel Power Density
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Impact
Power Limits Integration
Density Limit
Constant Power Limit
45nm
32nm
22nm
16nm
11nm
Source: Carter/Intel
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Penn ESE534 Fall 2016 -- Mehta & DeHon
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Impact
• Power density is limiting scaling
– Can already place more transistors on a chip than
we can afford to turn on!
• Power is potential challenge/limiter for all
future chips.
– Only turn on small percentage of transistors?
– Operate those transistors as much slower
frequency?
– Find a way to drop Vdd?
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Penn ESE534 Fall 2016 -- Mehta & DeHon
How far can we reduce Vdd?
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Limits
• Ability to turn off the transistor
• Parameter Variations
• Noise (not covered today)
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Penn ESE534 Fall 2016 -- Mehta & DeHon
MOSFET Conduction
From: http://en.wikipedia.org/wiki/File:IvsV_mosfet.png
Penn ESE534 Fall 2016 -- Mehta & DeHon
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Transistor Conduction
gate
drain
src
channel
• Three regions
– Subthreshold (Vgs<VTH)
– Linear (Vgs>VTH) and (Vds < (Vgs-VTH))
– Saturation (Vgs>VTH) and (Vds > (Vgs-VTH))
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Saturation Region
• (Vgs>VTH)
• (Vds > (Vgs-VTH))
Ids,sat=(mCOX/2)(W/L)(Vgs-VTH
2
)
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Linear Region
• (Vgs>VTH)
• (Vds < (Vgs-VTH))
Ids,lin=(mCOX)(W/L)((Vgs-VTH)Vds-(Vds)2/2)
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Subthreshold Region
• (Vgs<VTH)
V

Isub  IVT 10
gs VTH
/ S
S  (ln( 10))kT / q
[Frank, IBM J. R&D v46n2/3p235]
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Penn ESE534 Fall 2016 -- Mehta & DeHon
IDS vs. VGS
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Penn ESE370 Fall2014 -- DeHon
Operating a Transistor
• Concerned about Ion and Ioff
• Ion drive (saturation) current for charging
– Determines speed: Tgd = CV/I
• Ioff leakage current
– Determines leakage power/energy:
• Pleak = V×Ileak
• Eleak = V×Ileak×Tcycle
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Leakage
• To avoid leakage want Ioff very small
• Switch V from Vdd to 0
• Vgs in off state is 0 (Vgs<VTH)
V

Isub  IVT 10
gs VTH
Ioff  IVT 10
/ S
VTH  / S 
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Leakage
Ioff  IVT 10
•
•
•
•
VTH  / S 
S90mV for single gate
S70mV for double gate
For lowest leakage, want S small, VTH large
4 orders of magnitude IVT/IoffVTH>280mV
Leakage limits VTH in turn limits Vdd 29
Penn ESE534 Fall 2016 -- Mehta & DeHon
How maximize Ion/Ioff ?
• Maximize Ion/Ioff – for given Vdd ? EswCV2
• Get to pick VTH
Id,sat=(mCOX/2)(W/L)(Vgs-VTH
2
)
Id,lin=(mCOX)(W/L)(Vgs-VTH)Vds-(Vds)2/2
V

Isub  IVT 10
gs VTH
Penn ESE534 Fall 2016 -- Mehta & DeHon
/ S
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IDS vs. VGS
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Penn ESE370 Fall2014 -- DeHon
Preclass 2
• E = Esw + Eleak
• Eleak = V×Ileak×Tcycle
• EswCV2
V

Isub  IVT 10
gs VTH
• Ichip-leak = Ndevices ×Itr-leak
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Penn ESE534 Fall 2016 -- Mehta & DeHon
/ S
Preclass 2
• Eleak(V) ?
• Tcycle(V)?
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Penn ESE534 Fall 2016 -- Mehta & DeHon
In Class
• Assign calculations
– SIMD – each student computes for a
different Voltage
• Collect results on board
• Group: Identify minimum energy point
and discuss
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Graph for In Class
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Impact
• Subthreshold slope prevents us from
scaling voltage down arbitrarily.
• Induces a minimum operating energy.
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Challenge: Variation
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Statistical
Dopant
Count and
Placement
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Penn ESE534 Fall 2016 -- Mehta & DeHon
[Bernstein et al, IBM JRD 2006]
Vth Variability @ 65nm
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Penn ESE534 Fall 2016 -- Mehta & DeHon
[Bernstein et al, IBM JRD 2006]
Variation
• Fewer dopants, atoms  increasing Variation
• How do we deal with variation?
% variation in VTH
(From ITRS prediction)
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Penn ESE534 Fall 2016 -- Mehta & DeHon
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Impact of Variation?
• Higher VTH?
– Not drive as strongly  slower
– Id,sat (Vgs-VTH)2
• Lower VTH?
– Not turn off as well  leaks more
Ioff  IVT 10
VTH  / S 
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Variation
• Margin for expected variation
• Must assume VTH can be any value in range
Ion,min=Ion(Vth,max)
Probability Distribution
Id,sat (Vgs-VTH)2
Vgs = Vdd
VTH
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Margining
• Must raise Vdd to increase drive strength
• Increase energy
Ion,min=Ion(Vth,max)
Probability Distribution
Id,sat (Vgs-VTH)2
Vgs = Vdd
VTH
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Variation
• Increasing variation forces higher voltages
– On top of our leakage limits
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Penn ESE534 Fall 2016 -- Mehta & DeHon
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• Margins growing due to
increasing variation
Probability Distribution
Variations
Old
New
Delay
• Margined value may be worse than older
technology?
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Penn ESE534 Fall 2016 -- Mehta & DeHon
End of Energy Scaling?
Black nominal
Grey with variation
[Bol et al., IEEE TR VLSI Sys 17(10):1508—1519]47
Penn ESE534 Fall 2016 -- Mehta & DeHon
Minimum Energy vs Technology
• Similar
experiment for
FPGA logic
6
5
4
3
Energy Increase
Energy Increase
2
• …and a hint at
how to mitigate
Energy Decrease
1
[Mehta PhD thesis 2012 (refined from FPGA 2012)]
Penn ESE534 Fall 2016 -- Mehta & DeHon
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Chips Growing
• Larger chips (billions of transistors) 
sample further out on distribution curve
From: http://en.wikipedia.org/wiki/File:Standard_deviation_diagram.svg
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Big Ideas
• Can trade time for energy
– … area for energy
• Variation and leakage limit voltage scaling
• Power major limiter going forward
– Can put more transistors on a chip than can switch
• Continued scaling demands
– Deal with noisier components
• High variation
• … other noise sources
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Penn ESE534 Fall 2016 -- Mehta & DeHon
Admin
• Homework 2 due Tonight
• Reading for Monday on web
• Homework 3 due next Wednesday
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Penn ESE534 Fall 2016 -- Mehta & DeHon