Download 512k x 8 bit low power cmos sram

NOVEMBER
2007
January 2007
AS6C8016
X 8 BITCMOS
LOW SRAM
POWER CMOS SRAM
512K X 16 BIT SUPER 512K
LOW POWER
FEATURES
GENERAL DESCRIPTION
Fast access time : 55ns
Low power consumption:
Operating current : 30mA (TYP.)
Standby current : 6µA (TYP.) LL-version
Single 2.7V ~ 5.5V power supply
All inputs and outputs TTL compatible
Fully static operation
Tri-state output
Data byte control : LB# (DQ0 ~ DQ7)
UB# (DQ8 ~ DQ15)
Data retention voltage : 1.5V (MIN.)
Lead free and green package available
Package : 44-pin 400 mil TSOP-II
48-ball 6mm x 8mm TFBGA
The AS6C8016 is a 8,388,608-bit low power
CMOS static random access memory organized as
524,288 words by 16 bits. It is fabricated using very
high performance, high reliability CMOS technology.
Its standby current is stable within the range of
operating temperature.
The AS6C8016 is well designed for low power
application, and particularly well suited for battery
back-up nonvolatile memory application.
The AS6C8016 operates from a single power
supply of 2.7V ~ 5.5V and all inputs and outputs are
fully TTL compatible
PRODUCT FAMILY
Product
Family
AS6C8016(I)
Operating
Temperature
-40 ~ 85℃
Vcc Range
2.7 ~ 5.5V
FUNCTIONAL BLOCK DIAGRAM
Speed
55ns
PIN DESCRIPTION
SYMBOL
A0 - A18
Vcc
Vss
A0-A18
DQ0-DQ7
Lower Byte
DQ8-DQ15
Upper Byte
CE#
WE#
OE#
LB#
UB#
Power Dissipation
Standby(ISB1,TYP.) Operating(Icc,TYP.)
6µA(LL)
30mA
DESCRIPTION
Address Inputs
DQ0 – DQ15 Data Inputs/Outputs
DECODER
I/O DATA
CIRCUIT
512Kx16
MEMORY ARRAY
CE#
Chip Enable Input
WE#
Write Enable Input
OE#
Output Enable Input
LB#
Lower Byte Control
UB#
Upper Byte Control
VCC
Power Supply
VSS
Ground
COLUMN I/O
CONTROL
CIRCUIT
NOVEMBER/2007, V 1.0
Alliance Memory Inc.
Page 1 of 12
NOVEMBER
2007
January 2007
AS6C8016
X 8 BIT
LOW
POWER CMOS SRAM
512K X 16 BIT SUPER 512K
LOW POWER
CMOS
SRAM
PIN CONFIGURATION
A4
1
44
A5
A3
2
43
A6
A2
3
42
A7
A1
4
41
OE#
5
40
UB#
6
39
LB#
DQ0
7
38
DQ15
DQ1
8
37
DQ14
DQ2
9
36
DQ13
DQ3
10
35
DQ12
Vcc
11
34
Vss
Vss
12
33
Vcc
DQ4
13
32
DQ11
DQ5
14
31
DQ10
DQ6
15
30
AS6C8016
A0
CE#
A
LB# OE#
A0
A1
B
DQ8 UB#
A3
A4
CE# DQ0
DQ9
C
DQ9 DQ10 A5
A6
DQ1 DQ2
D
Vss DQ11 A17
A7
DQ3 Vcc
E
Vcc DQ12 NC
A16 DQ4 Vss
F
DQ14 DQ13 A14
A15 DQ5 DQ6
DQ15 NC
A12
A13 WE# DQ7
A10
DQ7
16
29
DQ8
WE#
17
28
A8
A18
18
27
A9
A17
19
26
A10
A16
20
25
A11
G
A15
21
24
A12
H
A14
22
23
A13
A18
A8
A9
1
2
3
4
TFBGA
TSOP II
A2
NC
A11
NC
5
6
ABSOLUTE MAXIMUN RATINGS*
PARAMETER
Voltage on VCC relative to VSS
Voltage on any other pin relative to VSS
Operating Temperature
SYMBOL
VT1
VT2
TA
RATING
-0.5 to 6.5
-0.5 to VCC+0.5
-40 to 85(I grade)
UNIT
V
V
℃
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
TSTG
PD
IOUT
TSOLDER
-65 to 150
1
50
260
℃
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
NOVEMBER/2007, V 1.0
Alliance Memory Inc.
Page 2 of 12
NOVEMBER
2007
January 2007
AS6C8016
X 8 BITCMOS
LOW SRAM
POWER CMOS SRAM
512K X 16 BIT SUPER 512K
LOW POWER
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
CE#
OE#
H
X
L
L
L
L
L
L
L
L
X
X
H
H
L
L
L
X
X
X
H = VIH, L = VIL, X = Don't care.
WE# LB#
X
X
H
H
H
H
H
L
L
L
UB#
X
H
L
X
L
H
L
L
H
L
X
H
X
L
H
L
L
H
L
L
I/O OPERATION
DQ8-DQ15
DQ0-DQ7
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
DOUT
High – Z
DOUT
DOUT
DOUT
High – Z
DIN
High – Z
DIN
DIN
DIN
SU P PLY CURRENT
ISB1
ICC,ICC1
ICC,ICC1
ICC,ICC1
DC ELECTRICAL CHARACTERISTICS
MIN.
SYMBOL
TEST CONDITION
PARAMETER
Supply Voltage
VCC
2.7
*1
Input High Voltage
VIH
2.4
*2
Input Low Voltage
VIL
- 0.2
≦
Input Leakage Current
ILI
VCC ≦ VIN
VSS
-1
Output Leakage
VCC ≦ VOUT ≦ VSS
-1
ILO
Output Disabled
Current
Output High Voltage
VOH IOH = -1mA
2.4
Output Low Voltage
VOL
IOL = 2mA
Cycle time = Min.
CE# = VIL,
ICC
- 55
II/O = 0mA
Average Operating
Other pins at VIL or VIH
Power supply Current
Cycle time = 1µs
ICC1 CE#≦0.2V, II/O = 0mA
Other pins at 0.2V or VCC-0.2V
Standby Power
Supply Current
ISB1
CE# ≦ VCC-0.2V
Other pins at 0.2V or VCC-0.2V
TYP.
3.0
-
*4
MAX.
UNIT
5.5
V
VCC+0.3
V
0.6
V
1
µA
-
1
µA
2.7
-
0.4
V
V
30
60
mA
4
12
-
6
mA
50
µA
Notes:
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃
CAPACITANCE
(T A = 25 ℃, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
CIN
CI/O
MIN.
-
MAX
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
NOVEMBER/2007, V 1.0
Alliance Memory Inc.
Page 3 of 12
NOVEMBER
2007
January 2007
AS6C8016
X 8 BIT
LOW
POWER CMOS SRAM
512K X 16 BIT SUPER 512K
LOW POWER
CMOS
SRAM
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to VCC - 0.2V
3ns
1.5V
CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
LB#, UB# Access Time
LB#, UB# to High-Z Output
LB#, UB# to Low-Z Output
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
LB#, UB# Valid to End of Write
SYM.
AS6C8016
UNIT
AS6C8016
UNIT
tRC
tAA
tACE
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
tBA
tBHZ
tBLZ
SYM.
tWC
tAW
tCW
tAS
tWP
tWR
tDW
tDH
tOW
tWHZ
tBW
*These parameters are guaranteed by device characterization, but not production tested.
NOVEMBER/2007, V 1.0
Alliance Memory Inc.
Page 4 of 12
NOVEMBER
2007
January 2007
AS6C8016
X 8 BIT
LOW
POWER CMOS SRAM
512K X 16 BIT SUPER 512K
LOW POWER
CMOS
SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
Address
tAA
Dout
tOH
Previous Data Valid
Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
tRC
Address
tAA
CE#
tACE
LB#,UB#
tBA
OE#
tOE
tOH
tOHZ
tBHZ
tCHZ
tOLZ
tBLZ
tCLZ
Dout
High-Z
Data Valid
High-Z
Notes :
1.WE#is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low.
3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter.
4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ.
NOVEMBER/2007, V 1.0
Alliance Memory Inc.
Page 5 of 12
NOVEMBER
2007
January 2007
AS6C8016
X 8 BIT
LOW
POWER CMOS SRAM
512K X 16 BIT SUPER 512K
LOW POWER
CMOS
SRAM
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC
Address
tAW
CE#
tCW
tBW
LB#,UB#
tAS
tWP
tWR
WE#
tWHZ
Dout
T OW
High-Z
(4)
(4)
tDW
tDH
Data Valid
Din
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)
tWC
Address
tAW
CE#
tAS
tWR
tCW
tBW
LB#,UB#
tWP
WE#
tWHZ
Dout
(4)
High-Z
tDW
Din
NOVEMBER/2007, V 1.0
tDH
Data Valid
Alliance Memory Inc.
Page 6 of 12
NOVEMBER
2007
January 2007
AS6C8016
X 8 BIT
LOW
POWER CMOS SRAM
512K X 16 BIT SUPER 512K
LOW POWER
CMOS
SRAM
WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6)
tWC
Address
tAW
tWR
CE#
tCW
tBW
tAS
LB#,UB#
tWP
WE#
tWHZ
Dout
(4)
High-Z
tDW
Din
tDH
Data Valid
Notes :
1.WE#,CE#, LB#, UB# must be high during all address transitions.
2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance
state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
NOVEMBER/2007, V 1.0
Alliance Memory Inc.
Page 7 of 12
NOVEMBER
2007
January 2007
AS6C8016
X 8 BITCMOS
LOW SRAM
POWER CMOS SRAM
512K X 16 BIT SUPER 512K
LOW POWER
DATA RETENTION CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITION
_ VCC - 0.2V
VCC for Data Retention
VDR
CE# >
VCC = 1.5V
_ VCC-0.2V
Data Retention Current
IDR
CE# >
Other pins at 0.2V or VCC-0.2V
See Data Retention
Chip Disable to Data
tCDR
Waveforms (below)
Retention Time
Recovery Time
tR
tRC* = Read Cycle Time
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1)
MIN.
1.5
TYP.
-
MAX.
5.5
UNIT
V
-
4
50
0
-
-
ns
tRC*
-
-
ns
µA
(CE# controlled)
_ 1.5V
VDR >
Vcc
Vcc(min.)
Vcc(min.)
tCDR
CE#
VIH
Low Vcc Data Retention Waveform (2)
tR
_ Vcc-0.2V
CE# >
VIH
(LB#, UB# controlled)
_ 1.5V
VDR >
Vcc
Vcc(min.)
Vcc(min.)
tCDR
LB#,UB#
VIH
NOVEMBER/2007, V 1.0
tR
_ Vcc-0.2V
LB#,UB# >
Alliance Memory Inc.
VIH
Page 8 of 12
NOVEMBER
2007
January 2007
A S 6 C 8 0 1 6
X 8 BIT
LOW
POWER CMOS SRAM
512K X 16 BIT SUPER 512K
LOW POWER
CMOS
SRAM
PACKAGE OUTLINE DIMENSION
θ
Ⅱ Package Outline Dimension
44-pin 400mil TSOP-Ⅱ
SYMBOLS
A
A1
A2
b
c
D
E
E1
e
L
ZD
y
Θ
DIMENSIONS IN MILLMETERS
MIN.
NOM.
MAX.
1.20
0.05
0.10
0.15
0.95
1.00
1.05
0.30
0.45
0.12
0.21
18.212
18.415
18.618
11.506
11.760
12.014
9.957
10.160
10.363
0.800
0.40
0.50
0.60
0.805
0.076
o
o
o
3
6
0
NOVEMBER/2007, V 1.0
DIMENSIONS IN MILS
MIN.
NOM.
MAX.
47.2
2.0
3.9
5.9
37.4
39.4
41.3
11.8
17.7
4.7
8.3
717
725
733
453
463
473
392
400
408
31.5
15.7
19.7
23.6
31.7
3
o
o
o
0
3
6
Alliance Memory Inc.
Page 9 of 12
NOVEMBER
2007
January 2007
AS6C8016
X 8 BIT
LOW
POWER CMOS SRAM
512K X 16 BIT SUPER 512K
LOW POWER
CMOS
SRAM
48-ball 6mm × 8mm TFBGA Package Outline Dimension
NOVEMBER/2007, V 1.0
Alliance Memory Inc.
Page 10 of 12
AS6C8016
NOVEMBER
2007
January 2007
X 8 BICMOS
T LOW
POWER
512K X 16 BIT SUPER 512K
LOW POWER
SRAM
CMOS SRAM
ORDERING INFORMATION
Alliance
Organization
VCC
Range
Package
Operating Temp
Speed
ns
AS6C8016 -55ZIN
512K x 16
2.7 - 5.5V
44pin TSOP II
Industrial ~ -40 C - 85 C
55
AS6C8016 -55BIN
512K x 16
2.7 - 5.5V
48ball TBGA
Industrial ~ -40 C - 85 C
55
PART NUMBERING SYSTEM
AS6C
8016
-55
Device Number
low power
SRAM prefix
80 = 8M
16 = x16
NOVEMBER/2007, V 1.0
Access
Time
X
X
Package Option
Temperature Range
Z - 44pin TSOP
I = Industrial
B = 48ball TFBGA
(-40 to + 85 C)
Alliance Memory Inc.
N
N = Lead Free
RoHS
compliant part
Page 11 of 12
NOVEMBER
2007
January 2007
AS6C8016
512K
X 8CMOS
BIT LOW
512K X 16 BIT LOW
POWER
SRAMPOWER CMOS SRAM
®
Alliance Memory, Inc
511 Taylor Way,
San Carlos, CA 94070, USA
Phone: 650-610-6800
Fax: 650-620-9211
Copyright © Alliance Memory
All Rights Reserved
www.alliancememory.com
© Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks ofAlliance.
All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to thisdocument and its
products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The datacontained herein represents
Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at anytime, without notice. If the product
described herein is under development, significant changes to these specifications are possible. The information inthis product data sheet is intended to be
general descriptive information for potential customers and users, and is not intended to operate as, or provide,any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of anyproduct described herein, and disclaims any
express or implied warranties related to the sale and/or use of Alliance products including liability orwarranties related to fitness for a particular purpose,
merchantability, or infringement of any intellectual property rights, except as express agreed to inAlliance's Terms and Conditions of Sale (which are available
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third parties. Alliance does not authorize its products for use as critical components inlife-supporting systems where a malfunction or failure may reasonably be
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all risk of such use and agrees to indemnify Alliance against allclaims arising from such use.
NOVEMBER/2007, V 1.0
Alliance Memory Inc.
Page 12 of 12
Mouser Electronics
Authorized Distributor
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AS6C8016-55BINTR AS6C8016-55ZINTR AS6C8016-55ZIN