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Clocked and Sense Amplifier-based Logic Families C.K. Ken Yang UCLA [email protected] Courtesy of MAH,JR EE 215B 1 Overview • • Reading – Rabaey 7.5.2 (NORA) – W&H 6.2.1-5 Overview – This set of notes cover in greater detail Static and Dynamic Logic Families. Since Static CMOS and Pseudo-NMOS were previously discussed, we focus the static logic section on various pass-transistor logic families. The dynamic families begin with a review of Domino and an extensive discussion on the noise issues in dynamic circuits and how it is resolved. Several variants of Domino are discussed. EE 215B 2 Dynamic/Clocked Logic Families Outline • Non-monotonic dynamic circuits • Sense-amplifier-based logic • Other dynamic logic families EE 215B 3 Dual-Rail Problem • • Generating both output and complement of output can be costly. The basic dynamic gate is great for a NOR. – But the dual-rail version is just as slow as a NAND. EE 215B 4 Clock Delaying • • • Domino requires the input to be stable during evaluate. What if… – Input to domino settles before evaluating. – Even if the input is from another domino gate. – Just use an appropriately delayed clock! Note that there is a “race” during pre-charge – Not a functional problem but wastes power – May limit the maximum delay permitted. EE 215B 5 Clocked-Delayed Domino • Delay the clock for each stage so that the inputs are “levelized” before the stage EVALUATES. – Must use the longest delay. – Or match each element independently. EE 215B 6 Delaying the Clock • • Many ways to delay the clock Goal is to track the delay of the circuit. – Under environmental variations. – Use dummy logic gates that look like the circuit. EE 215B 7 Race-based Logic • • High fan-in AND gate. – Build a NOR (OR + Inverter) During EVAL (=HIGH) – W needs to stay HIGH when X falls – Since X is pre-charged HIGH, W must droop some. • So X must fall before W falls (the race) – Used in the Itanium (Naffziger02) EE 215B 8 Complementary Signal Generator • • Latched Domino (Pretorius86) – Use cross-coupled NMOS to help discharge X faster. – Improves the race CSG (Intel – Vangal02) – Use cross-coupled PMOS to keep W = HIGH in the case of the race. EE 215B 9 Dynamic/Clocked Logic Families Outline • Non-monotonic dynamic circuits • Sense-amplifier-based logic • Other dynamic logic families EE 215B 10 DCVS Derivatives – Logic Using Cross-coupled Inverters • • The combination of a clocked gate and DCVS is the basis for many logic family variants Use the idea of a full keeper (like SRPL) to restore the signal. – A small V on the differential nodes is created by the DCVS tree. – The cross-coupled inverters amplify the difference. +V -V f f’ clk EE 215B 11 Sample-Set Differential Logic • • • • • SSDL (Grotjohn86) When =HIGH – The pull down tree will pull F’ or F’_b LOW (by a small amount since the PMOS is ON.) When =LOW – The small voltage difference between F’, and F’_b is amplified by the cross coupled inverters (enabled when =LOW) Draws static power when sampling (=HIGH) Helpful to have a keeper to restore the F/F’ because both nodes are lowered during EVAL EE 215B F F F’ F’ Pull-down Tree 12 Enable/Disable CMOS Differential Logic • ECDL (Lu88) – eliminates the static current during sampling – Flipped the clocking • =H – reset by discharging both outputs • =L – eval by pulling up 1 side (both initially) – Use a delayed clock to enable the next logic stage. N+1 EE 215B 13 Latched CMOS Differential Logic • • LCDL (Wu91) – Similar to SSDL – Add latches at the output X, X’ Use the same clock to fire the cross-coupling AND the DCVS pull-down! – Risky because the V developed at X, and X’ may be initially incorrect! – May amplify offset or noise. EE 215B 14 Differential Current Switch Logic • • • • DCSL (Somesekhar96) – Like DSL in that pull-down network swing is reduced (less power) DCSL1 – pre-charge-HIGH (like SSDL, LCDL) DCSL2,3 – pre-charge-LOW (like ECDL) – DCSL3 equalizes the output nodes instead of discharging during the pre-charge. Like LCDL, may result in amplifying noise. EE 215B 15 Design Issues for Sense-Amplifying Logic • The timing of the clock is important. – Input arrives a setup-time before the clock. – Cascading the logic is tricky because it is safe only when each stage’s clock is delayed from the previous stage. • Similar to N-phase skew-tolerant domino. EE 215B 16 Dynamic CML • Choose small voltage swing (20% of VDD) • Size C1 so that the dynamic charge is sufficient to discharge output, CL 17 Cascading DyCML Gates SE = clock to next state EOE = end of evaluation Interfacing with SCMOS IN=DyCML output Clock delay mechanism Self-timing scheme 18 Performance of DyCML EE 215B 19 Dynamic/Clocked Logic Families Outline • Sense-amplifier-based logic • Non-monotonic dynamic circuits • Other dynamic logic families EE 215B 20 NORA (Zipper) Domino clk clk Replace static gate with P-Block of predischarged loigc N-Block • • • P-Block NORA (NO-RAce) or Zipper Domino – fast b/c all dynamic Extremely noise sensitive: trips if output drops by a threshold – This includes power supply bounce between gates – Problem is that you have a noisy output connected to a noise sensitive input Tried on DEC J11 and AT&T’s “CRISP” microprocessor, but both chips failed on first silicon EE 215B 21 NORA Adder C1 C0 A0 B0 C0 A0 A0 B0 C0 • B0 • A0 Odd stages are Active-LOW signals Footers are left out. S0 ’ B0 S1 B1 A1 A1 B1 C1 C2 ’ C1 B1 A1 B1 A1 EE 215B 22 Clocked Skewed CMOS • • Alternate the precharge like NORA Embed in static CMOS (improve robustness) – Size static CMOS to favor an edge (skewed gates) Pre-charge HIGH Pre-charge LOW EE 215B 23 Output Prediction Logic • • • • OPL (McMurchie00) – CMOS is inverting logic – If pre-charge all nodes HIGH, only every other node will fall. Implementation – Start with a Static CMOS gate – NAND it with a clock When = LOW – Pre-charge HIGH When = HIGH – Inputs are from the same type of logic so inputs are initially HIGH. – During EVAL, only outputs that evaluates LOW will fall. • In reality, all outputs falls first to VDD/2 and PMOS pulls half of them back up. EE 215B 24 Output Prediction Logic Timing • • • • The trick is with the timing If all clocks are the same phase (a) – Clock arrives before inputs settle – A lot of glitching occurs at later stages as preceding stages evaluate. If subsequent stages are clocked by delayed clocks (c) – We get the desired waveforms, except the delay of each gate is essentially the delay of the clock. With optimized delay between each stage. – Outputs discharge to VDD/2 as clocks arrive just before the data. – The output transitions to the final value when data arrives. EE 215B 25 Output Prediction Logic Discussion • • • Inventors found this to be 5x faster than SCMOS and 30% more power. – Proper clock delay is needed. Performance can be sensitive to clock delay. – Too long, limited by clock delay – Too short, initial discharge drops the output too far and the recovery is too slow. Delay is also sensitive to PN ratio, P. – Small P evaluates (to LOW) quickly but recovers slowly if over-discharged. – Large P evaluates slowly but recovers from glitches quickly. EE 215B 26 Summary • • • Domino logic can be improved by – Delaying the clock with logic delay so that data is stable when evaluation starts – Eliminate monotonicity with race-based logic (precharge two consecutive nodes) More complex dynamic structures can be build that are more sensitive to small voltage differences. – Sense-amplifier based logic, or clocked CML – Requires clock delay to setup in the inputs before evaluation The initial value to precharge the signals can also improve performance. – Near Vthlogic to essentially eliminate the V for reaching the threshold – But a tradeoff with power. EE 215B 27