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VLSI Algorithm &
Computing Structures
Chapter 1. Introduction to DSP Systems
Younglok Kim
Dept. of Electrical Engineering
Sogang University
Spring 2007
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What will be covered in this course?
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DSP architectures & structures for high
performance VLSI design
Methodologies needed to design custom or semicustom VLSI circuits
NOT actual VLSI circuit or layout design
Focus on design of efficient architectures for
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Less area for smaller chip size
Less power consumption for longer battery lifetime
Higher speed for real time processing
Lower round-off noise
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DSP Applications
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Video compression
Digital set-top box
Cable modems
Portable video systems/computers
Digital audio/radio
Wireless communication
Digital still camera
Speech processing
GPS (global positioning systems)
Radar imaging
Acoustic beamformer
Biomedical signal processing
Etc
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DSP Architecture Examples
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For a speech applications,
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Low sampling rate
Low speed requirement
Prefer time-multiplexed architecture
For a video applications,
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10~100 giga operations per second
One-to-one mapping of algorithm operations and
processors
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What to do for this class?
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Understanding the topics covered in the
classroom
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Read book, papers or other material if needed.
Solve the problems at the end of each chapter.
Verify the DSP algorithm
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MatLab/C simulations
DSP
HDL
etc
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Class Materials
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Main Textbook
VLSI Digital Signal Processing Systems, Keshab K. Parhi,
John Wiley & Sons, Inc. 1999
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Lecture notes
Papers and Materials will be recommended in the
class
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Organization of Textbook
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Part I: High-level architectural transformations
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Part II: High-level algorithm transformations
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Part III: VLSI architecture of arithmetic
operations
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High-level architectural transformations
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Iteration bound (ch.2)
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Pipelining and Parallel Processing (ch.3)
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Retiming techniques (ch4)
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Unfolding (ch.5)
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Folding (ch.6)
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Systolic array design methodology (ch.7)
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High-level algorithm transformations
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Fast Convolution (ch.8)
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Strength reduction (ch.9)
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Look ahead and Relaxed look ahead (ch.10)
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Scaling and round-off noise (ch.11)
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Digital Lattice filter structures (ch.12)
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VLSI architecture of arithmetic operations
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Addition, multiplication and digital filters (ch.13)
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Redundant arithmetic (ch.14)
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Numerical strength reduction (ch.15)
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Synchronous and Asynchronous pipelines (ch.16)
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Low-power design (ch.17)
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Architectures for programmable digital signal
processors (ch.18)
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Chapter 1
Introduction to DSP Systems
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What is Digital Signal?
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A sequence of numbers having finite precision
Sampler
Analog
signal
Quantizer
Discrete-Time
signal
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Coder
Binary
digital
signal
Quantized signal
Discrete-time
Discrete-valued signal
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Performance Measurements of Digital Design
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Amount of hardware circuitry and resources
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Execution speed
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Space or area
Depends on both throughput and clock rate
Amount of power dissipation
Finite word length performance for fixed-point
DSP systems
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Quantization error or round-off noise
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Features of Digital Signal Processing
over General Computations
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Real time throughput requirement
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Throughput needs to meet sample rate requirement
Data driven property
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Enable the use of asynchronous systems
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Overview of Typical DSP algorithms
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Convolution
Correlation
Digital Filters
Adaptive Filters
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LMS adaptive filters
Stochastic-Gradient adaptive lattice filter
Motion Estimation
Discrete Cosine Transform (DCT)
Vector Quantization
Viterbi Algorithm and Dynamic Programming
Decimator and Expander
Wavelets and Filter Banks
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Some Definitions For DSP Algorithms
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Non-terminating programs
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Iteration
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Execution of all the computations in the algorithm
once
Iteration period
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Execute repetitively
Execution time of one iteration
Iteration rate
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Reciprocal of the iteration period
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Some Definitions For DSP Systems
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Sampling rate
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Path
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Proportional to the computation time
Critical path for combinational logic circuit
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Number of samples processed per second
Longest path between inputs and outputs
Critical path for sequential circuits
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Longest path between any two storage (delay)
elements
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Some Definitions For DSP Systems …
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Critical path computation time determines
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Minimum feasible clock period of DSP systems
Latency
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Difference between the time an output generated and
the time at which its corresponding input was received
by the system
Latency representations
 Absolute time units, or the number of gate delays,
for combinational logic circuit systems.
 Number of clock cycle for the sequential systems.
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3-Tap FIR Filter Example
y(n)  b0 x(n)  b1 x(n  1)  b2 x(n  2)
for
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Each iteration generates one output sample with
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n 1 
One input signal
3 multiplication operations (in parallel or serial)
2 addition operations
Latency dependent on the architectures
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Various Representations of DSP Systems
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DSP Algorithm Descriptions
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Behavioral Descriptions
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Graphical Representations
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DSP algorithm descriptions
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Mathematical formulations
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Specify functionality of DSP algorithm
Does not specify the order & structure of the internal
operations
Behavioral description languages or graphical
representations for architectural design
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Behavioral Descriptions
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Applicative languages
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Prescriptive languages
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A set of equations
Silage language
Specify the order of the assignment statements
Pascal, C or Fortran
Descriptive languages
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Represents the structure of DSP system
Verilog HDL or VHDL
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Graphical Representations
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Efficient for investigating and analyzing data flow
properties
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Efficient for exploiting the inherent parallelism
among different subtasks
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Easy mapping DSP algorithm descriptions to
hardware structural implementations
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Provide technology-independent architecture
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Various graphical representations
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Block Diagram
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Signal Flow Graph
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Data Flow Graph
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Dependence Graph
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Block Diagram
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Captures the exact functionality of a system
Consist of
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Functional block
Directed edges
 Represents data flow from its input block to output
block
 Contains non-negative delay element
Various block diagrams can be derived for the
same system with different realizations of the
same functionality
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Block Diagram of 3-Tap FIR Filter
y(n)  b0 x(n)  b1 x(n  1)  b2 x(n  2)
x(n)
D
Unit Delay
D
x(n)
b0
b1
D
x(n-1)
b2
y(n)
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Data-broadcast FIR filter
x(n)
b2
b1
D
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b0
D
y(n)
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Signal Flow Graph
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Node
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Directed edge
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Computations of tasks, ex: multipliers or adders
Source node: node with no entering node
Sink node: node with only entering node
Denotes the linear transformation from the signal at
originating node to the signal at terminating node
Cannot be used to describe multi-rate DSP
systems
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SFG of 3-Tap FIR Filter
y(n)  b0 x(n)  b1 x(n  1)  b2 x(n  2)
z-1
x(n)
source
node
b0
z-1
b1
b2
y(n)
sink node
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Transposition of SFG
z-1
z-1
y(n)
b0
b1
b2
x(n)
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SFG reversal (transposition) is only applicable to
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Linear networks
Single input single output (SISO) systems
Multi-input multi-output (MIMO) systems described by
symmetric transformation matrices
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Data-flow graphs (DFG)
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Generally used for high-level synthesis to derive
concurrent implementations of DSP applications
onto parallel hardware
Node
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Computation or Function
Directed edge
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Data path, communication between nodes
Contains non-negative number of delays
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BD & DFG Of Recursive Algorithm
y (n)  ay (n  1)  x(n)
x(n)
y(n)
D
a
1
(2)
D
A
1
1
B
1
A: addition
B: multiplication
(n): execution time in
terms of normalized time
unit (u.t.; units of time)
(4)
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Data-Driven Property of DFG
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Precedence constraint
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Intra-precedence constraint
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The edge has zero delay
Inter-precedence constraint
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Node fires whenever all the input data are available
A node with multiple input edges can only fire after all
its precedent nodes have fired
The edge has one or more delays
Major concerns
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Subtask scheduling
Resource allocation
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Synchronous DFG (SDFG)
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The number of data samples produced or
consumed by each node in each execution is
specified a priori
Single-rate SDFG example
1
(2)
D
A
1
1
B
1
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(4)
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SDFG of multi-rate DFGs
A0
B0
A1
A2
C0
Multi-rate
Non-Synchronous DFG
B1
C1
A3
B2
A4
Multi-rate DFG
1
A
3
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B
2
3
C
2
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Processing Rate of Multi-Rate SDFG
1
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A
3
5
B
2
3
C
2
Frequency of each node
= number of invocations of each node per iteration
A, B, C are operated at different frequencies
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A processes fA input samples per time unit
Produce 3fA output samples per time unit
3 f A  5 fB
fB  3 f A / 5
fC  2 f B / 3  2 f A / 5
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Dependence Graph (DG)
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Shows the dependence of the computations
Used for systolic array design
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Node
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Computation
Edge
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Precedence constraint among nodes
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2D DG OF FIR Filter
0
0
0
0
b2
0
Processing Element (PE)
b1
y
0
b0
x'
b
y0
x0
y1
x1
y2
x2
b'
b'=b
x'=x
y'=y+bx
y3
x3
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x
y'
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Differences between DFG & DG
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DFG
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Shows only one iteration
Contains delay elements
Iterations are executed repetitively
DG
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Shows all iterations
No delay elements
A node is NEVER reused
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