Download Bit-Line Biasing Technique for Phase-Change Memories

Bit-Line Biasing Technique
for Phase-Change Memories
F. Bedeschi1, C. Boffino2,3, E. Bonizzoni2,3, O. Khouri4, C. Resta1,3, and G. Torelli2
1
STMicroelectronics, Memory Products Group R&D, via Olivetti, 2 - 20041 Agrate Brianza, Italy
2
Department of Electronics, University of Pavia, via Ferrata, 1 - 27100 Pavia, Italy
3
Studio di Microelettronica, STMicroelectronics, via Ferrata, 1 - 27100 Pavia, Italy
4
STMicroelectronics, Memory Products Group, via Olivetti, 2 - 20041 Agrate Brianza, Italy
Abstract - This paper presents a bit-line biasing
technique that ensures read and write voltages to be fed
to the storage element with adequate accuracy, high
rejection of disturbs from the column decoder supply
line, and protection against spurious program
operations in read mode. Fast bit-line precharge and
sensing are also achieved. The presented technique has
been developed for phase-change memories, however, it
is also suitable for use in other non-volatile storage
devices such as Flash memories. Experimental results
on read and program operations demonstrated the
effectiveness of the approach.
I. INTRODUCTION
Today high-performance portable equipments demand
for non-volatile memories with higher and higher read/write
speed and endurance. Phase-Change Memory (PCM) [1],
[2] is a very promising technology to meet these
requirements. In fact, PCMs ensure fast read/write
operations as compared to currently dominant Flash
memories, together with high endurance, process
simplicity, and excellent compatibility with standard
CMOS fabrication process. A further key advantage with
respect to Flash memories is very fine write granularity
with no need for block erase.
In PCMs, also referred to as Ovonic Unified Memories
(OUMs), the storage device consists of a thin film of
chalcogenide alloy (in our case, Ge2Sb2Te5, GST) [3]. This
material can reversibly change between an amorphous (high
impedance, RESET state) and a polycrystalline (low
impedance, SET state) phase when thermally stimulated,
thus allowing data storage. The phase conversion of any
storage element is obtained by appropriately heating (by
means of electrical pulses applied to a suitable heater
element) and then cooling a small, and thermally isolated,
portion of the material. Once the chalcogenide material
melts, it completely loses its crystalline structure. When
rapidly cooled, the chalcogenide material is locked into its
amorphous state (to this end, the cooling operation rate has
to be faster than the crystal growth rate). To switch the
memory element back to its crystalline state, the
chalcogenide material is heated to a temperature between
its glass transition temperature and its melting point
temperature. In this way, nucleation and micro-crystal
growth occur in several ns, thus leading to a
(poly)crystalline state and, hence, to a percolation path for
the conduction.
From the above description, it is apparent that the
storage element can be modelled as programmable resistor
(high resistance = logic 0; low resistance = logic 1). In
order to reduce reprogramming time, SET and RESET
operations are performed without resorting to
program&verify and erase&verify techniques [4], [5]. Very
accurate electrical pulses have therefore to be applied to the
addressed bit-lines and, hence, to the selected cells.
Reading a cell basically consists in measuring the
resistance of the addressed storage device. In read
operations, a suitable sensing voltage is forced across the
storage element of the addressed cell, and the stored data is
detected by sensing the current flowing through the cell [6].
In practice, the cell current is compared to a reference
current provided by an identical cell programmed to a
suitable resistance value. To obtain the best sense accuracy,
the reference cell is located within the memory array and is
identically biased. This choice minimizes boundary effects
and allows thermal tracking between the reference and the
array cells. During read operation, the value of the sensing
voltage has to be adequately low, accurate, and stable so as
not to perturb the state of the cell and to prevent the risk of
any spurious SET pulse.
In order to provide the read and program voltages to the
storage element with the required accuracy and stability, an
adequate bit-line biasing technique is needed. In this paper,
a bit-line biasing technique designed for PCMs is presented.
A cascode scheme allows the desired read and write
voltages with the required features to be fed to the storage
element. Furthermore, the proposed approach ensures high
rejection to disturbs. The proposed bit-line biasing
technique was integrated in a 4-Mb (2048 rows 2048
columns) MOSFET-selected PCM test-chip fabricated in
single-poly, single-well, double-metal, p-substrate 3-V
0.18-m CMOS technology, and experimentally evaluated.
by inaccuracies due to technological process spreads which
impact over the on-resistance of switches and the variations
of the current drawn by the addressed memory cell.
Moreover, the higher the number of selection switches in
the column selector, the less accurate and controlled the bitline voltage, during both programming and reading.
Furthermore, in the column decoding architecture shown in
Fig. 1, disturbs present on nodes A, B, and C is transmitted
to the bit-line, thus adversely affecting the operation being
carried out. As a result, program and sense accuracy, as
well as program time, are adversely affected, with ensuing
degradation of yield, performance, and reliability of the
device.
II. CIRCUIT DESCRIPTION
To be more specific, here and in the following, we refer
to the case of PCMs, although all concepts are also valid for
other non-volatile storage devices such as Flash memories.
Figure 1 shows a schematic diagram of a conventional bitline biasing technique applied to a PCM device. In
particular, a detail of a bit-line including two memory
elements together with the associated selection transistors is
depicted. In this figure, MOS selection devices are
assumed, although substrate bipolar transistor can also be
used [7]. The column selector for each bit-line is
implemented by three PMOS transistors, M 1, M2, and M 3
(alternatively, NMOS transistors can be employed). The
number of selection transistors depends upon the size of the
memory array and the hierarchical organization of the
column decoder. The gates of M1, M 2, and M3 are fed by
column selection signals K L, K M, and K N, respectively,
which are generated by a column decoder (not shown).
In a PCM device, high voltages are required to perform
SET and RESET operations. In a single-supply chip, these
voltages are produced by using on-chip voltage multipliers,
which are generally based on charge pump techniques [8].
The charge pump feeds a voltage regulator, which, in turn,
provides the supply voltage to the program load circuit. The
latter consists essentially of a switch that connects the
column selector to the voltage regulator output only during
program operations. During reading, the program load
disconnects the charge pump and the voltage regulator from
the column selector, and the latter is connected to the input
of the read circuit. The read circuit compares the current
flowing through the addressed memory cell with the current
flowing through a reference memory cell (not shown),
thereby detecting the stored contents. From Fig. 1, it is
apparent that the voltage at node D (bit-line voltage) is
equal to the voltage at node A (column decoder supply line)
minus the voltage drop across the selection switches M1,
M2, and M 3. Consequently, the bit-line voltage is affected
Fig. 1 – Schematic diagram of a conventional bit-line biasing
technique applied to a PCM device.
The above drawbacks are overcome by using the bit-line
biasing scheme illustrated in Fig. 2. The Operation Control
(OC) block provides the regulated read and program
voltages, V READ and VPROG, respectively, to the gate of
natural transistor Y O (which operates in the saturation
region). In this way, the bit-line voltage (node D) turns out
to be:
VD = VG,YO (Vth + Vov )
(1)
where VG,YO, V th, and Vov are the gate biasing voltage, the
threshold voltage (including the body effect contribution),
and the overdrive voltage of transistor YO, respectively.
By appropriately driving the gate of transistor Y O, it is
possible to accurately bias the bit-line during both read and
program operations. The obtained bit-line voltage turns out
to be independent of the voltage drops across the selection
switches M1, M2, and M 3. The accuracy and the stability of
the bit-line voltage depend almost exclusively upon the
accuracy and the stability of the voltage supplied to the gate
of transistor YO (V READ or V PROG). It should be pointed out
that lines VREAD and VPROG are not required to supply any
DC current, and can thus be easier designed so as to ensure
the required performances. Furthermore, thanks to the
cascode configuration, adequate rejection of any ripple or
fluctuation on node A, B, and C is ensured. Consequently,
the constraints on the stability and precision of the column
decoder supply (node A) are less stringent as compared to
the case of the scheme shown in Fig. 1, which leads to
relaxed design specifications for the charge pump and the
voltage regulator. In some applications, the latter circuit can
be eliminated, with ensuing advantages in terms of silicon
area and power consumption. During reading, the proposed
bit-line biasing technique provides self-protection against
spurious SET pulses thanks to the high rejection to disturbs,
while still ensuring adequate bit-line precharge and sensing
speed.
Fig. 2 – Schematic diagram illustrating the proposed
bit-line biasing technique
III. EXPERIMENTAL RESULTS
The proposed bit-line biasing scheme was integrated in a
4-Mb (2048 rows 2048 columns) MOSFET-selected
PCM test-chip, fabricated in single-poly, single-well,
double-metal, p-substrate 3-V 0.18-m CMOS technology.
Table 1 summarizes the read and write currents together
with bit-line and word-line voltages for selected (Sel) and
unselected (No Sel) cells. Figure 3 shows a chip
microphotograph.
The nominal power supply Vdd and the column decoder
supply VA were set to 1.8 V and 3.3 V, respectively, so as to
allow correct operations during both reading and
programming. In order to evaluate the effectiveness of the
proposed bit-line biasing approach, a triangular signal,
provided by an external waveform generator, has been
superimposed to VA, thus emulating the ripple of a charge
pump or a possible circuit disturb. Correct operation has
been demonstrated during both reading and programming
when applying a disturb signal with a peak-to-peak
amplitude of 220 mV and a period of 20 ns.
Table 1 – Voltages and currents for selected (Sel)
and unselected (No Sel) cells.
READ
WL
BL
SET
RESET
V(V)
I(A)
V(V)
I(A)
V(V)
Sel
1.8
0
3
0
3
I(A)
0
No Sel
0
0
0
0
0
0
Sel
0.4
0-80
1.5
300
2.7
600
No Sel
0
0
0
0
0
0
Fig. 3 – Microphotograph of the test chip.
In particular, Fig. 4 shows the measured voltage
waveforms in consecutive RESET and SET operations (VA
= column decoder supply; BL = bit-line; WL = word-line;
WE = write enable, active high). It should be noted that
during the RESET operation, the falling edge of the
addressed word-line voltage has to be very sharp so as to
allow the melted GST material to be rapidly cooled, thus
correctly amorphizing the cell. This operation, referred to
as quenching, is carried out by keeping the word-line fall
time within few ns (in our case, 2 ns). From Fig. 4, a
RESET pulse of 40 ns and a SET pulse of 150 ns were
demonstrated without any appreciable disturb on the bitline voltage.
A fully symmetrical sense amplifier topology [6] was
integrated in the test-chip to ensure zero systematic offset
together with adequate rejection of disturbs due to
capacitive coupling with noisy substrate, power supply, and
ground. As mentioned in the Introduction, the sense
amplifier compares the addressed cell current to a reference
cell current. Figure 5 illustrates the measured voltage
waveforms when reading a SET cell (O E _ N = output
enable, active low; OUTPUT DATA = I/O pin; cell current
= 80 A; reference current = 30 A). The achieved read
access time is 45 ns. Also in this case, no appreciable
disturbs on the bit-line voltage are observed.
IV. CONCLUSIONS
In this paper, a bit-line biasing technique has been
presented. The proposed approach allows read and write
voltages to be fed to the storage element with adequate
accuracy, high rejection of disturbs from the column
decoder supply line, and protection against spurious
program operations in read mode. Fast bit-line precharge
and sensing are also ensured. The proposed scheme was
integrated in a 4-Mb MOSFET-selected Phase-Change
Memory test-chip and experimentally evaluated. Although
the presented technique has been developed for PCM
technology, it is also suitable for use in other non-volatile
storage devices such as Flash memories.
REFERENCES
[1] S. Tyson, G. Wicker, T. Lowrey, S. Hudgens, and K. Hunt,
“Nonvolatile, high density, high performance phase-change
memory”, Proc. 2000 IEEE Aerospace Conference, vol. 5, pp.
385-390, March 2000.
[2] M. Gill, T. Lowrey, and J. Park, “Ovonic Unified Memory – A
high performance nonvolatile memory technology for standalone memory and embedded applications”, 2002 IEEE SolidState Circuits Conference Dig. Tech. Pap., vol.1, pp. 458-459,
Feb. 2002.
Fig. 4 – Measured voltage waveforms during SET and RESET
operations (WL, BL: active probes, attenuation by a factor of 10).
[3] F. Pellizzer, A. Pirovano, F. Ottogalli, M. Magistretti, M.
Scaravaggi, P. Zuliani, M. Tosi, A. Benvenuti, P. Besana, S.
Cadeo, T. Marangon, R. Piva, A. Spandre, R. Zonca, A.
Modelli, E. Varesi, T. Lowrey, A. Lacaita, G. Casagrande, P.
Cappelletti, and R. Bez, “Novel trench phase-change
memory cell for embedded and stand-alone non-volatile
memory applications”, to appear in Proc. 2004 Symposium on
VLSI Technology.
[4] G. Torelli and P. Lupi, “An improved method for
programming a word-erasable EEPROM”, Alta Frequenza,
vol. LII, pp. 487-494, Nov./Dec. 1983.
[5] V. N. Kynett, M. L. Fandrich, J. Anderson, P. Dix, O.
Jungroth, J. A. Kreifels, R. A. Lodenquai, B. Vajdic, S. Wells,
M. D. Winston, and L. Yang, “A 90-ns one million
erase/program cycle 1-Mbit Flash memory”, IEEE Journal of
Solid-State Circuits, vol. 24, no. 5, pp. 1259-1264, Oct. 1989.
[6] F. Bedeschi, E. Bonizzoni, O. Khouri, C. Resta, and G. Torelli,
“A fully symmetrical sense amplifier for non-volatile
memories”, to appear in Proc. 2004 IEEE International
Symposium on Circuits and Systems.
[7] W. Y. Cho, B.-H. Cho, B.-G. Choi, H.-R. Oh, S.-B. Kang, K.S. Kim, K.-H. Kim, D.-E.Kim, C.-K. Kwak, H.-G. Byun, Y.N. Hwang, S.-J. Ahn, G.-T. Jung, H.-S. Jung, and K. Kim, “A
0.18 m 3.0 V 64Mb non-volatile phase-transition randomaccess memory (PRAM)”, 2004 IEEE Solid-State Circuits
Conference Dig. Tech. Pap., vol. 47, pp. 40-41, Feb. 2004.
Fig. 5 – Measured voltage waveforms when reading a SET cell
(OE_N and BL: active probes, attenuation by a factor of 10).
[8] J. Dickson, “On-chip high voltage generation in NMOS
integrated circuits using an improved voltage multiplier
technique”, IEEE J. Solid-State Circuit, vol. SC-11, no. 3, pp.
374-378, June 1976.