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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 5, MAY 2009
1477
Neural Network and Bandless Hysteresis Approach
to Control Switched Capacitor Active Power
Filter for Reduction of Harmonics
Mohd Amran Mohd Radzi, Member, IEEE, and Nasrudin Abd. Rahim, Senior Member, IEEE
Abstract—This paper proposes a combination of neural network and a bandless hysteresis controller, for a switched capacitor
active power filter (SCAPF), to improve line power factor and to
reduce line current harmonics. The proposed active power filter
controller forces the supply current to be sinusoidal, in phase with
line voltage, and has low current harmonics. Two main controls
are proposed for it: neural network detection of harmonics and
bandless digital hysteresis switching algorithm. A mathematical
algorithm and a suitable learning rate determine the filter’s optimal operation. A digital signal controller (TMS320F2812) verifies the proposed SCAPF, implementing the neural network and
bandless hysteresis algorithms. A laboratory SCAPF system is
built to test its feasibility. Simulation and experimental results are
provided to verify performance of the proposed SCAPF system.
Index Terms—Bandless hysteresis, harmonic, neural network,
power factor, switched capacitor active power filter (SCAPF).
I. I NTRODUCTION
T
HERE is growing concern regarding power quality of ac
supply systems. The main problem is harmonic distortion;
high usage of power electronic devices implemented in electricity supply networks increase it, and nonsinusoidal currents
of the nonlinear loads affect the system. Compensation of the
generated harmonics and correction of the load power factor are
necessary.
An active power filter (APF) is a main harmonic mitigating
tool as it is developed from the advances of power electronic
technology. Various topologies of APF are reported and inverter
is commonly discussed [1]–[3]. Various control methods to
ensure expected performance are also discussed [4]. Several
works offer switched capacitor APF topology [2], [5]–[8]. The
topology can be called as switched capacitor APF (SCAPF);
it brings new dimension to APF as it reduces components
and ratings (particularly capacitor) while performing at low
switching frequency. Comparison of the SCAPF topology with
other related APF topologies has been discussed in [2].
This paper proposes an improved control algorithm SCAPF.
Various control strategies for APFs have been developed previ-
Manuscript received July 10, 2008; revised January 5, 2009. First published
February 6, 2009; current version published April 29, 2009.
The authors are with the Center of Research for Power Electronics, Drives,
Automation and Control, Department of Electrical Engineering, University
of Malaya, 50603 Kuala Lumpur, Malaysia (e-mail: [email protected];
[email protected]).
Digital Object Identifier 10.1109/TIE.2009.2013750
ously [1], [4]. They can be classified into three main categories:
reference generation (known also as harmonic detection or
isolation method), current control (known also as switching
strategy), and dc-bus voltage control (usually implemented in
inverter-based control).
This paper proposed differs slightly different from inverterbased topology; the third control is unnecessary, less complicating the whole system easy implementation of control
algorithm in a small, limited speed and limited memory, embedded controller.
As [4] explains, detection of harmonics can be implemented
through methods of time domain, frequency domain, and heterodyne (which involves multiplying a distorted signal by a
sinusoid), pattern learning and identification (which mainly
reports on neural network technique), and instantaneous power
compensation (which uses the definition of instantaneous active
power and reactive power theory).
In a previous development of SCAPF, the optimization algorithm extracted the harmonic component and directly created
filter current switching pattern [5]. The method tends to complicate computation, and the convergence causes time delay.
Genetic algorithm improved the convergence time, improving
it [9]. However, the algorithm’s complexity is a main issue in
the system’s development.
Moreover, both algorithms are implemented as offline control, slowing performance. In [10], analog circuit extracted
harmonics through principle of adaptive noise canceling. The
topology has three bidirectional switches, two connected to
capacitors for operation of their voltage polarity [8], another
connected to an inductor. Thus, hysteresis current control can
be used as online control for the filter. However, the control
method needs analog and logic circuits, which complicates
hardware development.
This paper proposes, for extraction of harmonics, a fast
and improved artificial neural network (ANN) control scheme.
Previous works [11]–[17] exist, particularly in inverterbased topology. It is widely developed, owing to its simplicity, and learning and generalization ability. Furthermore,
possible control scheme modification through a weightsupdating algorithm will speed up extraction of harmonics,
shortening adaptation time and realizing fast response of the
SCAPF.
This paper prefers the least-squares approach. Most popular
is the least-mean-square (LMS) algorithm, known also as the
delta rule or the Widrow–Hoff (W–H) rule; basically, it operates
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 5, MAY 2009
with a single linear neuron model. The algorithm can be used
directly in an APF application as in [11] where two neural
adaptive filters in “notch” and “band” configurations were
developed. The algorithm is also applied directly to determine
components of active, reactive, and harmonic currents, for
selective compensation on priority with respect to the inverter’s
limited power capacity [12]. Other application works [13]–[16]
report their adaptation of the algorithm. A modified W–H rule
minimizes average square error between actual and estimated
signals.
An interesting work on ANN algorithm is the algorithm’s
modification; only the fundamental component with a proper
learning-rate value is depended on [16]. Simulation work with
it showed tremendous performance. Yet, challenges still exist in
the experimental test implementation, and in lack of discussions
on methods and ideas for a good range of learning rate value.
This paper therefore proposes how the algorithm can be helpful
in a SCAPF application and discusses a few considerations in
selecting proper learning rate value.
This paper implements digitally the ANN algorithm. A digital control system is preferable to an analog one as a digitalsystem tool can be fully optimized to process and analyze
real-time signals. One of the best tools is digital signal processor (DSP), used in developing the hardware. With growing
DSP use in various digital control applications, APFs also
are not excluded of using the processor to miniaturize systems and perform at high speed. Previous works [18]–[20]
report the importance of DSP in implementing, and testing
by experiment, the designed algorithms, in ensuring expected
performance.
The next stage is implementing switching algorithm; a hysteresis algorithm is proposed. This technique is widely used
owing to its simplicity and robustness [8], [12], [16]. The
switching pulse is produced when the real signal operates
within an allowable band of reference signal; this sometimes
causes problem in digital operation where high ripple is produced at the output and more time is required for algorithm operation. Therefore, this paper proposes an improved switching
technique; it can be called a bandless digital hysteresis control.
It just neglects to use a band control in hysteresis algorithm
in determining the filter’s switching pattern, directly reducing
ripple component in the filter’s current, simultaneously minimizing time required for calculation and for comparison tasks
by the DSP.
Section II of this paper describes the SCAPF’s topology as an
alternative APF. Section III discusses development of its control
system, and Section IV presents simulated results. Section V
presents experimental work and results validating the SCAPF’s
performance, ending in Section VI with a summary of the
SCAPF’s function and performance.
II. SCAPF T OPOLOGY
Fig. 1 shows a basic diagram of an APF system connected
parallel to a nonlinear load. In nonlinear load without APF,
the load current iL comprises a fundamental component i1
and harmonic components iH , both present within the source
current iS , polluting the power system. After APF is connected,
Fig. 1.
Basic configuration of APF.
Fig. 2.
SCAPF topology.
it generates a filter current iF which then compensates harmonic
current produced by the load, as shown by
iS = iL + iF = i1 + iH + iF .
(1)
Therefore, if iF = −iH , the source current iS will only contain
the fundamental component.
Fig. 2 shows a block diagram of the SCAPF’s topology,
showing two capacitors in series with two main bidirectional
switches connected parallel to the ac line. In the experiment,
since both switches are considered to be applied with a small
deadband during their transition period, a small resistor with
another bidirectional switch is required to allow smooth transfer
of current between both capacitor branches at that period. All
switches are connected to the DSP, which performs digital
control algorithm in the system. Two current sensors measuring
load and filter currents are connected to the DSP. A small
limiting inductor is connected between all branches and line
to control the filter current.
Switches S1 and S2 work in antiphase so that the filter current flows through the branches alternately. Another switch, S3
will work during the transition period of S1 and S2 . Both capacitors are charged and switching patterns are determined through
a hysteresis algorithm explained later. The filter current’s rate of
change is controlled by a limiting inductor. The two capacitor
branches make the circuit’s operation more flexible, allowing
switching at any instant and also at any switching frequency.
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RADZI AND RAHIM: NEURAL NETWORK AND BANDLESS HYSTERESIS APPROACH TO CONTROL SCAPF
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III. C ONTROL D EVELOPMENT
A. Neural Network Detection
As mentioned, extraction of harmonic component is through
ANN algorithm; the principle of using the sum of sine and
cosine components with an appropriate coefficient attached to
each component to represent any periodic signals.
For each sample k in digital operation with sampling time
Δt and fundamental frequency ω, the nonlinear load current
iL is represented by a fundamental component and a harmonic
component as shown by
N
iL (k) =
[w1n sin(nkωΔt) + w2n cos(nkωΔt)]
n=1,2,3,...
= w11 sin(kωΔt) + w21 cos(kωΔt)
+
N
[w1n sin(nkωΔt) + w2n cos(nkωΔt)]
n=2,3,...
(2)
where w1n and w2n are the amplitudes of the sine and cosine
parts of the measured nonlinear load current, an n is the number
of harmonics, to N maximum number.
Both terms can be represented in vectorial form as
T
iL (k) = W X(k)
where the weight matrix W
the sine and cosine vector
T
(3)
= [w11 w21 , . . . , w1N w2N ] and
⎤
sin(kωΔt)
⎢ cos(kωΔt) ⎥
⎥
⎢
⎥
⎢.
⎥
⎢
X(k) = ⎢ .
⎥.
⎥
⎢
⎥
⎢.
⎦
⎣
sin(N kωΔt)
cos(N kωΔt)
⎡
Fig. 3. Harmonic extraction by ANN.
lengthens calculation time, relatively, a simplified algorithm
[16] proposes that
W (k + 1) = W (k) +
T
The ANN algorithm is used to train W to generate the right
value of iL (k), as shown in Fig. 3. The heart of this algorithm
extraction circuit is the weights updating algorithm block where
the W–H weights updating algorithm is used. The W–H weights
updating algorithm can minimize the average square error e(k)
between the actual measured signal iL (k) and the estimated
signal iest (k), which can be written as
W (k + 1) = W (k) +
e(k)X(k)
T
(4)
X (k)X(k)
T
where e(k) = iL (k) − iest (k) and X (k)X(k) is the square of
the norm of the vector X(k).
T
However, the dimension of the weight matrix W is updated according to the number of harmonic orders N , which
αe(k)Y (k)
(5)
T
Y (k)Y (k)
T
sin(kωΔt)
where W = [w11 w21 ], Y =
and α is the
cos(kωΔt)
learning rate.
This modified W–H algorithm needs only to update the two
weights of the fundamental component, making it independent
of the number of harmonic orders present. The modification is
based on the mathematical relationship of the elements being
orthogonal to each other. With this modification, the iteration
speed is greatly enhanced, resulting in faster estimation. However, updating only the two weights results in a large e(k).
Hence, a learning rate is added, as shown in (5), and Fig. 4
shows the modified version of proposed ANN algorithm.
The next issue of implementing this method is the selection
of suitable learning rate value. Previously, initial work was
carried out with some range of learning rate [21] but, then,
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 5, MAY 2009
Fig. 5.
Normal hysteresis.
Fig. 6.
Digital hysteresis.
Fig. 4. Modified ANN.
this paper does not discuss selection of learning rate, and experimental work on the algorithm’s implementation in handling
harmonics existing in the system does not show encouraging
results.
Therefore, further study is needed to determine a good range
of learning rate. From (4), if maximum number of harmonic N
is decided, the square of the norm of the vector X(k) results in
N , too. However, in (5), the square of the norm of the vector
Y (k) is one as it contains only the fundamental component.
Therefore, the learning rate can be chosen to be less than 1/N
to ensure the algorithm’s optimum performance.
The harmonic current, iH (k) can be produced from load
current deduction (from load current’s fundamental sine part),
or as follows:
iH (k) = iL (k) − w11 sin(kωΔt).
(6)
Two main considerations are proposed for the best learning
rate value: how fast the algorithm can produce the harmonic
current iH to be used in hysteresis algorithm later, and how good
the algorithm can produce harmonic current iH to minimize
THD of source current iS .
B. Bandless Digital Hysteresis Current Control
Hysteresis current control seems to be widely used since it
is easy to be implemented than other switching methods are. In
SCAPF application, this switching scheme has been used with
analog scheme development [10]. However, digital hysteresis
can be considered, too, since it will minimize hardware development complexities.
As an introduction, from Fig. 5, normal hysteresis in an
analog control operates when filter current iF reaches bandwidth ΔI of the reference current iREF before the switch state
changes. The proper selection of ΔI together with a limiting inductor improves filter performance in produce smoother
current. Through this method, the switching frequency varies
according to the switch state.
However, in digital control, sample time T must be considered, to determine whether the switch will change state.
Fig. 6 shows an operational digital hysteresis control. Let the
system be sampled at time T . The bandwidth ΔI is set for
the hysteresis operation. Ideally, the switch changes its state
when the filter current reaches the bandwidth, but as it is
operated digitally, then it changes state only when it reaches
sampling point after going through the bandwidth. Therefore,
the switch changes its state at the desired sample rather than
at the bandwidth limit, causing the filter current to exceed
the bandwidth. Switching time is longer, resulting too low a
switching frequency. The ripple is higher and a bigger inductor
is needed to limit the ripple, directly increasing losses.
Therefore, and to avoid use of bandwidth, this paper implements a modified digital hysteresis current control. Fig. 7
shows the proposed algorithm. The switch will change state
at sampling point after iF is higher, or lower, than iREF . The
algorithm can be explained as below.
1) When iF < iREF , S1 is on.
2) When iF > iREF , S1 is off.
The ripple will be lower than it was before as long as an
inductor of suitable value is selected. Switch operation is optimized, resulting in a smooth waveform. Although the switching
frequency varies, the maximum value can be determined. If T
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RADZI AND RAHIM: NEURAL NETWORK AND BANDLESS HYSTERESIS APPROACH TO CONTROL SCAPF
Fig. 7.
Bandless digital hysteresis.
is sample time, then the switching period is in minimum value
at double of sample time T .
Maximum switching frequency can be determined from
fswitch (max) =
1
.
2T
(7)
Therefore, sampling frequency or sample time must be
properly selected when programming the DSP. Among the
considerations, the DSP must have enough time to handle
acquisition of data from sensor measurements, be capable in
handling calculation of algorithm for harmonic detection at
each sampling time, and be able to compare with the reference
current, the filter current, in the hysteresis algorithm, at each
sampling time.
A high sampling frequency increases sensitivity of the controller’s reaction to the signal, but will limit time to handle all
algorithms. Those requirements are considered in the experiment’s implementation.
C. Implementation of Digital Control in DSP
This paper chooses a DSP for its fast processing speed, which
enables high sampling task, and for its capability to cover mathematical algorithm, considered the main element of the control.
Its smallness provides advantage over the usual processor in
running a specialized task. Configuration of SCAPF’s control
algorithm is therefore developed directly in the DSP.
In digital control, data is based on sample time set through
the controller. The DSP as the selected controller with the
proper setting of sampling frequency captures continuously
signals from measured points of sampling time. This paper
uses sampling frequency in determine the number of samples
acquired from sensors within one cycle, and to generate switching signal. The sampling frequency is set at 25 kHz (40 μs
in sampling time). For a 50-Hz operation, 500 samples can
be captured. Equation (7) determines the maximum switching
frequency
fswitch (max) =
1
= 12.5 kHz.
2 × 40 × 10−6
Fig. 8 shows the control block developed in the DSP. One
voltage sensor and two current sensors are used at measure-
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ment. The voltage sensor measures voltage at the point of
common coupling Vpcc . One current sensor is connected to the
load, measuring load current IL and another is connected to
SCAPF, measuring filter current IF .
A zero-crossing detector (ZCD) circuit is designed to generate signal to the DSP when a zero crossing voltage is detected at
the point of common coupling. The measurement processed by
DSP starts from the ZCD circuit’s signal detection. The ZCD’s
input module program initializes starting time of the DSP’s
sampling operation.
Measurement of IL and IF are processed by an analog-todigital (ADC) module in the DSP, analog values converted to
digital ones. IL is processed by the harmonic detection algorithm, ANN, for harmonic current IH . This current is compared
with IF in the hysteresis algorithm, to produce pulse signals
equivalent to those of S1 and S2 .
IV. S IMULATION R ESULT
The circuit was developed and tested in MATLAB Simulink
together with SimPowerSystems block. A control block implemented the ANN algorithm, performing the bandless digital
hysteresis algorithm. The solver was configured by using discrete variable step to ensure the simulation’s digital operation.
Sampling time was set as 40 μs. The simulation’s main purpose
was to determine the best range of learning rate value for use in
the experiment. The effectiveness of hysteresis control was also
observed.
Two types of nonlinear loads were developed by using a
diode bridge rectifier, feeding a capacitive load comprising of
a 470-μF capacitor and 50-Ω resistor, and feeding an inductive
load comprising a 160-mH inductor and a 15-Ω resistor. Table I
shows details of the proposed SCAPF’s parameters.
In the beginning, both circuits were simulated without connecting SCAPF. In capacitive load, the THD was 77.03%,
and in inductive load, it was 33.19%. Then, the SCAPF was
connected to both configurations of the circuit and learning
rate values from 0.006 to 0.0007 were chosen for testing.
Table II presents observations on time taken for the algorithm to
successfully form a stable iH , and the THD measurements when
the learning range was changed. From Table II, the learning
rate’s optimum value was 0.003, where the time taken was only
in two cycles, and the THD was measured within allowable
limits for both types of nonlinear loads. Although the smaller
value could reduce THD owing to production of good iH , it
would cause slow increment of iH in each sample k value.
Therefore, the stated value was selected as it would help the
algorithm to produce a stable iH faster, and then minimize the
THD to within allowable limits.
Fig. 9 shows waveforms of harmonic current IH extracted
by ANN algorithm through the best learning rate of 0.003
for both capacitive and inductive loads. The ANN algorithm
successfully produced a stable iH after two cycles. Figs. 10 and
11 show waveforms of the source voltage, the load current, the
filter current, and the source current for capacitive load and
for inductive load, respectively. From Table II and Fig. 10, in
the capacitive load, the THD reading was recorded as 3.27%.
Besides having a good iH , hysteresis control also helps in
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 5, MAY 2009
Fig. 8. Control block developed in DSP.
TABLE I
PARAMETERS FOR PROPOSED SCAPF
TABLE II
OBSERVATION TIME TO OBTAIN STABLE IH AND THD MEASUREMENT
FOR S PECIFIED L EARNING R ATES
Fig. 9. Harmonic extractions by ANN algorithm for both capacitive and
inductive loads.
minimizing allowable value of THD. At the same time, iS
seemed to work in phase with VS , which led to a maximum
power factor. In inductive load, the THD was 2.69%. The
SCAPF also successfully compensated harmonic current (see
Fig. 11). The ANN algorithm took two cycles to get a stable iH
and iS seemed to work in phase with VS .
V. E XPERIMENT R ESULT
The experiment setup is as shown in Fig. 12. The SCAPF
sampling frequency was 25 kHz. Three insulated gate bipolar transistors (1200 V, 41 A) and 12 fast recovery diodes
(1200 V, 30 A) were used to develop bidirectional switches.
Three bidirectional switches were developed, two connected to
120-μF capacitors, and one to a 15-Ω resistor.
A diode bridge rectifier configuration feeding a capacitive
load comprising a 470-μF capacitor and 50-Ω resistor was set
up as a nonlinear load. The capacitor and the resistor were
connected to a 5-mH limiting inductor.
A DSP TMS320F2812 implemented the control algorithms.
The DSP was selected as it has a 32-b CPU performing at
150 MHz. Among its interesting features, useful in this paper,
were a 12-b ADC module handling 16 channels, and two onchip event manager peripherals providing a broad range of
functions particularly useful in applications of control. The
programming part for ANN algorithm and bandless digital
hysteresis algorithm were developed and written in C language
and then compiled in Code Composer Studio. The compiled
program was downloaded onto the DSP. Sampling frequency
was set at 25 kHz. The ANN algorithm was configured by using
a learning rate of 0.003, already determined in simulation to be
the optimum value.
Voltage source, load current, filter current, and source current
were measured. THD was measured through a Power Quality
Analyzer. To study this filter’s effectiveness, power factor was
also measured for both types of load configurations. Fig. 13
shows the results.
Fig. 13 also shows the SCAPF to have functioned very well
in compensating load harmonic current, with the source current
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RADZI AND RAHIM: NEURAL NETWORK AND BANDLESS HYSTERESIS APPROACH TO CONTROL SCAPF
1483
Fig. 12. Configuration of experimental setup.
Fig. 10. Simulated waveforms for the source voltage VS , the load current IL ,
the filter current IF , and the source current IS for capacitive load.
Fig. 13. Experimental result for the source voltage VS (200 V/div), the load
current IL (10 A/div), the filter current IF (10 A/div), and the source current
IS (10 A/div) for capacitive load.
digital hysteresis algorithms developed in the DSP were able
to operate the filter in reducing the THD value, with reduced
current harmonics.
Fig. 14 shows results of the experiment when SCAPF was
connected to the inductive load (160-mH inductor and 15-Ω
resistor). Load current THD was 26.3% while that of source
current was 4.6%. Power factor was 0.99. The encouraging
values show that this filter is able to reduce current harmonics.
VI. C ONCLUSION
Fig. 11. Simulated waveforms for the source voltage VS , the load current IL ,
the filter current IF , and the source current IS for inductive load.
waveform being almost sinusoidal. Load current THD was
58.6%, and that of the source current was 4.7%. The power
factor was 0.98. This means that the ANN and the bandless
The SCAPF proves to be a plausible alternative in reducing
harmonic distortion through capacitors connected to bidirectional switches. In the APF, a modified ANN and bandless
digital hysteresis algorithms were proposed for its control. The
ANN was designed and developed to detect harmonic component, and the bandless digital hysteresis was implemented to
produce switching strategies for the filter. A suitable learning
rate is important in implementing an ANN algorithm; therefore,
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 5, MAY 2009
Fig. 14. Experimental result for the source voltage VS (200 V/div), the load
current IL (10 A/div), the filter current IF (10 A/div), and the source current
IS (10 A/div) for inductive load.
the simulation found it. From the simulation, a laboratory
prototype was implemented practically. From the experiment,
current harmonics observed in the testing system, produced
from nonlinear loads, was successfully reduced. At the same
time, the source current was closely in phase with the voltage
source where power factor was near to unity.
R EFERENCES
[1] H. Akagi, “Active harmonic filters,” Proc. IEEE, vol. 93, no. 12, pp. 2128–
2141, Dec. 2005.
[2] M. El-Habrouk, M. K. Darwish, and P. Mehta, “Active power filters:
A review,” Proc. Inst. Elect. Eng.—Elect. Power Appl., vol. 147, no. 5,
pp. 403–413, Sep. 2000.
[3] B. Singh, K. Al-Haddad, and A. Chandra, “A review of active filters for
power quality improvement,” IEEE Trans. Ind. Electron., vol. 46, no. 5,
pp. 960–971, Oct. 1999.
[4] T. C. Green and J. H. Marks, “Control techniques for active power filters,”
Proc. Inst. Elect. Eng.—Elect. Power Appl., vol. 152, no. 2, pp. 369–381,
Mar. 2005.
[5] P. Mehta, M. Darwish, and T. Thomson, “Switched-capacitor filters,”
IEEE Trans. Power Electron., vol. 5, no. 3, pp. 331–336, Jul. 1990.
[6] P. Mehta and M. Darwish, “Active reactive-power controller,” Proc. Inst.
Elect. Eng.—Elect. Power Appl., vol. 142, no. 6, pp. 405–409, Nov. 1995.
[7] M. El-Habrouk and M. K. Darwish, “A new control technique for active
power filters using a combined genetic algorithm/conventional analysis,”
IEEE Trans. Ind. Electron., vol. 49, no. 1, pp. 58–66, Feb. 2002.
[8] T. Kandil, L. Lopes, and W. Xu, “Analysis and design of a new current
controlled switched capacitor filter for harmonic mitigation,” Elect. Power
Compon. Syst., vol. 33, no. 1, pp. 1–20, Jan. 2005.
[9] M. Welsh, P. Mehta, and M. K. Darwish, “Genetic algorithm and extended analysis optimisation techniques for switched capacitor active
filters—Comparative study,” Proc. Inst. Elect. Eng.—Elect. Power Appl.,
vol. 147, no. 1, pp. 21–26, Jan. 2000.
[10] T. Kandil, L. Lopes, and W. Xu, “Transient analysis of a per phase
switched capacitor based load compensator,” in Proc. 5th Int. Conf. Power
Electron. Drive Syst., Singapore, 2003, vol. 1, pp. 560–565.
[11] M. Cirrincione, M. Pucci, and G. Vitale, “A single-phase DG generation
unit with shunt active power filter capability by adaptive neural filtering,”
IEEE Trans. Ind. Electron., vol. 55, no. 5, pp. 2093–2110, May 2008.
[12] B. Singh, V. Verma, and J. Solanki, “Neural network-based selective
compensation of current quality problems in distribution system,” IEEE
Trans. Ind. Electron., vol. 54, no. 1, pp. 53–60, Feb. 2007.
[13] D. O. Abdeslam, P. Wira, J. Mercklé, D. Flieller, and Y.-A. Chapuis,
“A unified artificial neural network architecture for active power filters,”
IEEE Trans. Ind. Electron., vol. 54, no. 1, pp. 61–76, Feb. 2007.
[14] J. R. Vazquez and P. Salmeron, “Active power filter control using
neural network technologies,” Proc. Inst. Elect. Eng.—Elect. Power Appl.,
vol. 150, no. 2, pp. 139–145, Mar. 2003.
[15] P. K. Dash and S. K. Panda, “Fast estimation of voltage and current
phasors in power network using an adaptive neural network,” IEEE Trans.
Power Syst., vol. 12, no. 4, pp. 1494–1499, Nov. 1997.
[16] L. H. Hey, P. L. So, and Y. C. Chu, “Improvement of power quality
using adaptive shunt active filter,” IEEE Trans. Power Del., vol. 20, no. 2,
pp. 1558–1568, Apr. 2005.
[17] J. H. Marks and T. C. Green, “Predictive transient-following control
of shunt and series active power filters,” IEEE Trans. Power Electron.,
vol. 17, no. 4, pp. 574–584, Jul. 2002.
[18] B.-M. Han, B.-Y. Bae, and S. J. Ovaska, “Reference signal generator for
active power filters using improved adaptive predictive filter,” IEEE Trans.
Ind. Electron., vol. 52, no. 2, pp. 576–584, Apr. 2005.
[19] A. K. Jain and V. T. Ranganathan, “Wound rotor induction generator with
sensorless control and integrated active filter for feeding nonlinear loads
in a stand-alone grid,” IEEE Trans. Ind. Electron., vol. 55, no. 1, pp. 218–
228, Jan. 2008.
[20] R. M. S. Filho, P. F. Seixas, P. C. Cortizo, L. A. B. Torres, and A. F. Souza,
“Comparison of three single-phase PLL algorithms for UPS applications,”
IEEE Trans. Ind. Electron., vol. 55, no. 8, pp. 2923–2932, Aug. 2008.
[21] M. A. M. Radzi and N. A. Rahim, “Neural network based detection in
switched capacitor filter for harmonic mitigation,” in Proc. 3rd IEEE
Conf. Ind. Electron. Appl., Singapore, 2008, pp. 1481–1486.
Mohd Amran Mohd Radzi (M’01) was born in
Kuala Lumpur, Malaysia, in 1978. He received the
B.Eng. (Hons.) and M.Sc. degrees in electrical power
engineering from Universiti Putra Malaysia (UPM),
Serdang, Selangor, Malaysia, in 2000 and 2002, respectively. He is currently working toward the Ph.D.
degree in the Center of Research for Power Electronics, Drives, Automation and Control, Department
of Electrical Engineering, University of Malaya,
Kuala Lumpur.
He is a Lecturer with the Department of Electrical
and Electronic Engineering, UPM. His research interests are power electronics,
power quality, and embedded controller applications.
Nasrudin Abd. Rahim (M’89–SM’08) was born
in Johor, Malaysia, in 1960. He received the B.Sc.
(Hons.) and M.Sc. degrees from the University of
Strathclyde, Glasgow, U.K., and the Ph.D. degree in
1995 from Heriot–Watt University, Edinburgh, U.K.
He is currently a Professor with the Department of
Electrical Engineering, University of Malaya, Kuala
Lumpur, Malaysia, and the Director of the Center of
Research for Power Electronics, Drives, Automation
and Control.
Dr. Rahim is a Fellow of the Institution of Engineering and Technology, U.K., and a Chartered Engineer. He is also Chairman
of the Working Group WG-8, covering reluctance motors, of the IEEE Motor
Subcommittee under IEEE Power Engineering Society/Electric Machinery
Committee. His research interests include power electronics, real-time control
systems, and electrical drives.
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