Download Chapter 2 Interconnect Parasitic Extraction

Chapter 7
High-Speed Signal
Prof. Lei He
Electrical Engineering Department
University of California, Los Angeles
URL: eda.ee.ucla.edu
Email: [email protected]
High-speed Links are Everywhere
Backbone
Router
Rack
PC or
Console
[Sredojevic:ICCAD’08]
High-Speed Links: Applications
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Chip-to-chip signaling
Computers, games: SDRAM(DDR, DDR2) 100-700MHZ,
RDRAM 800-1600MHz, DDR3 800-1600MHz, DDR4 1.63.2GHz, XDR DRAM 3.2-6.4GHz
Board-to-board
Computers: Peripherals- PCI (66-133-400MHz), PCIe (250M500M-1GHz), Infiniband (2.5Gb/s)
Networks
LAN: Fast Ethernet, Gigabit Ethernet, 10G Ethernet
WAN: OC-12 (625MHz), OC-192(12.5GHz)
Routers: 625Mb/s – 2.5Gb/s
Outline
Link Design Basics
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Signal Integrity
High Speed Signaling Architectures
Equalization
Post-Silicon Tuning of High-Speed Signaling
Noise
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Signals may be corrupted from many sources
Inter-symbol interference (ISI)
– Frequency-dependent attenuation (dispersion)
– Reflection
– Oscillation
Crosstalk
Power supply noise
Real noise
– Thermal and shot noise
Parameter variation
Noise measure
Eye diagram
– Timing jitter
– Amplitude noise
Inter-Symbol Interference
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A signal interfering with itself
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Ideally a transmission system is time invariant
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No history of previous bits
In reality, the state of the system is affected by previous bits
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Signals that don’t reach the rails by the end of cycle
– Signal’s transition time is limited by channel bandwidth
Reflections on the transmission lines
Magnitude and phase of excited resonances
ISI - Dispersion
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Frequency-dependent attenuation
In general, channel is low pass
Our nice short pulse gets spread out
Example: a 101 pattern
ISI - Reflection
Reflections of previous bits travel up
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and down transmission lines
A mismatch of δ gives (to the first

order) a reflection of ρ
Z0  Zt 1  


Z0  Zt 1  
ISI - Resonances
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Oscillations are excited by signal
transitions and may interfere with later
transitions
Excitation of resonant circuits is reduced
with longer transition times
Slower edge has less high frequency
spectral content
Resistance damps oscillation
Crosstalk
• Crosstalk is the coupling of energy from one line to another via:
• Mutual capacitance (electric field)
• Mutual inductance (magnetic field)
• One signal interfering with another signal
Mutual Inductance, Lm
Mutual Capacitance, Cm
Zo
Zo
Zo
Zo
far
far
Cm
Lm
near
Zs
Zo
near
Zs
Zo
Crosstalk Induced Noise
• The mutual inductance will induce current on the victim line opposite
of the driving current (Lenz’s Law)
• The mutual capacitance will pass current through the mutual
capacitance that flows in both directions on the victim line
Zo
I Cm
Zo
Zo
dV
 Cm
dt
Zo
far
far
ICm
ILm
Lm
near
Zs
Zo
near
Zs
Zo
I near  I Cm  I Lm
I far  I Cm  I Lm
VLm
dI
 Lm
dt
Voltage Profile of Coupled Noise
• Near end crosstalk is always positive
• Currents from Lm and Cm always add and flow into the node
• For PCB’s, the far end crosstalk is “usually” negative
• Current due to Lm larger than current due to Cm
• Note that far and crosstalk can be positive
Zo
Zo
Far End
Driven Line
Un-driven Line
“victim”
Zs
Driver
Near End
Zo
Power Supply Noise
The power supply network has parasitic
elements
On-chip: resistive
Off-chip: inductive
 Current draw across these elements
induces a noise voltage:
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d
Ri  L i (t )
dt
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Instantaneous current is what matters
May be many times the DC current
– 10W chip draws 4A at 2.5V
– Peak current may be 10-20A
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Simultaneous Switching Outputs (SSO)
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When several outputs switch
simultaneously, significant current is
drawn from the supply or sent into
ground
Supply connections have inductance
SSO currents produce a voltage drop
across these inductances
On-chip, the VDD to VSS voltage
difference decreases
Effect grows with number of drivers
switching
Quadratic with the inverse of
transition time
Between chips, the drops across VSS
inductances can effect driver timing
and shift the receiver threshold
Other Noise Sources
Alpha particles
5MeV particle injects 730fC of charge into substrate
One node typically collects less than 50fC
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Thermal and shot noise
Proportional to bandwidth – typically in the uV
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Parameter mismatch
VT and β have deviation proportional to 1/sqrt(WL)
Systematic variations depend on layout
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Eye Diagram
This is a “1”
This is a “0”
Eye – space between 1 and 0
With voltage noise
With timing noise
With both!!
Eye Diagram (cont’d)
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Standard measure for signaling
Synchronized superposition of
all possible realizations of the
signal viewed within a
particular interval
channel
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Timing jitter
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Deviation of the zero-crossing
from its ideal occurrence time
Amplitude noise
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Set by signal-to-noise ratio
(SNR)
The amount of noise at the
sampling time
TX
RX
Outline
Link Design Basics
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Signal Integrity
High Speed Signaling Architectures
Equalization
Post-Silicon Tuning of High-Speed Signaling
Signaling – Main Idea
A good signaling system isolates the signal from noise rather than
trying to overpower the noise
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Crosstalk
– Terminate both ends, use homogeneous media
ISI
– Matched terminations, no resonators, rise-time control
Power supply noise
– Avoid coupling into signal or reference
 Differential signaling
 Current mode
 stable reference
...1001...
...1001...
Multiplexer
Driver
Amp
Channel
Tx Clock
Rx Clock
Demultiplexer
Architecture of Signaling
Signaling Architecture Tradeoffs
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Signal modulation
PAM (Pulse-amplitude modulation)
Pulsed (Return-to-Zero, RZ) signaling
Binary (ex:NRZ) or Multiple-level signaling (MLS)
Uni-directional or Bidirectional
Time-multiplexed bidirectional or simultaneous bidir.
Single-ended or differential
Current mode or voltage mode
Bus or single-trace
Point-to-point or multi-drop
Example System - Trade-offs
Transmitter choices:
output impedance,
bipolar/unipolar driver,
amplitude, rise time,
single-ended/differential
Line considerations:
length, impedance,
attenuation, discontinuities
Termination choices:
source, destination,
both, underterm
Reference considerations:
VDD-div, Tx, Rx, diff
Receiver choices:
offset, sensitivity, BW
Voltage Mode vs Current Mode
Main differences are
Ease of control and generation
– Much easier to generate a small current than a small voltage
Coupling of supply noise
– 50% of supply noise shows up on the data line in the matched
voltage mode; potentially much less in a high-Z current-mode
driver
Generation of high-Z switches easier than controlled-Z switches
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Single-ended vs Differential
Single-ended signaling
compare to shared reference
Often used with a bus
Issues
– Generates SSO noise
– How to make reference
– How to quiet reference
– Crosstalk cannot be made
common-mode
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• Differential signaling
• compare between two lines
• Noise immunity
• Many noise sources
become common mode
• Issues
• Differential must run >
2x as fast as singleended to make sense
• Otherwise, powerx2,
pinsx2
Binary vs Multiple-level (4-PAM)
Binary (NRZ) is 2-PAM
Use 2-levels to send one-bit per
symbol
• 4-PAM uses 4-levels to
send 2 bits per symbol
• Each level has 2 bit value
When Does 4-PAM Make Sense?
Simultaneous Bidirectional Signaling
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Wires can transmit waves in both directions
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It seems a shame to only use one direction at a time
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Simultaneous Bidirectional Signaling
Transmit waves in both directions at the same time
Waveform on wire is superposition of forward and reverse
traveling wave
Subtract transmitted wave at each end to recover received
wave
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There are 3-levels on the line but it’s still 2-level signaling
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Much more sensitive to reflections and crosstalk
Outline
Link Design Basics
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Signal Integrity
High Speed Signaling Architectures
Equalization
Post-Silicon Tuning of High-Speed Signaling
Equalization
channel
equalizer
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Channel is band-limited, most of them are low-pass
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Goal is to flatten the overall response
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Equalization: Boost higher frequencies relative to lower frequencies
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Can be done at Tx or RX or both
Receiver Linear Equalizer
Amplifies high-frequencies attenuated
by the channel
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Pre-decision
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Digital or Analog FIR filter
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Issues
Also amplifies noise!
Precision
Tuning delays (if analog)
Setting coefficients (adaptive filter)
– Adaptive algorithms such as LMS
Transmitter Linear Equalizer
Tx Pre-emphasis Filter
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Attenuates low-frequencies
Need to be careful about output amplitude limited output power
– If you could make bigger swings, you would
– EQ really attenuates low-frequencies to
match high frequencies
Also FIR filter: D/A converter
Can get better precision than RX
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Issues
How to set EQ weights?
Doesn’t help loss at high f
Tx Linear EQ: Single Bit Response
Outline
Link Design Basics
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Signal Integrity
High Speed Signaling Architectures
Equalization
Post-Silicon Tuning of High-Speed Signaling
Process Variation vs Analog Circuits
[ITRS]
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Threshold voltage variation is increasingly dominant and is primarily random
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Due to increasing and random doping fluctuation
Corner-based design is not effective for match used widely in analog circuits
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Often results in over-sized circuits and excessive area/power
Post-Silicon Tuning is Effective
[Li:ICCAD’08]
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Post-silicon tuning is effective to compensate random process variation
Digitally tunable circuit is commonly adopted
Insensitivity to noise and variation
Suitable for process migration
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Post-Silicon Tuning of High-Speed Signaling
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Algorithm Framework
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Problem formulation
Branch and bound based algorithm
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Case Study I: Transmitter
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Case Study II: PLL
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Conclusions
Unit Cell Based Design Methodology
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Pre-characterize different types of unit cell, e.g., transistor with a given threshold voltage and
unit W/L.
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A transistor of larger W/L can be synthesized by connecting those unit cells of same type
in parallel
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Design variables simply become
–
type of unit cell α(threshold)
number of unit cells in parallel (sizing)
Constraints such as output swing is satisfied for correct operation
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Apply to other circuit elements such as unit capacitance and resistance
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Make design better and modeling more accurate
Digitally Tunable Circuits
with variation
Analog output
A
A+ A
A
A’=A- A’
LSB size
D[0]
D[1]
D[2]
w/o variation
A’
D’ D
Digital Input
one tap in a pre-emphasis filter
current source can be implemented by
current-division DAC
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Current-division DAC is commonly used to combat process variation
Two tuning parameters
LSB size (): minimum step during digital-to-analog conversion
Resolution (β): number of bits used
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Impact of Post-Silicon Tuning
(a) Without Tuning
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(b) With Tuning
Example: BER for a high-speed link
4-tap pre-emphasis filter in a transmitter
0% (3σ) variation in Vt
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Design-time optimization and post-silicon tuning circuit both need area, and
joint optimization is must
Joint Optimization
parametric yield
power constraint. Process variation changes
power
area constraint. Process variation does not
change layout area
bound on design parameters
bound on the total number of unit cells types
bound on the LBS and resolution
e
Optimization Challenges
 3000 Monte Carlo runs over different unit cell design α, resolution β,
and LSB size for one tap of FIR
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Discrete problem with non-convex objective and constraints
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Solution space surface is rough and many local maxima exist
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Significant improvement can be expected
Overall Algorithm
 Algorithm framework:
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 Partition the solution space by LSB size ( ) and unit cell type (α)
 Develop a bound on the parametric yield
 Discard (fathom) if bound worse than the current best solution
Use gradient ascent method to
find the local maxima
– Sequentially take steps in
γ
the direction proportional to
the gradient.
αi
γ
Bound estimation
Remove the area and power
γ
constraints
αj
All
infeasible
Use LMS algorithm to find
γ
optimal yield value
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i
j
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i
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j
αk
γi
γj
Pruned by upper bound check
Gradient Ascend Method
 In each un-pruned region, sequentially take steps in direction
proportional to the gradient, until a local maximum of the
objective function is reached.
 At each step, increase/decrease each variable by 1 in turn and
check the change of the objective function.
 Always take the change (direction) that causes the maximum
increase.
 Termination of the algorithm indicates that one of the local
maxima has been reached or that we have reached the boundary.
 The initial guess for the GDA can be arbitrarily chosen. In our
experiments, we find that it did not influence runtime or quality
significantly.
 We also observed that the algorithm always converges to local
optimum within two or three iterations.
Post-Silicon Tuning of High-Speed Signaling
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Algorithm Framework
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Case study 1: transmitter
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Knobs for design-time and post-silicon
Modeling and formulation
Experimental results
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Case Study 2: PLL
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Conclusions
Knobs for Optimization
Receiver
Transmitter
RD
Pre-driver
Channel
Slicer
out
data
Pre-amplifier
FIR pre-emphasis filter/driver
CDR
RD
N-tap FIR filter
a1
a0
an
Filter coefficients
IC0
IC1
ICn
Given transmission channel → filter coefficient → transistor size
change channel behavior ← parasitic capacitance
Knobs for Optimization
Receiver
Transmitter
RD
Pre-driver
Channel
Slicer
out
data
Pre-amplifier
FIR pre-emphasis filter/driver
CDR
RD
N-tap FIR filter
a1
a0
an
Filter coefficients
with
IC1
IC0
variation
ICn
Analog output
A
A+ A
A
A’=A- A’
LSB size
w/o variation
A’
D’ D
D[0]
D[1]
D[2]
Problem Formulation
For transmitter
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,
random variable
BER Distribution Comparison
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20% (3σ) variation in Vth with 10000
Monte Carlo runs
Design 1 - without tuning circuit
All resources are used for filter
– Unavoidable large variation
–
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Design 2 - one tap filter
–
–
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All resources are used for DAC
Has extreme small variance but
suffers severe ISI
Design 3 – heuristic design
Assume 4-tap filter
Assume LSB size is equal for each tap
– Limit the solution space
– Good improvement compared to two
extreme cases
–
–
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Design 4 - our algorithm
–
Provides better solution (mean,
Yield Rate
Experiment setting
Channel – 30cm differential microstrip line with FR-4 substrate
5GHz data rate
Yield is set by BER=1e-15 (estimated by EVM)
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Yield comparison for different area constraints
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Our algorithm always provide
better yield than design heuristic
With aggressive area constraint,
our algorithm has much less
yield degradation
Saturation effect
Up to 47% improvement
area
Yield with Power Constraint
power
vt variation
Post-Silicon Tuning of High-Speed Signaling
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Algorithm Framework
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Case study 1: Transmitter
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Case study 2: PLL Design
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Conclusions
Jitter Modeling
PLL output clock jitter
Hnin and HnVCO are the noise transfer function of reference clock noise and VCO
noise
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E.g.
 Tunable PLL

CLKVCO
CP1
Jitter can be changed by
tuning the charge pump current
ratio
[Mansuri:JSSC’02]
CLKref
ФnIN
ω0
PFD
KPFD
UP /
DN
VINT
OPamp
CCP
1/gmOP
VCtrl
VCO
KVCO/S
ФnVCO
ICP
VCtrl
η×ICP
VINT
CP2
ФOUT
Joint Optimization
Design-time optimization
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Two charge pumps Icp1, Icp2
Ratio (Icp1/ Icp2) determines
output RMS jitter
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Optimal ratio can be found using
design-time optimization
Again, process variation would cause
performance degradation
Digitally tuned current mirror
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Small reference current
–
Consumes less power
–
η need to be far less than
unity
–
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Limited tuning resolution
Large reference current
–
Good tunability
–
Power and area penalty
[Horowitz:JSSC’00]
Same Formulation Applies
For PLL
objective function becomes
and area can be computed in a way similar to the transmitter case.
Experimental Results
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PLL with digitally controlled charge pump current
Yield is defined by output clock RMS jitter
Design heuristic using minimized biasing current
Consider 30% Vth variation
Improve the yield by up to 56%
Conclusions
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Formulate a joint optimization problem for digitally tuned analog
circuits
Consider both design-time optimization and post-silicon tuning
Maximize performance yield s.t. power and area constraints
Propose a general optimization framework
Combine branch-and-bound and gradient-ascent algorithm
Effectively find the global optimum
Two joint optimization design examples for high-speed serial link
Transmitter design
PLL design
Experiments show great (>47%) yield improvement over common
circuit design heuristic
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