Download Slides

VAX-11/780
A VIRTUAL ADDRESS EXTENSION TO THE DEC
PDP-11 FAMILY
W.D.STRECKER
Motivation
-Limited virtual address space
Features
-extension of virtual address from 16 bits to 32 bits.
-with 8 bit byte the basic addressable unit, the extension
provides a virtual address space of 4.3GB.
One of the main goals of VAX-11 was maximum PDP-11 compatibility.
-VAX-11 includes two modes
-compatibility mode.
-provides basic PDP-11 instruction set less only privileged
instructions and floating point instructions.
-native mode
-native mode data types and formats are identical to PDP-11.
As a consequence VAX-11 native mode assembly language programming
is similar to PDP-11.
-VAX-11/780 uses the same peripheral buses (Unibus and Massbus)
and the same peripherals.
-The VAX/VMS file system is same as used in RSX-11M/IAS
operating systems permitting interchange of files and volumes.
-VAX-11 high level language compilers accept the same source languages
as equivalent PDP-11 compilers and the execution of compiled programs
gives the same result.
VAX-11 NATIVE ARCHITECTURE
Processor state
-VAX-11 is organized around a general register processor state. This
organization was favored because access to operands stored in general
registers is fast and because only small number of bits in an instruction
are used to designate a register.
-Registers are used with large set of addressing modes which permit flexible
operand addressing methods.
-VAX-11 has 16 32 bit general registers which are used for both
fixed and floating point operands. (PDP-11 has 8 16 bit general registers
and 6 64 bit floating point registers). Merged set of fixed and floating point
registers were favored as it simplified programming.
Four registers in VAX-11 architecture are assigned special meaning.
They are
Program counter (R15) – contains address of next byte to be
interpreted in instruction stream.
Stack pointer(R14) – contains the address of the top of the processor
defined stack used for procedure and interrupt linkage.
Frame pointer(R13) – The VAX-11 procedure calling convention builds
a data structure on stack called stack frame. FP contains the
address of this structure.
Argument pointer(R12) – The VAX – 11 procedure calling convention
uses a data structure called argument list. AP contains the address
of this structure.
DATA TYPES AND FORMATS
-Integer data type
-8 bit byte, 16 bit word,32 longword, 32 bit quadword.
-Floating data type
-32 bit floating(7), 64 bit floating(16).
-Variable bit field data type
- 0 to 32 bits located arbitrarily with respect to addressable byte
boundaries.
-
Character string data type
-0 to 65535 contiguous bytes. Specified by two operands i.e the
length and starting address of the string.
-Decimal string data type
-0 to 31 digits. Specified by two operands i.e length and starting
address.
-the Primary data type is packed decimal which contains two digits in
each byte and byte containing least significant digit has single digit.
An instruction consists of one or two byte opcode
followed by specifications of operands. An operand
specification is one to 10 bytes in length and consists of one or two
byte operand specifier followed by specifier extension.
Address modes :
Register mode
-designated register contains the operand.
Register deferred mode
-designated register contains the address of the operand.
Autoincrement mode
-contents of the designated register is used as the
address of the operand and is incremented by the size of
the operand. (PC - immediate mode)
Autoincrement deferred mode
-contents of the designated register are used as the address of
longword in memory which contains the address of the operand.
(PC-absolute mode)
Displacement mode
-displacement is added to the contents of the designated register
to form the operand address. (PC- relative mode)
Displacement deferred mode
-displacement is added to the designated register to form the address
of longword containing the operand address. (PC – relative deferred
mode)
Literal mode
-operand specifier itself contains a 6-bit literal which is the operand.
Index mode
- not really a mode but a prefix operator for any other mode which
evaluates the address.
-the index mode prefix is cascaded with the operand specifier for that
mode to form an aggregate two byte operand specifier.
-the base operand specifier is used to evaluate a base address. A
copy of the contents of the register designated in the index prefix
is multiplied by the size of the operand and added to the base address
to give the final operand address.
176
10
MOVW opcode
5
56
12
Displacement
6
270
Byte register mode(R5)
Word displacement mode(R6)
Displacement
MOVW 56(R5), 270(R7)
Instruction set
o
Integer logic and arithmetic
-along with conventional arithmetic and logical instructions a number
of optimizations are included like clear, test,
increment, decrement. Extended multiply and divide and add
with carry and subtract with carry were provided to support longword precision integer operations.
Floating point instructions
-along with conventional several specialized floating point instructions
were included like extended modulus instruction which multiplies two
floating point operands and stores the integer and fraction parts of
the product in separate result operands.
Address instructions
-move address instruction stores in the result operand the effective
address of the source operand.
-push address optimizations push on the stack the effective address of
the source operand.
Field instruction
-the extract field instruction extracts 0-32 bit field, sign or zero extended
if it is less than 32 bits, and store the result in longword operand.
-compare field instructions compare a field against a longword operand.
Control instructions
-There is a complete set of conditional branches supporting both signed
and unsigned interpretation of various data types. These branches
test the condition codes and take one byte PC relative branch
displacement.
-There are three conditional branch instructions
-first taking one byte PC relative displacement.
-second taking a word PC relative displacement.
-third called jump taking a general operand specification.
-There are a set of branch instructions which branch on the state of single
bit and, depending on the instruction set, clear or leave unchanged
that bit.
Queue instructions
-represented by doubly linked circular list.
-instructions are provided to insert an item into a queue or to remove
an item from the queue.
Character string instructions
-general move character instruction takes five operands specifying
lengths and starting address of the source and destination strings.
-an optimized move character instruction assumes the string length are
equal and takes three operands.
Packed decimal instructions
-A conventional set of arithmetic instructions is provided.
-The arithmetic shift and round instruction provides decimal point
scaling and rounding.
MEMORY MAPPING
-The 4.3GB virtual address space is divided into four regions.
-The first two regions-the program and control regions comprise
the per process virtual address space which is uniquely mapped for
each process.
-The second two regions-the system region and a region reserved for
future use-comprise the system virtual address space which is singly
mapped for all processes.
-The program region contains user programs and data.
-The control region contains operating system data structures specific
to the process.
-The system region contains procedures which are common to all
processes.
1GB
2GB
3GB
4GB
PROGRAM
REGION
CONTROL
REGION
SYSTEM
REGION
RESERVED FOR
FUTURE EXPANSION
VIRTUAL ADDRESS SPACE
VIRTUAL ADDRESS
313029
9 8
0
-------------------------------------VIRTUAL PAGE NUMBER-----------------------------------------------------BYTE WITHIN PAGE-------
PHYSICAL ADDRESS
31 30 29
9 8
0
------------------------------------PAGE FRAME NUMBER---------------------------------------------------------BYTE WITHIN PAGE---------
ACCESS CONTROL
At a given point in time a process is in any of the four access
modes.
Kernel
-Interrupt and exception handling, scheduling, paging,
physical I/O, etc.
Executive
-Logical I/O as provided by RMS.
Supervisor
-The command interpreter.
User
-User procedures and data.
Interrupts and Exceptions
-VAX-11 provides a 31 priority level interrupt system.
-16 levels(16-31) are provided for hardware.
-15 levels(1-15) are provided for software.
-current interrupt priority level (IPL) is stored in PSL.
-interrupts are serviced by routines executing with kernel mode
access control.
Process context switching
-The process context is gathered together in a data structure called a
Process Control Block (PCB).
-while the process is executing, the process context resides in processor registers.
when switching from one process to another the process context from the
previously executing process is saved in its PCB in memory and the process
context for the process to be executed is loaded from it’s PCB in memory.
VAX-11/780 IMPLEMENTATION
-The vax-11/780 system is the first implementation
of the VAX-11 architecture. When executed in
compatibility mode vax-11/780 has a performance
comparable to PDP-11/70.
-The VAX-11/780 system consists of
CPU
-CPU implements the native and compatibility mode instructions
sets, the memory management, and the interrupt and exception
mechanisms.
-CPU includes an 8KB byte write through cache or buffer memory
(reduces the effective memory access time).
-To reduce delays CPU includes a write buffer. The CPU
issues write to buffer and the actual memory write
takes place in parallel with other CPU activity.
-Contains 128 entry address translation buffer which is
cache of recent virtual to physical translations. The buffer is divided
into two 64 entry sections: one for per process region and other for
system region.
-Fourth buffer of CPU is 8-byte instruction buffer. It serves for two
purposes. First, it decomposes the highly variable instruction
format into its basic components and second it also fetches ahead
to reduce delays in obtaining instruction components.
-There is a writable diagnostic control store (WDCS) which is used for
diagnostic purposes, implementation of certain instructions and for future
micro code changes.
SBI (Synchronous Backplane Interconnect)
-The SBI is the primary control and data transfer path in the VAX-11/780
system.
-SBI is a synchronous bus with a cycle time of 200 nsec cycle.
-The data path width of the SBI is 32 bits. i.e during each 200 nsec cycle
either 32 bits of data or a 30 bit physical address is transferred.
-Arbitration of SBI is distributed :each interface to the SBI has a specific
priority and its own bus request line. when interface wishes to use the bus,
it asserts its bus request line. If at the end of 200 nsec cycle there are no
interfaces of higher priority requesting the bus, the interface takes control
of the bus.
Memory subsystem
-The memory subsystem consists of one or two memory controllers
with up to 1 MB of memory on each. The memory is organized in 64 bit
quadwords with an 8-bit ECC which provides single bit error correction and
double bit error detection.
-The memory controllers have buffers which hold up to four memory
requests. These buffers substantially increase the utilization of the SBI and
memory by permitting the pipelining of multiple memory requests.
I/O subsystem
-The I/O subsystem consists of buffered interfaces or adapters between
the SBI and the two types of peripheral buses: Unibus and Massbus.
-The Unibus is a medium speed multiplexor bus which is used as primary
memory as well as peripheral bus .
-Unibus has an 18-bit physical address space and supports byte and word transfers.
-The Massbus is a high speed block transfer bus used primarily for disks and
tapes.
VAX-11/780
Thank You