Download A 40 GHz Sampling Chip for Picosecond Timing

Development of a Picosecond Timing 20 GHz Sampling Chip
Technical Design Report
Argonne National Laboratory, EFI Chicago, Fermilab, University of Hawaii, Orsay (IN2P3, France), Saclay (IRFU, France),
Stanford Linear Accelerator Center
February 9, 2010
Version 1.0.0
INTRODUCTION
The typical resolution for time-of-flight achieved in large detector systems in high energy physics has not
changed in many decades, being on the order of 100 psec [1]. This is set by the characteristic difference in light collection
paths in the system, which in turn is usually set by the transverse size of the detectors, characteristically on the order of
one inch (100 psec). However a system built on the principle of `no light bounces', e.g. Cherenkov radiation directly
illuminating a photo-cathode followed by an photo-electron amplifying system with characteristic dimensions of 10
microns or less, has a characteristic size much smaller, and consequently a much better intrinsic time resolution [2,3,4].
Time-of-flight techniques with resolution of a one to several picoseconds would allow the measurement of the
mass, and hence the quark content, of relativistic particles at high energy colliders, the association of photons with
collision vertices, and the construction of spectrometers with which to study muon cooling without magnetic
spectrometers [5]. There are likely to be applications in other fields as well, such as measuring longitudinal emittances in
accelerators [6], precision time-of-flight in mass spectroscopy in chemistry and geophysics [7], and applications in
medical imaging [8].
In order to take advantage of photo-detectors with intrinsic single photo-electron resolutions of tens of
picoseconds to build large-area time-of-flight systems, one has to solve the problem of collecting signal over distances
large compared to the time resolution while preserving the fast time resolution inherent in the small feature size of the
detectors themselves. Since these applications imply hundreds to tens of thousands of detector channels, the readout
electronics has to be integrated with the photo-detector itself, in order to reduce the physical dimensions and power,
improve readout speed, and provide all-digital data output.
There are a number of techniques to measure the arrival time of very fast electrical pulses [9]. A recent
development is the large-scale implementation of fast analog pulse-sampling onto arrays of storage capacitors using
CMOS at rates greater than 1 GHz, such as has been pioneered by Breton [10] for the LHC experiments, Delagnes [11]
for HESS, Varner for the Anita experiment [12], and Ritt for the Meg experiment [13]. The steady decrease in feature size
and power use now opens the possibility for multi-channel chips able to sample between 10 and 100 GHz, providing both
time and amplitude after processing. Assuming that the signals are recorded over a time interval from before the pulse up
to past the peak of the pulse, with sufficient samples, fast pulse sampling provides the information to get the time of
arrival of the first photo-electrons, the shape of the leading edge, and the amplitude and integrated charge. While other
techniques can give time and amplitude (or charge), fast sampling has the advantage that it collects all the information,
and so can support corrections for pileup, baseline shifts before the pulse, and filtering for noisy or misshapen pulses. In
applications such as using time-of-flight to search for rare slow-moving particles [14], having the complete pulse shape
provides an important check that rare late pulses are consistent with the expected shape.
This proposal represents a collaborative effort to develop a next-generation sampling chip with a sampling rate fast
enough to acquire multiple samples on the leading edge of an ultra-fast photo-detector, such as a Micro-Channel Plate
PhotoMultiplier (MCP) , for which rise-times less than 100 psec have been measured [15]. The rise-time and transit-timespread (TTS) of MCP’s is measured to depend strongly on the size of the pores, being faster for smaller pore size. MCP’s
are commercially available with 10 micron pores and 25 cm2 area; 2-micron and 3-micron MCP’s are available with
1
smaller areas. Recent advances in material sciences may allow much smaller pore size and much larger areas to be
constructed cheaply [17].
The limitation at present for implementation of fast timing capable of resolutions commensurate with this MCP
performance is the cost and performance of available electronics. The best electronics now available consists of individual
units of a single channel of amplifier, constant-fraction-discriminator (CFD) and analog time-to-amplitude converter
(TAC), costing about $10,000/channel, and occupying large amounts of rack space at a distance from the photo-detector
itself. However, even at this cost, the limit in resolution is more than 3 psec [16]. In contrast, a fast multi-channel
sampling chip would sit directly on the back of the optical device, occupy little space, provide sub-psec resolution, be
much more robust, and cost on the order of $10 per channel [17].
There is already a worldwide community of experts in the field [10, 11, 12, 13]. The development of the next generation
takes advantage of the progress in developing smaller-feature CMOS processes; this chip would be in a 130 nm, which
allows the next generation to be smaller, faster, and lower-power than the previous chips which were done in 250 nm or
350 nm (see Table 1). The design represents a consensus opinion based on real-time experience on many of the debatable
details, such as phase-locking the loop, to-reset or not-to-reset, the input analog bandwidth, and others. We see many
applications for such a chip, and consequently would like to join our strengths and resources to make the next generation
available to ourselves and others.
This proposal is organized as follows: Section I presents the optimization of the sampling parameters by simulation. A
comparison is also made of the sampling technique versus the use of a single threshold, multiple thresholds, and the
current CFD. Section II is a survey of the existing sampling chips worldwide. Section III describes the functions and
architecture of the proposed sampling chip. The details of technology are described in Section IV. Section V describes the
building blocks, including the timing generator, the analog storage cells, the triggering discriminators, and the A-to-D
converters. The Input/Output pads are listed in section VII. Section VIII describes the area in silicon and the power
dissipated. Section IX describes the development necessary to be able to test the constructed chip. The system aspects are
described in Section X and Section XI deals with schedule and workload.
We have experience in ASIC design distributed among several institutions [18], and propose that this chip be designed in
a similar fashion, sharing the load among the designers based on their experience and desires.
Figure 1. Raw MCP signals (50 Photo-Electrons). From Matthew Wetstein, ANL
2
I PULSE SAMPLING
Figure 2. Simulated timing resolution as a function of the number of Photo-Electrons for Single Threshold, Multiple
Threshold, Constant Fraction, and Pulse Sampling techniques.
Figure 3. Simulated time resolution (ps) as a function of the sampling rate for 30 (blue) and 100 (red) photo-electrons.
Typical signal to noise has been measured as approximately 80, for a 50 photo-electrons signal [16].
Figure 4. Simulated time resolution as a function of the digitization. MCP rise-time is 100ps
The main parameters for sampling are:
-
The sampling rate,
The effective input analog bandwidth,
The sampling start time and duration,
The sampling accuracy (in amplitude and time),
The dynamic range.
3
Additional environmental constraints are mainly:
3) The data acquisition mode (self-triggered, common stop, channel trigger),
4) The number of channels,
5) The conversion time and readout time
6) Rate capability
7) Power
II CONTEXT
Several circuits have already been designed in the HEP community for fast pulse sampling, mainly to record
photo-multipliers pulse shapes. As detailed in section I, fast timing requires higher sampling rates, but smaller dynamics
ranges.
Hawaii
Sampling frequency
Analog bandwidth
Number of
Channels
Triggered mode
/Orsay/Saclay
Lab 3
20 MHz-3.7
GHz
Planned Blab2
Sam
1-10 GHz
0.7-2.5 GHz
900 MHz
850 MHz
300 MHz
9
Common Stop
Resolution
Samples
Clock
256
33 MHz
PSI
Planne
d
16
10 GHz
650
MHz
2
10 MHz-5 GHz
5 GHz
10 GHz
450 MHz
> DRS3
>1 GHz
12/6/2/1
8/4/2/1
4
Common Stop
Common Stop
Common Stop
Channel
trigger
10 bit
11.6 bit
11.6 bit
11.5 bit
8-10 bit
1024-12288
1024-8192
20 MHz
fsamp/2048
40 MHz
No
No
Yes
Yes
Yes
Pseudo diff
4/8 rows of 512
33 MHz
256
2048
66 MHz
5ms
TIA (5kOhm gain)
Yes
256
0.6 ms
No
Differential inputs
No
Pseudo-diff
Yes
Input impedance
50 Ohms Ext
30-70Ohms adjustable
> 10 MOhm
1 GHz Wilkinson
16 MHz
Readout clock
Planned DRS4
Channel trigger on
sums
Max latency
Input Buffers
DRS3
PSEC
This
proposal
7-11pF
Readout time
150s
s
< 2s
33 MHz
30ns *
n_samples
Locked delays
Ext DAC
Ext DLL
Int DLL
Ext PLL
Int PLL
On-chip ADC
Yes
1 GHz Wilkinson
No
No
No
Yes
No
No
Yes
No
50mW
Yes
20mW/sample
0.2W/read
150 mW
1-13mW
2-20mW
1mV/1V
0.65mV-2V
0.35mV/1.1V
0.35/1V
<0.5%
R/W simultaneous
Power/ch
Dynamic range
Xtalk
Average
<<10%
Sampling jitter
Power supplies
2.5V
< 0.1%
0.30%
40 MHz
< 25.6 s
1V
TBD
40ps
<0.5%
200ps (Ext
PLL)
Ext PLL
10ps
2.5V
0-3.3V
2.5V
2.5 V
1.8V
UMC 0.25
UMC 0.25
CMOS 0.13
25 mm2
25 mm2
1 mm2
Process
TSMC 0.25
TSMC 0.25
AMS 0.35
Chip area
2.5 mm2
12 mm2
10 mm2
500$/40 10$/2k
15.7$/12k
Cost/channel
33 MHz
30ns *
n_samples
AMS
0.18
10-15$
Table 1. State of the art, this proposal. The yellow column is from Gary Varner’s group at the University of Hawaii
(USA) [12], the light blue from Dominique Breton from the University of Paris-Sud (Orsay) [10] and Eric Delagnes from
CEA (Saclay), (France) [11]. The orange column from Stefan Ritt at PSI (Switzerland) [13]. The dark blue is this
proposal.
A first prototype in CMOS 130nm technology has already been submitted and tested.
4
See http://clrwww.in2p3.fr/www2008/WTDMPPA/
III FUNCTIONAL DESCRIPTION AND MAIN SPECIFICATIONS (Chip version 2).
In practice, a timing generator implemented in CMOS technology, locked on a 40 MHz-80MHz clock, provides
50-100 ps controls equally spaced in time to a set of 256 analog storage elements for a total duration of the order of 12.525 nanoseconds, long enough to measure with sufficient resolution the pedestal, the rising edge, up to pulses values
beyond the peaking time, from any input pulse to be acquired. The sign of the analog input can also be selected. The
timing generator feeds four independent channels (Figure 6).
The timing generator is phase locked on the sampling clock using the outputs of an internal phase comparator
feeding an external charge pump which takes controls of the delay elements, as a delay locked loop (DLL).
The 256-deep sampling cells bank switches the analog input voltage to 60 fF capacitors which are buffered out to
comparators of a set of Wilkinson ADCs digitizing in parallel all 256 stored samples of a channel, in order to reduce the
dead time. As an example, four 12-bit Wilkinson ADCs clocked from internal ring oscillators at 2 GHz, would digitize the
full chip in 2 s. There will be one ring oscillator per analog channel.
There are two modes of operations, Self-triggered or External triggered modes. In a “Self-triggered mode”,
digitization takes place if one at least of the input channels detects a signal that exceeds a given threshold. In the external
Trigger mode, the external Trigger input stops the sampling process and freeze the voltages stored in the capacitor banks.
Data can be read 2 s after, when Analog to Digital conversions have been completed. Trigger outputs are available in the
self-trigger mode.
The first trigger signal starts the digitization of all channels. Data can be read 2 s afterwards. More precisely, the
sampling process runs continuously as an analog shift register, stopped on receipt of a response from a triggering
discriminator, or an external trigger input, after an appropriate delay.
This delay can be tuned from the outside allowing recording several samples of the pedestal before the triggering
instant.
A sliding window (sampling window) controls the write process to the storage capacitors. A width of eight
samples is predicted to be optimum by the simulations, and has been implemented in the first channel. The three other
channels receive a tunable sampling window whose width can be set from an external analog voltage.
The readout is achieved using a token passing mechanism. Each bank can be addressed separately, and read by
sections of 64 elements (this allows avoiding reading large amounts of pedestals, if the event time is approximately
known, using the distance in time between the trigger and the output of the timing generator, for instance)
A comparator test structure is implemented since this block has been significantly modified wrt the last design.
Therefore, the foreseen sampling architecture comprises (Figures 5):
-
The sampling timing generator, sampling windows generation and fan-outs,
The storage elements,
The Wilkinson A/D converters and associated clocks and counters,
The readout control,
A comparator test structure.
An access to an internal analog output bus allowing observing the sampling cells outputs.
5
Figure 5a. Block diagram of one analog sampling channel and timing generator.
Figure 5b. Full block diagram. The timing generator is shared by all channels. There are two tokens, one
for two input channels, the other for two input channels and sampling window channel. The tokens address one
6
channel at a time, selected by three address bits. There are two sampling windows, one of fixed duration (8
delay cells) feeding one analog channel, and a variable duration one (400ps-1.6ns) feeding the other channels.
The main specifications are sketched in Table I
Channels
Depth
Sampling rate
Analog Bandwidth
Self or External trigger
4 + 1 (sampling window)
256
10-20GS/s
> 1.5GHz
One internally delayed self trigger/channel, or common external
trigger
1.0V
Variable on three channels, 400ps-1.6ns, fixed (8 x 100ps delay
cells) on one channel.
10ps
1%
Internal phase comparator, external LP filter
50external
Adjustable 1-2 GHz internal ring oscillator. Minimum conversion
time 2us. One ring oscillator/channel
40 MHz. Readout time (4-channel) 4 x 256 x 25ns=25.6 s
Readout Time can be reduced reading blocks of 64 cells only at
one time, state of the timing generator recorded at the trigger time)
40mW/channel
1.2V
IBM 8RF-DM (130nm CMOS)
Dynamic range
Sampling window
Sampling jitter
Crosstalk
DLL Timing generator
DC Input impedance
Conversion clock
Read clock
Power
Power supply
Process
Table 1. Main minimum specifications.
IV
TECHNOLOGY
Silicon CMOS Technology
A 130nm CMOS technology available from the Multi Project Wafer MOSIS facility (4676 Admiralty Way,
Marina del Rey, CA 90292), is well-suited to a fast implementation of the sampler chip. The availability of CMOS RF
transistors together with passive components allows implementing efficiently fast linear storage devices, as well as the
timing generation, analog-to-digital converters, and the digital readout control. From the supply voltage of 1.2V, it has
been possible to design a sampling cell able to store voltage levels with a dynamic range of 1V.
7
V BUILDING BLOCKS
V-1 The timing generator
Gate propagation delays of the order of 100 ps used as delay elements locked externally on an internal reference
clock running at 40-80 MHz.
The process spreads of these delays has been measured to be substantially less than one pico-second [21] in
CMOS technologies. This low spread will ensure a reproducible and reliable performance for such a timing generator
locked on the main clock.
These delays will be controlled by a Delay Lock Loop whose phase comparators will be integrated on-chip, and
low-pass filtered by an external RC filter.
The layout of this DLL and the sampling windows and fan-outs to the storage elements is critical. However, a
sampling jitter (noise or fixed pattern) can be tolerated at a 20 GHz sampling rate (Figure 7).
Figure 6. Timing generator and sampling cells
Figure 7. Simulation of the timing resolution as a function of the sampling jitter for 30 and 100 Photo-electrons
at 20 GHz sampling.
These delayed clock signals have to be dispatched through the chip to the storage cells. In the envisaged layout,
the timing generator sits at the center, and dispatches signals up and down to two sets of two analog RF channels (Figure
8.). A fifth test channel receives the sampling window.
8
Figure 8. Overall 4-channel version 2 chip layout. 4 x 4 mm2
9
V-2 The Analog storage cells
A bank of capacitors of values trading-off bandwidth and kT/C timed by the timing generator store successive
values of the input signals. A value of 60fF is compatible with the required resolution, allowing an ideal input bandwidth
much larger than 1.5 GHz ( 3 GHz simulated after layout). For this value, √kT/C= 260 V which is one LSB of the 12-bit
ADC. The structure of the sampling cell is depicted in Figure 9.
Figure 9. The analog Sampling cell.
V-3 The Triggering discriminators
The input signals are sampled continuously. Whenever an input level exceeds a given (programmable) threshold,
the corresponding channel is stopped after a delay. This delay allows recording a given duration of the pulse shape. To
take into account the walk (slope dependent) spreads of the triggering discriminator, a sufficient number of storage cells is
foreseen, 256 cells leading to a total recording duration of 25.6ns at a 10 GHz sampling rate.
The delay is programmable between 10 and 25ns. Input discriminator outputs are available on four output pads, as
well as one delayed output. An input analog pad controls the value of the delay. The total delay can be tuned between 5
and 15ns.
10
V-4 The Analog to Digital converters
As part of the sampling cell, the analog-to-digital converter digitizes the sampler channels containing relevant
data after the sampling process has been stopped by a triggering discriminator. According to simulations (Figure 4), a 810 bit Wilkinson ADC appears to have a sufficient precision for that particular task, and seems the most efficient
architecture where a high level of parallelism is required. A Wilkinson ADC converter running 12 bits at 2GHz converts
256 samples in 4096 x 500 ps = 2.048 s, which is faster and smaller than any successive approximation or pipelined
converter, for the same power dissipation. In addition, one single calibration is required (if needed).
As implemented in the Labrador chip [12], each sampling cell can integrate a comparator used to digitize the
stored charge, all cells using the same (buffered) ramping signal, so that only one single calibration is required.
VI OPERATION MODES
Modes
Write
Writes continuously samples of inputs in a capacitor arrays at 10 GS/s for 25.6s.
Sampling stopped upon trigger.
Clears 2 GHz counter, ramps up Wilkinson ADCs for 2 s.
Convert
Read
Sequences 256 counters of the channel selected by AD0-3 onto the data
bus. Four selectable blocks of 64 cells can be read for each channel at 40 MHz clock rate.
VII I/Os
Table 2 shows the detailed I/Os. (changes wrt ver1)
Signal Name #
Type
Sampling cells
9
Biasl<0-3>
RF<0-3>
ANALOG_out
aI
aI
aI/0
Triggers
15
TRIG_mode
I/O Pad
Function
y
y
y
Input returns
Analog inputs 0-1V, external 50 to returns
Test analog output bus for one channel - to observe output
of sampling cell/buffer. Output to be controlled by token. Also
could be used to input DC level to comparators
dI
y
TRIG_ext
dI
y
TRIGout<0-3>
dO
y
LOW: use internal input discriminators to stop the sampling
process; HIGH: use Trigger_EXT input.
External Trigger input when Self-External = External. High:
sample, Enables the sampling windows closing the sampling
switches. Operates on all 5 channels.
Low: hold, stops the recording process. All sampling switches
open.
Internal trigger outputs
11
TRIGdelay_out
TRIGdelay_cntrl
dO
aI
y
y
TRIGthres<0-3>
TRIG_bias
TRIG_sign
ANALOGout_sel
aI
aI
dI
dI
y
y
y
y
Delayed trigger
Trigger Delay Control between (5 to 15ns in total including the
discriminator response)
Trigger thresholds
Common- trigger discriminator bias current/voltage
Common - sign indicates + or - pulses
Selects the analog output bus onto the ANALOG_out bus
Timing generator
8
MClk
VCN
VCP
VswN
VswP
VDLout
SWfixed_obsv
SWvar_obsv
dI
aI
aI
aI
aI
dO
dO
dO
y
y
y
y
y
y
y
y
Write clock (40 MHz to timing generator)
Timing cell control (falling)
(rising)
Sampling window rising edge control (instant)
falling edge control (duration)
Timing generator output for delay lock
Fixed sampling window output
Variable sampling window output
ADC control
9
CEXT
RAMPbuffer_out
RAMPbias
RAMP
aIO y
dO y
aI
y
dI
y
V2GN
V2GP
CLEARglob1
aI
aI
dI
y
y
y
CLEARglob2
dI
y
chanROmonitor
dO
y
Read control
27
RdClk1
RdClk2
Rd<0-4>
TOKin1
TOKin2
TOKout1
TOKout2
CHAN_select0
CHAN_select1
CHAN5_sel
TOKblock_select0
TOKblock_select1
dI
dI
dI
dI
dI
dO
dO
dI
dI
dI
dI
dI
y
y
y
y
y
y
y
y
y
y
y
y
External capacitor, external ramp input or internal ramp output
Observe the output of the ramp buffer
Ramp bias
Ramp (Ramp) active low, high clears the ramp cap and the ADC’s
counters.
Controls 2G counter ring oscillator (falling)
(rising)
Clears the ADC counters 1, resets the sampling
capacitor, clears the ramp
Clears the ADC counter 2, resets the sampling
capacitor, clears the ramp
Monitors the channel ring oscillators
Read clock 1 (40 MHz)
Read clock 2 (40 MHz)
Controls the read switches.
Input of the token 1 passing
Input of the token 2 passing
Output of the token 1 passing
Output of the token 2 passing
Channel address 0, selects the channel to be read (0-3)
Channel address 1, selects the channel to be read (0-3)
Channel address 1, selects the channel to be read (4)
Token block select 0
Token select select 1
12
D0-11
dI
Power supplies
46
probe_powclamp
avdd
agnd
dvdd
dgnd
aIO
Tests and monitoring
y
12-bit data bus controlled by the token and rd<0-3>.
RC clamp (external)
+1.2V
0V
+1.2V
0V
6
Comparator
testComp_n
testComp_p
testComp_out
aI
aI
aO
y
y
y
Test comparator input Test comparator input +
Test comparator output
dO
y
Monitors RO/4096 frequency output
aI
aI
y
y
Test resistor input0
Test resistor input1
Ring Oscillator monitor
chanROmonitor
Resistor tests
Resistor_test_0
Resistor_test_1
Chip:
74
23
23
Total:
I/Os
Gnd
Vdd
120 pads
Package CQFP120A
4.32 x 4.32 mm2 are foreseen with 120 I/O pads as described above. 30 bare dies + 10 x CQFP 120A
packaged chips ordered to MOSIS. I/O pads pitch is 135 m.
ESD protections
The ESD protections envisaged trade off the protection efficiency and the bandwidth degradation.
Double diodes (double_diode_n from the esd8rf library in the IBM design kit) should be adequate, as well as
RC_clamp for Vdd to Gnd protection.
13
IX Power
Assuming 50 fF storage capacitors and a maximum amplitude of 1 V, the charge storage would dissipate: 16
channels x 50 fF x 1V x 1V x 1/50 ps = 15 mW.
Other contributions from free running digital activity, input discriminators and internal buffers steady power
dissipation, have to be evaluated, and will likely dominate.
TESTS
A dedicated card similar to the one used to evaluate the version 1 (including the sampling chip and the
control FPGA) will be developed.
X SYSTEM ASPECTS
In order to use the sampling chip in various environments, the external constraints for the applications in view that
have been mentioned in the introduction will be reviewed. The sampling process, the analog and digital storages, the
digitization processes and the readout schemes foreseen (self-triggered, external triggered) together with their detailed
on-chip implementations should match the properties of the signals from the fast detectors to be used (shape, duration,
signal to noise ratio, reproducibility), the timing of the experiment or device (recurrent or random events, cycling period if
any, data taking time, idle time), and the channel occupancy as well as event rates. In particular, the sampling rate, the
analog storage hold time, the conversion time, the data buffering and IO capabilities have to match the experimental
context.
A companion FPGA driver integrating the digital hardware requiring some flexibility and that would not be
integrated on-chip, such as the digital signal processing extracting the time and the amplitude, the data formatting,
management of the off-chip storage, can be specified. An application-dependent sequencer including the trigger
management could also be implemented in this FPGA.
XI SCHEDULE AND WORKLOAD
XI-1 Prototyping
The design of the first prototype has taken six months of two full-time engineers (FTE). The chip manufacturing
and the test design took two months of two FTE’s, and the tests themselves three other months of the same people, the
fully characterized prototype is still not available after nine months.
XI-2 Second version
Starting after the prototype tests, the design of the second version will take six months of two full-time engineers.
Manufacturing and the design of the test card and related electronics will take three other months of two FTEs, and the
tests themselves four other months. Detector tests take four months of one FTE.
REFERENCES
[1] https://hepblog.uchicago.edu/cdf/cdf2/
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14
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Nucl. Instr. Meth. A560 (2006) 303-308.
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SAM : A new GHz sampling ASIC for the HESS-II Front-End. Cerenkov 2005.
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[13] S. Ritt.
Design and Performance of the 5 GHz Waveform Digitizer Chip DRS3.
Submitted to IEEE Transactions on Nuclear Science. November 2007.
[14] Rare slow-moving particles
[15] Rise-times less than 100 psec Photek ?
[16] J. Va’Vra. Private communication.
[17] Sampler chip @10 $
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The FEI3 readout chip for the ATLAS pixel detector. Nuclear Instruments and Methods A.Vol 565, p178, 2006.
[19] Argonne Test stand
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