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CITS2002SystemsProgramming 1 next→ CITS2002 CITS2002schedule ComplexityofI/ODevices Modernoperatingsystemsareexpectedtosupportawidevarietyofdifferentinputandoutput(I/O)devices. However,thevarietyofthesedevicesmakestheirconsistent,logical,andefficientsupportdifficult.Inparticular,theI/Otransferratesandsizesareofmost concernforefficientoperationofanoperatingsystem. ThetypesofI/Odevicessupportedcanbegroupedroughlyintothreedistinctcategories: Humaninterfacedevices communicatewiththeuser,includingkeyboard(10Bps),mouse(50Bps),laserprinter(4MBps),andvideodisplays(150MBps). Machine-readabledevices communicatewithinthesinglecomputersystem,orprovidedigitalinputfromexternalsensors,includingdigital-analogueconverters(100KBps),floppy disks(10KBps),magneto-opticaldisks(1MBps),magnetictape(5MBps),magneticdisk(150MBps),solid-statedisk(600MBps). Communicationdevices connectcomputersystemstoeachother,includingmodems(7KBps),standardEthernet(1.25MBps,12.5MBps),ATMnetworks(19.375MBpandvery fastEthernet(125MBps). Note,thatthe(approximate)I/OtransferspeedsshownabovearepresentedinmultiplesofBytes-per-second(Bps). ManyI/Odevices,typicallycommunications/networkingdevices,reporttheirtransferspeedsinbits-per-second(bps).Moreover,communicationspeeds aregiveninmultiplesof1000bps,not1024bps,sothattransferringonemegabyteofdataat1Mbpsmaytake2.4%longerthanyou'dthink! CITS2002SystemsProgramming,Lecture23,p1,27thOctober2016. CITS2002SystemsProgramming ←prev 2 next→ CITS2002 CITS2002schedule ComplexityofI/ODevices,continued ThediversityofusestowhichI/Odevicesareplacedmakesitdifficultforanoperatingsystemtomakea(single)uniformandconsistentapproachtotheir management. Wecanhighlightmanyofthesedifferences: Datarate: ourpreviousexampleshavehighlightedtransferratesspanning7-8ordersofmagnitude. Application: theexpecteduseofadeviceaffectsthesoftwarepoliciesandprioritiesemployedbyanoperatingsystem.Forexample,differentoutputdevicesmay besupportedatdifferentpriorities(particularlyinareal-time,alert-basedsystem)andotherwiseidenticaldiskdrivesmaybemanageddifferentlyifone istheswappingdevice,andtheother"only"storesusers'files. Complexityofcontrol: devicessuchasmiceandkeyboardsrequirelittlecontrol(beingread-onlydevices),whereasbidirectional,mirroreddiskdrivesaremuchmore complex. Datatransfermodels: typicallycharacterstream-based(keyboards),orblock-based(disksandtapes). Errormanagement: complexI/Odevicesoftenrecoverfromtheirownerrors,andtheoperatingsystemonlyhearsofcatastrophicfailures.Inaddition,someerrorsmaybe handledbytheoperatingsystem,whereasothersmust"percolate"totheuser'sapplication. TheauthorStallingsdescribesI/Omanagementasthe"messiestaspectofoperatingsystemdesign". CITS2002SystemsProgramming,Lecture23,p2,27thOctober2016. CITS2002SystemsProgramming ←prev 3 next→ CITS2002 CITS2002schedule TypesofI/OFunctions AnoperatingsystemmaybeexpectedtosupportI/Ousingoneofthreemethods. WhichmethodisemployeddependsonthecomplexityoftheI/Odevice: Programmed,orpolled,I/O TheprocessorissuesanI/O-basedinstructiononbehalfofthecurrentlyexecutingprocess.TheprocessloopsincessantlyuntiltheI/Orequestis satisfied.Ofcourse,inamulti-programmedenvironment,allotherprocessesaredelayed,too. Thistechniqueisoftentermedbusy-waiting. Interrupt-drivenI/O TheprocessoragainissuesanI/O-basedinstructiononbehalfofthecurrentlyexecutingprocess. Theprocesseithercontinuesexecutionuntil: itis(asynchronously)informedthattheI/Ohascompleted(termedasynchronousI/O),or theprocessisblocked(anotherprocessmayexecute)andtheoriginalprocessiseventuallymarkedasReadywhentheoperatingsystem receivestheappropriate"I/Odone"hardwareinterrupt. DirectMemoryAccess(DMA) TheprocessorissuesanI/O-basedinstructiononbehalfofthecurrentlyexecutingprocess,butdirectstherequesttoaDMA(hardware)module.The DMAmodulemanagesthedatatransferbetweenmainmemoryandtheI/Odevicewithoutprocessorintervention. Whenthewholedatablockhasbeentransfered,theDMAmoduleinterruptstheprocessor(asdescribedabove). CITS2002SystemsProgramming,Lecture23,p3,27thOctober2016. CITS2002SystemsProgramming ←prev 4 next→ CITS2002 CITS2002schedule ResponsibilitiesofanI/OController Ascomputerhardwareandoperatingsystemshaveevolved,themethodsemployedtomanageI/Ohaveincreasedincomplexity. Theseevolutionarystepshavebeen: 1. theprocessordirectlycontrolstheI/Odevice. 2. anI/Ocontrollerormoduleisemployed.TheprocessorcommunicateswiththiscontrollerusingprogrammedI/O(nointerrupts),butisunawareofthe device'sexternalinterface. 3. anI/Ocontrollerisagainused,butefficiencyisincreasedbecausethecontrollerinterruptstheprocessorwhenready. 4. theI/OcontrollercommunicateswiththeDMAmodule,relinquishingtheprocessorofallI/Oresponsibilities. 5. theI/OcontrollersupportsitsownprocessorandI/Oinstructionset.ThemainprocessorinitiatesI/Obyprovidingthecontrollerwiththeaddressofa sequenceofI/Oinstructionsinmainmemory.WhentheI/Ochannelhasfetchedandexecutedthissequence,itinterruptsthemainprocessor. 6. theI/Ocontrollersupportsitsownprocessorandlocalmemory.TheI/Ocontrollerisnowdirectedfromthemainprocessorbysimplyprovidinga descriptionoftheI/Otaskrequired.WhenthisI/Oprocessorhasperformeditstask,itinterruptsthemainprocessor. Inthisevolutionarysequence,theI/Ocontrollerbecomesincreasingly"intelligent",andthemainprocessorisincreasinglyrelievedofanyI/O responsibilities,leavingittoperformothercomputations. CITS2002SystemsProgramming,Lecture23,p4,27thOctober2016. CITS2002SystemsProgramming ←prev 5 next→ CITS2002 CITS2002schedule DirectMemoryAccess TheDirectMemoryAccess(DMA)controllerhastheresponsibilityoftransferringblocksofdatabetweenmainmemoryandanyI/Odevices,without involvingtheprocessor.Typically,datasizesarelarge-tens,hundredsofkilobytes,ormegabytes. TheDMAmoduleusesthemainbustoperformthetransfer.Ideallythisusewillbewhentheprocessordoesnotrequirethebus,otherwisetheDMA modulemustsuspendtheprocessor'sexecution. Thelattertechniqueisoftentermedcycle-stealingastheDMAmodule'sactionsstealaprocessorcycle. DMAandInterruptBreakpoints Ascanbeseen,theprocessordoesnotneedtousethebusallofthetime(andcertainlynotfordatastoredentirelyinitsregisters).Thisprovides opportunitiesfortheDMAcontrollertotransferdatausingthebuswhenitisotherwiseidle. TheDMAmoduleisabletosuspendtheprocessorduringitsinstructionfetch-decode-executecycle.DuringtheDMAbreakpoints,theDMAmodule suspendstheprocessorandtransfersasingleunit(typicallyonlyonebyte)betweenmemoryandanI/Omodule. NoticethattheDMAmoduledoesnotinterrupttheprocessor,itjustsuspendsit.Thereisnoneedfortheprocessortosaveitsexecutioncontextand executeanotherroutine,astheDMAmoduledoesnotalterthiscontext.Theprocessorrunsslowerduetoitssuspension,butnotasslowasifitwere interruptedatthecompletionofeachbyte'stransferorifpollingwerebeingused. CITS2002SystemsProgramming,Lecture23,p5,27thOctober2016. CITS2002SystemsProgramming ←prev 6 next→ CITS2002 CITS2002schedule DirectMemoryAccessOrganisation Atthehardwarelevel,themainprocessor,DMAmodule,andotherI/Omodulesmaybeconfiguredindifferentways: InFigure(a),DMAmodulesareseparatedevices,onthesamebusastheprocessorandI/Omodules. InFigure(b),moresophisticated(faster)deviceshavetheirownDMAcontroller,orasingleDMAcontroller(here,oftentermedanI/Ochannel)may directlysupportmultipledevices. CITS2002SystemsProgramming,Lecture23,p6,27thOctober2016. CITS2002SystemsProgramming ←prev 7 next→ CITS2002 CITS2002schedule DirectMemoryAccessOrganisation,continued InFigure(c),theDMAmoduleactsasanI/ObridgebetweenthemainsystembusandanewI/Obus. ItmaynowbepossibleforasinglesystemtohaveavarietyofdifferentI/Obusstandards,suchas: IDE(IntegratedDriveElectronics)orSCSI(SmallComputerSystemInterface)fordiskdrives, aUSBv3.0bus(UniversalSerialBus,600MBps)forexternaldrivesandscanners,and aFirewirebus(IEEE1394,50MBps)fordigitalmultimedia. ThisdecreasesthenumberofdirectinterfacesthattheDMAmodulemustsupport,andremoveshalfofthemainbustrafficwhichcanpotentiallyinterfere withtheprocessor'sexecution. Moreover,somedevicesmaynowonlybecontactedviatheirDMA(now,bus)controller. CITS2002SystemsProgramming,Lecture23,p7,27thOctober2016. CITS2002SystemsProgramming ←prev 8 next→ CITS2002 CITS2002schedule LogicalOrganisationofI/O Aswithmostaspectsofoperatingsystemdesign,ahierarchicalstructurecanbeemployedtodecomposeI/Oresponsibilitiesintomanageable subproblems. AtthelowestleveloftheI/Ohierarchyaresectionsofcodewhichmustinteractdirectlywithhardware,andcompletetheiractivitiesinafewbillionthsofa second. Atthehighestlevel,applicationprogramswishtocommunicatetheirI/Orequirementsatamorelogicallevel,andwishtobeisolatedfromhardware specifics.Weseethesemore"logical"interfacesrepresentedinaconsistent,smallsetofsystemcalls. Therearethreedistinctlevelsinthishierarchy: LogicalI/O: treatstheI/Odeviceasalogicalresource,whileignoringthecontrolofthedevice.Operatingsysteminterfaces(systemcalls)allowapplication programstointeractwiththisresponsibilitywithfamiliaroperationssuchasopen(),lseek(),read(),write(),andclose(). DeviceI/O: therequiredI/Ooperationsandthedata'slocationareconvertedtosequencesofinstructionsandaccesses. Schedulingandcontrol: theoperatingsystemschedulestheI/Orequestsinanattempttomaximisetheirthroughput(basedontheI/Odevice'scharacteristics)."Returning" interruptsarealsohandledatthislevel,withcontrolinformation(status)beingreturnedtotheinvokingprocesses. CITS2002SystemsProgramming,Lecture23,p8,27thOctober2016. CITS2002SystemsProgramming ←prev 9 CITS2002 CITS2002schedule ExamplesofLogicalI/OOrganisation Howmuchoperatingsystemcodeis"squeezed"aboveDeviceI/Odependsmostlyonhowthedeviceisrepresentedtoanapplication(Stalling'sFigure 11.4). Forexample,thecommunicationsport'scodemayincludeafullTCP/IPprotocolsuite,requiringtensofthousandsoflinesofcode. AModelofI/OOrganization CITS2002SystemsProgramming,Lecture23,p9,27thOctober2016.