Download Operating Systems Hardware Support

CSE 3430
Overview of Computer Systems for Non-Mayors
Operating Systems Hardware
Support
Presentation K
Gojko Babić
Read/Study: Bryant 8.1
03-29-2017
Computer System Components
1. Hardware – provides basic computing resources (CPU,
memory, I/O devices).
2. Operating system – controls and coordinates the use of
the hardware among the various application programs for
the various users.
3. Applications programs – define the ways in which the
system resources are used to solve the computing
problems of the users (compilers, database systems,
video games, business programs).
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Abstract View of Computer Components
Thus, an operating system is the software layer between
the hardware and the user programs.
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Computer Architecture (again)
• A modern meaning of the term computer architecture covers
three aspects of computer design:
– instruction set architecture,
– computer organization and
– computer hardware.
• Instruction set architecture - ISA refers to the programmer
visible machine interface such as instruction set, data
representation (integers, real, characters, etc.), registers,
memory organization and exception (i.e. interrupt) handling.
One can think of an ISA of a particular computer as a
hardware functionality of that computer.
• Instruction set architecture - ISA is of particular importance
to an operating system.
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Basic (Single CPU) Computer Structure
• CPU and device controllers connect through common bus
providing access to shared memory
• Symmetric multiprocessor (SMP) architecture has several CPU’s
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I/O Computer System Operation
• I/O controllers (devices) and the CPU can execute concurrently.
• Each device controller is in charge of a particular device and a
device controller normally has a small local buffer.
• I/O is transfer from the device to local buffer of controller.
• For device controllers without DMA, CPU moves data from/to
main memory to/from local buffers. Device controller informs
CPU that it has finished (i.e. received data or sent data) its
operation by causing an I/O interrupt (usually per each byte).
• DMA (Direct Memory Access) is used for high-speed I/O
devices able to transmit information at close to memory speeds.
DMA device controller transfers blocks of data from/to local
buffer directly to/from main memory without CPU intervention.
With DMA, only one interrupt is generated per block, rather
than the one interrupt per byte.
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Moving-Head Disk Mechanism
• A sector (usually 512 bytes) is a basic unit of transfer (read/write)
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Reading a Disc Sector
Processor chip
Register file
Prog. Counter
ALU
Instr. Register
• CPU (executing code) initiates a disk
read by writing a read command, logical
sector (block) number, and destination
memory address to a port (registers)
associated with disk controller.
Main
memory
Bus interface
I/O bus
USB
controller
mouse Keyboard
Graphics
adapter
Disk
controller
Monitor
Disk
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Reading a Disc Sector (cont.)
Processor chip
• Disk controller reads the sector and performs
a direct memory access (DMA) transfer into
main memory.
• Note that CPU has to execute some
instructions, while disc controller is reading.
Register file
Prog. Counter
ALU
Instr. Register
Main
memory
Bus interface
I/O bus
USB
controller
Graphics
adapter
Mouse Keyboard
Monitor
Disk
controller
Disk
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Reading a Disc Sector (cont.)
Processor chip
Register file
Prog. Counter
ALU
Instr. Register
• When the DMA transfer completes, the disk
controller notifies the CPU with an interrupt,
asserting a special “interrupt” pin on the CPU
• An interrupt normally causes that CPU ceases
executing its current code, and starts executing
some other code. But how is that done????
Main
memory
Bus interface
I/O bus
USB
controller
Graphics
adapter
Mouse Keyboard
Monitor
Disk
controller
Disk
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What is an Operating System?
• Operating system is a program that acts as an intermediary
between a user of a computer and the computer hardware.
• Operating system goals:
– make solving user problems easier, i.e. make the computer
system convenient to use
– use of the computer hardware in an efficient manner.
• O.S. implements a set of system calls that provide a
convenient mean for requesting operating system services.
– Example: file system & its system calls and disk structure.
• Operating system manages the hardware resources such as:
– processor (CPU),
– main memory (RAM),
– I/O controllers,
– disk storage, etc.
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Modes of CPU Operation
• There are two modes of CPU operations:
– kernel mode and
– user mode.
• Privileged instructions can be executed only in the kernel
mode. Examples of privileged instructions: I/O instructions,
instructions that access system registers such as memory
mapping registers, etc.
• In principle, computer systems function such that the
operating system is executed with CPU in a kernel mode,
while user programs execute with CPU in user mode.
– Why?
– How?
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Layered Approach
System
calls
Operating System
(CPU in kernel mode)
User Programs
(CPU in user mode)
Privileged
instructions
Hardware
Nonprivileged
instructions
System calls (or monitor calls) are means by which user programs
require services of operating system.
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Dual-Mode of CPU Operation
• CPU mode bit added to computer hardware to indicate the
current CPU mode: 0 (=kernel) or 1 (=user).
• When an interrupt occurs, CPU hardware switches to the
kernel mode.
• Switching to user mode (from kernel mode) done by setting
CPU mode bit (by an instruction).
Exception/Interrupt/Fault
kernel
user
Set user mode
Privileged instructions can be executed only in kernel mode.
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Interrupts Classes
There are three classes of causes for an interrupt.
Other classifications can be also made.
1. Interrupts caused by hardware failure:
• Power failure
• Memory parity error
2. Interrupts caused by external signals:
• Reset: A signal asserted on the appropriate pin;
• Hardware Interrupts: Interrupt requests made via asserting
signal on any of special CPU chip pins.
• Interrupt request lines – IRQ’s.
• Usually used by I/O controllers to signal normal I/O completion
or a variety of error conditions.
• These interrupts also called I/O interrupts.
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Interrupts by External Signals
IRQ 1
Reset
IRQ 0
Timer
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Interrupts Classes (continued)
 3. Interrupts as result of instruction execution (these are also called
exceptions); There are two types of those interrupts:
Type A caused by problems during instruction execution:
– Address Error: a reference to a nonexistent or illegal memory
address;
– Reserved Instruction: An instruction with undefined opcode field or
a privileged instruction in User mode;
– Integer Overflow: An integer instruction results in a 2’s
complement overflow;
– Floating Point Error: e.g. divide by zero, overflow, and underflow;
Type B caused by special instructions (software interrupts):
– MIPS processors: Syscall instruction executed;
– Intel processors: INT n instruction executed;
Note: These instructions are used to implement system calls.
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MIPS CPU Modes and Address Spaces
MIPS has two processor modes of operation:
• Kernel Mode and
• User Mode
The processor is in Kernel Mode when CPU mode bit in Status
register is set to zero. The processor enters Kernel Mode at
power-up, or as result of an interrupt.
The processor leaves Kernel Mode and enters User Mode
when CPU mode bit is set to one (by some instruction).
Memory (logical) address space is divided in two ranges:
• User address space
– addresses in the range [0 – 7FFFFFFF16]
• Kernel address space
– addresses in the range [8000000016 – FFFFFFFF16]
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MIPS Privilege Instructions
With CPU in User Mode, the program in execution has access
only to the CPU and FPU registers, while when CPU operates
in Kernel Mode, the program has access to the full capabilities
of processor including CP0 registers.
Again, privileged instructions can not be executed when the
processor is in User mode, i.e. they can be executed only when
the processor is in Kernel mode.
Examples of MIPS privileged instructions:
• any instruction that accesses Kernel address space
• all instructions that access any of CP0 registers, e.g. MFC0,
MTC0 and ERET (but SYSCALL is not)
• any instruction that accesses registers (a port) of I/O
controllers (i.e. I/O instruction).
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MIPS Interrupt Processing
• When any of the interrupts previously listed occurs, hardware
should perform some predefined (by its ISA) tasks.
• Here we describe in some level of details how MIPS processor
processes interrupts.
• MIPS does hardware interrupt processing in three steps.
Step 1. (Saving content of PC)
• EPC register gets a value equal to either:
– the address of a faulty instruction if the instruction itself
caused problems (e.g. address error, reserved instruction) or
hardware malfunctioning detected (e.g. memory parity error),
– the address of the next instructions which would have been
executed in all other cases, i.e. for interrupts caused by
external signals or by those interrupt causing instructions.
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MIPS Interrupt Processing (continued)
Step 2. (PC gets new value and interrupt cause code is saved)
• PC  8000018016
Thus, the next instruction is fetched from location 8000018016
• Cause register  a code of the exception
Each interrup has its code, e.g.:
– hardware interrupt = 0
– illegal memory address (load/fatch or store) = 4 or 5
– bus error (fetch or load/store)= 6 or 7
– syscall instruction execution = 8
– illegal op-code, i.e. reserved or undefined op-code= 10
– integer overflow = 12
– any floating point exception = 15
Step 3. (Mode of CPU operation set to kernel mode)
• CPU mode bit  0;
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Hardware Interrupt Processing in General
• Hardware interrupt processing first saves the address of the
interrupted instruction. Many architectures use a system stack
(in memory) to save the address, while in MIPS architecture,
EPC register is used.
• Hardware interrupt processing then loads PC with the new
address. In many architectures, new content of PC comes from
one of special memory locations (interrupt vectors). Each
interrupt has its specific vector address, built in the hardware as
a part of ISA. In MIPS architecture, PC always gets the value
8000018016.
• Finally, hardware interrupt processing sets CPU to kernel mode.
• This processing takes equivalent of executing 1-2 instructions.
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O.S. and Hardware Interrupt Processing
• On power-up of computer system, during booting of operating
system, its code and its interrupt handling routines are loaded
starting at the some memory locations.
• In MIPS architecture, the operating system code must start at
memory address 8000018016, and then based on the content
of Cause register appropriate processing is performed.
• Hardware interrupt processing saves the address of the
interrupted instruction so the interrupted program (if needed)
may be later restarted at the point of interruption.
• Note that incoming interrupts may be disabled while another
interrupt is being processed to prevent a loss of interrupts.
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Transition from User Process to O.S. Code
•
•
•
A process is an operating system concept that captures the idea of a
program in execution.
Using system calls, a process requests services of an OS.
Operating system also takes over if a user program encounters
problems during instruction execution, e.g. illegal instruction, or an
hardware interrupt occurs
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Memory Layout For Multiprogramming
Process 1
Process 2
Process 3
Process 4
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Memory Protection
• Must provide memory protection at least for the interrupt
vector and the interrupt service routines. E.g. for this purpose,
MIPS processor provides kernel and user memory address
space, and operating system code is loaded in kernel address
space, while user programs are loaded in user address space.
• But, it must also provide memory protection between user
programs.
• In order to have that memory protection, one approach is to
add two registers that determine the range of legal addresses
a program may access:
Base register – holds the smallest legal physical memory
address.
Limit register – contains the size of the range
• Memory outside the defined range is protected.
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Use of Base and Limit Registers
Instructions for loading into base and limit registers are
privileged instructions.
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Hardware for Address Protection
• This is the simplest methods used for memory protection.
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CPU Protection and Timer
• Timer has the following hardware characteristics:
– Content of timer register is decremented every clock tick,
– When timer reaches zero, a hardware interrupt occurs,
– Load into the timer register is a privileged instruction.
• Operating system sets the appropriate value in the timer (clock)
register before CPU starts execution of any user program. The
value set should correspond to the maximum time the program
can use CPU. This assures that the program can not
monopolize CPU for infinite time, since a hardware interrupt
from the timer (clock) is certain after the set time. When a
hardware interrupt happens, CPU will cease execution of the
program and start execution of the appropriate routine in the
code of operating system.
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Main Components of Operating System
• Process Management:
– process creation and deletion,
– process suspension and resumption,
– provision of mechanisms for:
a. process synchronization,
b. process communication,
c. deadlock handling.
• Main Memory Management:
– keeping track of which parts of memory are currently
being used and by whom,
– allocate and deallocate memory space as needed,
– deciding which processes to load when memory space
becomes available.
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Main Components of Operating System (cont.)
• File Management:
– file creation and deletion,
– directory creation and deletion,
– support of primitives for manipulating files and directories,
– mapping files onto secondary storage,
• I/O System Management:
– a buffer-caching system,
– a general device-driver interface,
– drivers for specific hardware devices.
• Mass-Storage (Secondary) Management:
– free space management
– storage allocation
– disk (head) scheduling
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Main Components of Operating System (cont.)
• Protection and Security System:
– Protection: a mechanism for controlling access by
programs, processes, or users to both system and user
resources; protection mechanisms must distinguish between
authorized and unauthorized usage, specify the controls to
be imposed and provide a means of enforcement.
– Security: defense of the system against internal and external
attacks; It includes: denial-of-service, worms, viruses,
identity theft, theft of services.
• Networking support
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Problem A:
OS loads the exception handling routine at the address 100816.
What else should be done so this routine is activated each time
an interrupt happens? Your solution should include only
instructions.
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Homework 6 : In a MIPS based computer, assume that the
operating system loads:
− the floating point exceptions handling software routine starting at
the memory address 81000014hex,
− the illegal op-code exception handling software routine starting
at the memory address 82000028hex,
− the software routine for handling all other exceptions starting at
the memory address 83000030hex.
What else should be done so this routine is activated each time an
interrupt happens?
Hints: 1. Your assembly code has to start at location 0x80000180.
2. Cause register ($c14) will contain exception code (slide K21).
3. Use MFC0 instruction to bring exception code in one of integer
registers and then based on that code jump/branch appropriately.
Due: Friday 04-07-2017
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