Download TN100 RF module

TN100-MOD
TN100 RF module
Target Specification
Features
■
TN100 transceiver
■
STM32 microcontroller
■
Matching circuits (balun)
■
Integrated 2.4 GHz chip antenna
■
ISM band pass filter
■
32.768 kHz, 16 MHz, and 32 MHz quartz
crystals
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Peripherals
■
27 peripheral module pins with:
– 27 programmable digital IOs
– 2 analog inputs
■
Pulse width modulation (PWM) output
■
Microcontroller reset input
■
2 universal synchronous/asynchronous
receiver/transmitter (USART) input/outputs
■
CAN interface (2.0B Active)
■
Up to two I²C interfaces (SMBus/PMBus)
■
SPI interface
■
Receive/transmit signal that enables an
external preamplifier
■
JTAG interface
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Certification
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The TN100 RF module is certified for use in
Europe (R&TTE) and Japan (ARIB-T66).
Certification is pending for the USA (FCC).
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- Description
This smart TN100 RF module is only 33 mm by
24 mm and less than 3 mm thick. Yet it integrates
all the required components for a complete RF
module based on ST’s innovative TN100
transceiver. As well as the TN100 chip, this
module includes the STM32 microcontroller, a
band pass filter, a balun, and an integrated 2.4
GHz chip antenna.
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December 2008
Rev 1
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
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www.st.com
1
Contents
TN100-MOD
Contents
1
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Schematic diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
4.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2
DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3
RF parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
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Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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TN100-MOD
1
Functional description
Functional description
TN100 transceiver
This module supports a freely adjustable center frequency with 3 non-overlapping frequency
channels within the 2.4 GHz industrial, scientific and medical (ISM) band. This provides
support for multiple physically independent networks and improved coexistence
performance with existing 2.4 GHz wireless technologies. Data rates are selectable from 2
Mbps to 125 kbps.
Due to the chip’s unique chirp pulse, adjustment of the antenna is not critical. This
significantly simplifies the system’s installation and maintenance (“pick and place”).
A sophisticated MAC controller with CSMA/CA and TDMA support is included, as is Forward
Error Correction (FEC) and 128-bit hardware encryption. To minimize software and
microcontroller requirements, the TN100 transceiver also provides scrambling, automatic
address matching, and packet retransmission.
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Integrated into the TN100 transceiver is the Digital Dispersive Delay Line (DDDL) which is
responsible for distinguishing between two possible incoming signals that are generated by
another TN100 chip. This received signal is either an upchirp, a downchirp, or a folded pulse
(an upchirp and a downchirp at the same time). All of these signals have the same center
frequency and the same bandwidth. The difference between an upchirp and a downchirp
occurs only in the phase information of the complex spectrum.
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This phase information is enough for the DDDL to compress a pulse at one output port and
expand it at the other (that is, to extend the incoming signal to the doubled duration). In this
way, the DDDL acts like a matched filter for one of the possible transmitted pulses.
STM32 microcontroller
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This is a low power CMOS 32-bit microcontroller based on the ARM 32-bit Cortex™-M3
CPU with 128 Kbytes of Flash memory and 20 Kbytes of SRAM. This microcontroller drives
the TN100 transceiver via the SPI interface and operates between 2.3 V and 2.7 V.
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Matching circuits (balun)
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At the RF interface of the TN100, a differential impedance of 150 Ohm exists which is
matched to the asymmetrical 50 Ohm impedance of the antenna port by a 150 / 50 RF
balun. Additional external components at the RF interface have a power and noise matching
function that allows a sharing of the antenna without an external Rx/Tx – RF switch.
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Integrated 2.4 GHz chip antenna
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As well as this integrated antenna, an external 2.4 GHz antenna can also be connected to
the module.
ISM band pass filter
For an improved robustness against out-of-band inferences, an ISM band pass filter is
connected at the antenna port.
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Functional description
TN100-MOD
32.768 kHz, 16 MHz, and 32 MHz quartz crystals
The 32.768 kHz quartz is used for the real time clock oscillator. The 16 MHz quartz is used
by the STM32 microcontroller, while the 32 MHz quartz works with the internal oscillator
circuitry of the TN100 chip.
Connectors
The TN100 RF module is programmable via a JTAG interface. 27 peripheral module pins in
total are provided, with 27 programmable digital IOs and 2 analog inputs. The module also
provides a pulse width modulation (PWM) output, a microcontroller reset input, a universal
synchronous/asynchronous receiver/transmitter (USART) input/output, and a
receive/transmit signal that enables an external preamplifier.
Figure 1.
TN100 RF module layout
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TN100-MOD
Pin descriptions
Pin definitions
Pin
no.
Pin name
Type (1)
Table 1.
I/O level(2)
2
Pin descriptions
1
VCC
S
2
JNTRST
I/O
FT
PB4
3
JTDI
I/O
FT
PA15
4
JTMS/SWDIO
I/O
FT
PA13
5
JTCK/SWCLK
I/O
FT
PA14
6
JTDO
I/O
FT
PB3/TRACESWO
7
NRST
I/O
8
GND
S
9
PB5
I/O
Port B5
I2C1_SMBAl
I/O
FT
Port B6 with 4.7kΩ pull up
resistor
I2C1_SCL/TIM4_CH1
I2C1_SDA/TIM4_CH2
TIM4_CH3
10
PB6
Main function(3) (after reset)
Voltage supply
Reset (active low)
Ground supply
11
PB7
I/O
FT
Port B7 with 4.7kΩ pull up
resistor
12
PB8
I/O
FT
Port B8
13
PB9
I/O
FT
Port B9
14
VBAT
S
15
PC13
I/O
16
VDDA
S
17
PA0
18
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TIM4_CH4
Battery supply
Port C13
TAMPER-RTC
I/O
Port A0
WKUP/USART2_CTS/
ADC12_IN0/TIM2_CH1_ETR
PA1
Port A1
USART2_RTS/ADC12_IN1/
TIM2_CH2
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I/O
PA2
I/O
Port A2
USART2_TX/ADC12_IN2/
TIM2_CH3
Port A3
USART2_RX/ADC12_IN3/
TIM2_CH4
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PA3
I/O
21
GND
S
Ground supply
22
GND
S
Ground supply
23
ANT
24
GND
S
25
TX_RX
I/O
26
GND
S
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Alternate functions
External antenna
Ground supply
Tx/Rx switch pin with 4.7kΩ pull
up resistor
Ground supply
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Pin descriptions
TN100-MOD
I/O level(2)
Pin definitions (continued)
Pin
no.
Pin name
Type (1)
Table 1.
27
GND
S
28
PB2/BOOT1
I/O
FT
Port B2
29
PB10
I/O
FT
Port B10
I2C2_SCL/USART3_TX
30
PB11
I/O
FT
Port B11
I2C2_SDA/ USART3_RX
31
GND
S
32
PB12
I/O
FT
Port B12
SPI2_NSS/I2C2_SMBAl/
USART3_CK/TIM1_BKIN
33
PB13
I/O
FT
Port B13
SPI2_SCK/USART3_CTS/
TIM1_CH1N
34
PB14
I/O
FT
Port B14
SPI2_MISO/ USART3_RTS/
TIM1_CH2N
35
PB15
I/O
FT
Port B15
SPI2_MOSI/TIM1_CH3N
36
GND
S
37
PA8
I/O
FT
Port A8
USART1_CK/TIM1_CH1/MCO
38
PA9
I/O
FT
Port A9
USART1_TX/ TIM1_CH2
39
PA10
I/O
FT
Port A10
40
PA11
I/O
FT
Port A11
41
PA12
I/O
FT
Port A12
42
GND
S
Main function(3) (after reset)
Alternate functions
Ground supply
Ground supply
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Ground supply
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USART1_RX/ TIM1_CH3
USART1_CTS/ CANRX/
TIM1_CH4 / USBDM
USART1_RTS/ CANTX /
TIM1_ETR / USBDP
Ground supply
1. I = input, O = output, S = supply, HiZ = high impedance.
2. FT = 5 V tolerant.
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3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is
always the lower number of peripheral that is included. For example, if a device has only one SPI and two
USARTs, they will be called SPI1 and USART1 & USART2, respectively.
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TN100-MOD
3
Schematic diagrams
Schematic diagrams
Figure 2.
TN100 schematic diagram
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Schematic diagrams
Figure 3.
TN100-MOD
Antenna matching circuitry
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TN100-MOD
Schematic diagrams
Figure 4.
STM32 schematic diagram
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Electrical characteristics
TN100-MOD
4
Electrical characteristics
4.1
Absolute maximum ratings
Table 2.
Absolute maximum ratings
Parameter
Value
Unit
Min. operating temperature
-40
°C
Max. operating temperature
+85
°C
Max. supply voltage (VCC)
2.7
V
Max. DC current per I/O pin
40
mA
-0.5 to 13.0
V
Voltage on pin NRST with respect to GND
Note:
Stresses listed above may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those
indicated in the operational sections of the specification is not implied.
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Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
4.2
DC parameters
Table 3.
DC parameters
Symbol
Parameter
VCC
Supply voltage
ICC
Supply current
VIL
Input low voltage
VIH
Input high voltage
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Table 4.
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Test conditions
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fCPU does not exceed
recommended value at
given supply voltage
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Min.
Typ.
Max.
Unit
2.7
V
100
mA
V
2.3
No external connections
other than power supply
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RF
parameters
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VCC = 2.3 to 2.4V
VCC = 2.4 to 2.7V
–0.5
–0.5
0.2VCC
0.3VCC
VCC = 2.3 to 2.4V
VCC = 2.4 to 2.7V
0.7VCC
0.6VCC
VCC+0.5
VCC+0.5
RF parameters
Symbol
Parameter
ZANT
Line impedance of antenna signal ANT
RDATA
Data rate
PSENS
Receiver sensitivity
PTX
Transmit power
Min.
Typ.
Max.
50
125
-33
Unit
Ohm
2000
kb/s
-97(1)
dBm
0
dBm
1. The displayed value is the minimum receive signal power required for BER = 10e-3, which is equivalent to
the maximum receiver sensitivity.
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TN100-MOD
5
Revision history
Revision history
Table 5.
Document revision history
Date
Revision
10-Dec-2008
1
Changes
Initial release.
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TN100-MOD
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