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ECE 313 – Microprocessor Organization
Lecture 4 - Instruction Sets: MIPS
Fall 2004
Reading: 2.3-2.6
Image Source: MIPS, Inc. www.mips.com
Prof. John Nestor
ECE Department
Lafayette College
Easton, Pennsylvania 18042
[email protected]
Portions of these slides are derived from:
Textbook figures © 1998 Morgan Kaufmann Publishers all rights reserved
Tod Amon's COD2e Slides © 1998 Morgan Kaufmann Publishers all rights reserved
Dave Patterson’s CS 152 Slides - Fall 1997 © UCB
Rob Rutenbar’s 18-347 Slides - Fall 1999 CMU
other sources as noted
Some Well-Known Architectures
Type
Architecture
Bits
Appl.+
Microcontroller
68HC11
8/16
E
CISC
80x86 (IA-32)
32
AMD Hammer
64
D/S
Extension of x86
680x0
32
E/D
Palm PDAs , Orig. Mac
MIPS
32/64
E / D / S PS2 / AIBO / SGI
SPARC
32/64
D / S / E Sun wkstns, servers
PowerPC
32/64
E / D / S Mac, Auto, Networks
RISC
ARM
VLIW / EPIC
Ver y Lon gIn str . Wor d
Explictly Par allel
In str . Com p.
DSP
Comments
Industrial / Auto
D / S / E Evolved from 8-bit µP
E
iPOD, Cell Phones
Trimedia
32
E
Multimedia
Intel IA-64
64
S
Itanium® - Servers
TI TMS320
24
E
Telecomm. / Industrial
+Application - E=Embedded, D=Desktop, S=Server
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Lecture 4 - Instruction Sets: MIPS
2
Microprocessor Usage
1400
1300
1200
1100
1000
Other
SPARC
Hitachi SH
PowerPC
Motorola 68K
MIPS
900
IA-32
800
ARM
700
600
500
400
300
200
100
0
1998
1999
2000
2001
2002
Figure 1.2
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Lecture 4 - Instruction Sets: MIPS
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Outline - Instruction Sets
 Instruction Set Overview
 MIPS Instruction Set
 Overview \
 Registers and Memory
 MIPS Instructions
 Software Concerns
 Summary
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Lecture 4 - Instruction Sets: MIPS
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MIPS Design Principles
1. Simplicity Favors Regularity
2. Smaller is Faster
3. Good Design Makes Good Compromises
4. Make the Common Case Fast
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MIPS Registers and Memory
32 bits
R0
R1
R2
R30
R31
32 General Purpose Registers
PC = 0x0000001C
0x00000000
0x00000004
0x00000008
0x0000000C
0x00000010
0x00000014
0x00000018
0x0000001C
0xfffffff4
0xfffffffc
0xfffffffc
Registers
Memory
4GB Max
(Typically 64MB-1GB)
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MIPS Registers
 Fast access to program data
 Register R0/$0/$zero: hardwired to constant zero
 Register names:
 $0-$31 or R0-R31
 Specialized names based on usage convention
•
•
•
•
$zero ($0) - always zero
$s0-$s7 ($16-$23) - “saved” registers
$t0-$t7 ($8-$15) - “temporary” registers
$sp - stack pointer
• Other special-purpose registers
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MIPS Registers and Usage
Name
$zero
$at
$v0-$v1
$a0-$a3
$t0-$t7
$s0-$s7
$t8-$t9
$k0-$k1
$gp
$sp
$fp
$ra
Register number
0
1
2-3
4-7
8-15
16-23
24-25
26-27
28
29
30
31
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Usage
the constant value 0
reserved for assembler
values for results and expression evaluation
arguments
temporary registers
saved registers
more temporary registers
reserved for Operating System kernel
global pointer
stack pointer
frame pointer
return address
Lecture 4 - Instruction Sets: MIPS
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More about MIPS Memory Organization
 Two views of memory:
 232 bytes with addresses 0, 1, 2, …, 232-1
 230 4-byte words* with addresses 0, 4, 8, …, 232-4
Not all architectures require this
 Both views use byte addresses
 Word address must be multiple of 4 (aligned)
8 bits
0x00000000
0x00000001
0x00000002
0x00000003
32 bits
0x00000000
0x00000004
0x00000008
0x0000000C
0
1
2
3
*Word sizes vary in
other architectures
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MIPS Instructions
 All instructions exactly 32 bits wide
 Different formats for different purposes
 Similarities in formats ease implementation
6 bits
5 bits
5 bits
5 bits
5 bits
op
rs
rt
rd
6 bits
5 bits
5 bits
16 bits
op
rs
rt
offset
shamt funct
6 bits
26 bits
op
address
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6 bits
Lecture 4 - Instruction Sets: MIPS
R-Format
I-Format
J-Format
13
MIPS Instruction Types
 Arithmetic & Logical - manipulate data in registers
add $s1, $s2, $s3
or $s3, $s4, $s5
$s1 = $s2 + $s3
$s3 = $s4 OR $s5
 Data Transfer - move register data to/from memory
lw $s1, 100($s2)
sw $s1, 100($s2)
$s1 = Memory[$s2 + 100]
Memory[$s2 + 100] = $s1
 Branch - alter program flow
beq $s1, $s2, 25
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if ($s1==$s1)
PC = PC + 4 + 4*25
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MIPS Arithmetic & Logical Instructions
 Instruction usage (assembly)
add dest, src1, src2
sub dest, src1, src2
and dest, src1, src2
dest=src1 + src2
dest=src1 - src2
dest=src1 AND src2
 Instruction characteristics
 Always 3 operands: destination + 2 sources
 Operand order is fixed
 Operands are always general purpose registers
 Design Principles:
 Design Principle 1: Simplicity favors regularity
 Design Principle 2: Smaller is faster
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Arithmetic Instruction Examples
 C simple addition and assignment
C code:
A = B + C
MIPS code:
add $s0, $s1, $s2
 Complex arithmetic assignment:
C code:
A = B + C + D;
E = F - A;
MIPS code:
add $t0, $s1, $s2
add $s0, $t0, $s3
sub $s4, $s5, $s0
 Compiler keeps track of mapping variables to
registers (and, when necessary, memory)
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MIPS Data Transfer Instructions
 Transfer data between registers and memory
 Instruction format (assembly)
lw $dest, offset($addr)
sw $src, offset($addr)
load word
store word
 Uses:
 Accessing a variable in main memory
 Accessing an array element
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Example - Loading a Simple Variable
8
R0=0 (constant)
R1
R2=0x10
R3
R4
R5 =R5
692310
+
0x00
0x04
0x08
0x0c
0x10
0x14
0x18
0x1c
Variable X
Variable Y
Variable Z = 692310
R30
R31
Registers
lw R5,8(R2)
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Lecture 4 - Instruction Sets: MIPS
Memory
20
Data Transfer Example - Array Variable
12=0xc
R0=0 (constant)
R1
R2=0x08
R3
R4
R5=105
+
Base Address
0x00
0x04
0x08
0x0c
0x10
0x14
0x18
0x1c
a[0]
a[1]
a[2]
a[3]=105
a[3]
a[4]
R30
R31
Registers
C Program:
Assembly:
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int a[5];
a[3] = z;
scaled offset
sw $5,12($2)
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Memory
21
MIPS Conditional Branch Instructions
 Conditional branches allow decision making
beq R1, R2, LABEL
bne R3, R4, LABEL
if R1==R2 goto LABEL
if R3!=R4 goto LABEL
 Example
C Code
L1:
Assembly
L1:
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if (i==j) goto L1;
f = g + h;
f = f - i;
beq $s3, $s4, L1
add $s0, $s1, $s2
sub $s0, $s0, $s3
Lecture 4 - Instruction Sets: MIPS
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Example: Compiling C if-then-else
 Example
C Code
if (i==j) f = g + h;
else f = g - h;
bne $s3, $s4, Else
add $s0, $s1, $s2
j Exit;
# new: unconditional jump
Else: sub $s0, $s0, $s3
Exit:
Assembly
 New Instruction: Unconditional jump
j LABEL
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# goto Label
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Comparisons - What about <, <=, >, >=?
 bne, beq provide equality comparison
 slt provides magnitude comparison
slt $t0,$s3,$s4
condition register
# if $s3<$s4 $t0=1;
# else $t0=0;
 Combine with bne or beq to branch:
slt $t0,$s3,$s4
bne $t0,$zero, Less
# if (a<b)
#
goto Less;
 Why not include a blt instruction in hardware?
 Supporting in hardware would lower performance
 Assembler provides this function if desired
(by generating the two instructions)
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Binary Representation - Jump
6 bits
26 bits
op
address
 Jump Instruction uses J-Format (op=2)
 What happens during execution?
PC = PC[31:28]
:
(IR[25:0] << 2)
Conversion to
Concatenate upper 4 bits word offset
of PC to form complete
32-bit address
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Jump Example
 Machine language for Assume L5 is at address 0x00400020
and
j L5
lower 28
PC <= 0x03FFFFFF
bits
>>2
6 bits
26 bits
op
address
2
0x0100008
000010
00000100000000000000001000
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Lecture 4 - Instruction Sets: MIPS
0x0100008
Decimal/Hex
Binary
31
Constants / Immediate Instructions
 Small constants are used quite frequently
(50% of operands)
e.g., A = A + 5;
B = B + 1;
C = C - 18;
 MIPS Immediate Instructions (I-Format):
addi $29, $29, 4
slti $8, $18, 10
andi $29, $29, 6
ori $29, $29, 4
Arithmetic instructions sign-extend immed.
Logical instructions don’t sign extend immed.
 Allows up to 16-bit constants
 How do you load just a constant into a register?
ori $5, $zero, 666
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MIPS Logical Instructions
 and, andi - bitwise AND
 or, ori - bitwise OR
 Example
$s0 11011111010110100100100011110101
$s1 11110000111100001111000011110000
$s2,$s0,$s1
$s2 11010000010100000100000011110000 and
00000000000000000000000011111100 (25210)
$s3 11010000010100000100000011111100
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Lecture 4 - Instruction Sets: MIPS
ori
$s3,s2,252
34
Summary - MIPS Instruction Set
 Three instruction formats
 Similarities in formats ease implementation
6 bits
5 bits
5 bits
5 bits
5 bits
op
rs
rt
rd
6 bits
5 bits
5 bits
16 bits
op
rs
rt
offset
shamt funct
6 bits
26 bits
op
address
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6 bits
Lecture 4 - Instruction Sets: MIPS
R-Format
I-Format
J-Format
39
Instruction Sets - Overview
 Instruction Set Overview
 MIPS Instruction Set
 Overview
 Registers and Memory
 Instructions
 Software Concerns





\
Compiling C Constructs
Procedures (Subroutines) and Stacks
Example: Internet Worms
Compiling, Linking, and Loading
Example: String Processing / SPIM Demo
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Procedure Calls in MIPS
 Register conventions to support procedures:
 $a0-$a3 - four argument registers ($4-$7)
 $v0-$v1 - two return value registers ($2-$3)
 $ra - one return address register ($31)
 Calling procedures - jump and link (jal)
jal ProcedureAddress
// J-Format instr.
effect:
$ra = PC
PC = ProcedureAddress
 Returning from procedure - “jump register (jr)
jr $ra
effect:
PC = $ra
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Using the Stack
 Stack operations
 Push - add data to stack
 Pop - remove data from stack
(stored data)
(stored data)
(stored data)
High Address
0x7fffffff
 MIPS stack pointer: $sp
$sp
(stored data)
(stored data)
(stored data)
Direction of
Growth
Low Address
0x00000000
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“Push” - Adding Data to the Stack
 Adjust stack pointer to
allocate space
subi $sp,$sp,12
 Store registers in allocated
space
sw $t1,8($sp)
sw $t0,4($sp)
sw $s0,0($sp)
$sp
(stored data)
(stored data)
(stored data)
(stored data)
(stored data)
(stored data)
(contents of $t1)
(contents of $t0)
(contents of $s0)
High Address
0xffffffff
Direction of
Growth
Low Address
0x00000000
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Pop - Removing Data from Stack
 Move data from stack to
register if needed
lw $s0,0($sp)
lw $t0,4($sp)
lw $t0,8($sp)
 Adjust stack pointer to
remove space
$sp
addi $sp,$sp,12
(stored data)
(stored data)
(stored data)
(stored data)
(stored data)
(stored data)
(contents
(contents of $t1)
$t1)
(contents
(contents of $t0)
$t0)
(contents
(contents of
of $s0)
$s0)
High Address
0xffffffff
Direction of
Shrinkage
Low Address
0x00000000
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Nested Calls in C Functions
DTYPE read_input(char* filename) {
...
return data;
}
void process_data(DTYPE pdata) {
main(char *argc[], int argv) {
DTYPE data;
data = read_input(argv[0]));
process_data(stuff);
write_output(stuff)
}
x = f1(pdata[I]);
…
f2(pdata[J])
...
}
int f1( ... ) {
. . .
return x;
}
int f1( ... ) {
. . .
}
void write_data(DTYPE wdata) {
...
}
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Recursion in C Functions
int fact (int n) /* see book p. 136)
{
if (n < 1) return 1;
else return (n * fact(n-1));
}
int fact (5)
{
fact 1;
(4)
if (n < 1)int
return
{
else return (n * fact(n-1));
(3)1;
if (n <int
1) fact
return
}
{
else return (n *int
fact(n-1));
fact (2)
if
(n
<
1)
return
1;
}
{
else return (n int
* fact(n-1));
(1) 1;
if (n < 1)fact
return
}
{
else return (n * int
fact(n-1));
fact (0)
if
(n
<
1)
return
1;
}
{
else return (n * fact(n-1));
if (n < 1) return 1;
}
else return (n * fact(n-1));
}
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Procedures and the Stack
 Each called procedure maintains a stack frame
$fp
$fp
$sp
$sp
$fp
frame
pointer
Saved argument
registers (if any)
Saved return addr.
Saved “saved”
registers e.g. $s0
(if any)
$sp
Before Call
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Local arrays
and structures
(if any)
After Call
Lecture 4 - Instruction Sets: MIPS
After Return
47
MIPS Runtime - Memory Map
0xffffffff
Reserved (OS)
0x7fffffff
Stack
$sp
Stack Data
Dynamic Data
0x1008000
0x1000000
Heap
$gp
Static data
Static Data
Instructions
0x00040000
Text
0x00000000
Reserved
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Dynamic Memory Allocation
 C programs
Stack
 Create space using malloc
 Release space using free
(watch for memory leaks!)
 Java programs
Stack Data
Heap
 Create objects using new
 Space recovered by
garbage collection
Static Data
Dynamic Data
Static Data
t1 = malloc(sizeof struct S1);
t2 = malloc(sizeof struct S2);
t3 = malloc(sizeof struct S1);
free(t1);
free(t3);
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Summary: MIPS Architecture
Registers
Memory (Max. 4GB)
32 bits
32 bits
R0
R1
R2
0x00000000
0x00000004
0x00000008
0x0000000C
0x00000010
0x00000014
0x00000018
0x0000001C
R30
R31
32 General Purpose Registers
32
0xfffffffc
PC = 0x0000001C
0xfffffffc
Instruction Formats (Fixed Length)
op
rs
rt
op
rs
rt
op
ECE 313 Fall 2004
rd
shamt funct
R-Format
offset
I-Format
address
Lecture 4 - Instruction Sets: MIPS
J-Format
51
Summary: MIPS Instructions
Cate gory
Ari thme tic
add
MIPS as sembly language
Examp le
Mean ing
add $s1, $s2, $s3
$s1 = $s2 + $s3
Three operands ; data in regis ters
s ubtrac t
sub $s1, $s2, $s3
$s1 = $s2 - $s3
Three operands ; data in regis ters
add immediate
addi $s1, $s2, 100
lw $s1, 100($s2)
sw $s1, 100($s2)
lb $s1, 100($s2)
sb $s1, 100($s2)
lui $s1, 100
$s1 = $s2 + 100
$s1 = Memo ry[ $s2 + 100 ]
Memo ry[$s2 + 100 ] = $s1
$s1 = Memo ry[ $s2 + 100 ]
Memo ry[$s2 + 100 ] = $s1
$s 1 = 100 * 216
Us ed to add cons tants
beq
$s1, $s2, 25
if ($s 1 == $s2) go to
PC + 4 + 100
Equal test; PC-relative branch
branch on not equalbne
$s1, $s2, 25
if ($s 1 != $s2) go to
PC + 4 + 100
Not equal test; PC-relativ e
$s1, $s2, $s3
if ($s 2 < $s3) $s 1 = 1;
els e$s 1 = 0
Compare less than; for beq, bne
if ($s 2 < 100) $s 1 = 1;
els e$s 1 = 0
Compare less than cons tant
In structio n
load w ord
s tore w ord
Data tran sfer
load byte
s tore byte
load upper
immediate
branch on equal
Cond itio nal
bra nch
Uncondi ti onal jum p
s et on less than
slt
s et less than
immediate
slti
jump
j
jr
jal
jump regis ter
jump and link
$s1, $s2, 100
2500
$ra
2500
Comm ents
Word from memory to register
Word from regis ter to memory
By te from memory to register
By te from regis ter to memory
Loads cons tant in upper 16 bits
go to 1000 0
Jump to target addres s
go to $ra
For s w itc h, procedure return
$ra= PC + 4 ; go to 1000 0 For proc edure c all
(From textbook - COPYRIGHT 1998 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED)
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Summary: MIPS Addressing Modes
Textbook Fig. 2.24 - COPYRIGHT 1998
MORGAN KAUFMANN PUBLISHERS, INC.
ALL RIGHTS RESERVED)
Used for lw, lb, lh
Used for beq, bne
Used for j, jal
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53