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Unit1: Modeling & Simulation Module2: Behavioral Modeling Contents Introduction Description of the pulse Sources of delays Different ways of behavioral modeling ◦ Delay table ◦ Timing modeling in RTLs Introduction Variations between input-output signals ◦ Output value varies according to the function ◦ Arrival of output varies w.r.t input Complete behavior of the circuit is described by amplitude and time variations of the output w.r.t to time. The model which enables the complete description of the block is called as behavioral model. Representation of any Gate Any gate can be represented by ideal gate and adding delay model to it. Ideal gate represents the function model of the gate. Functional modeling is a part of behavioral modeling. Why do we need behavioral modeling Any pulse in a digital circuit has a certain ◦ Amplitude ◦ Width ◦ Rise time ◦ Fall time To get the exact behavior of a circuit we need transient analysis of the circuit for a digital circuit. Modeling a Digital pulse – type 1 t1 t2 We can model the pulse into a square signal. The pulse is assumed to be start at 50% of the of the signal. Amplitude. Pulse Width = t2 - t1 Rise time and Fall time Rise time Fall time • Rise time: time taken by the signal to change its value from 10% of its amplitude to 90%. • Fall time: time taken by the signal to change its value from 90% of its amplitude to 10%. • tr and tf are also called Rise time and fall time delay. Propagation delay Propagation delay of a gate defines how quickly it responds to a change at its input(s). It is measured between the 50% transition points of the input and output waveforms : Input and output pulse for an inverter Modeling a Digital pulse – type 2 Due to Rise and fall delay another way of modeling a pulse as square pulse seems to be insufficient. Trapezium is used to model a pulse. t1 t2 Delay model as a Table Green lines : 10% and 90% values Red lines : 50% values Delay type Delay Value Tr(Rise time) 1 ns Tf(Fall time) 1 ns Td(Propagation delay) 1.4 ns Pulse width 4.2 ns Sources of Delays Logic high voltage nearer to Vdd Logic low voltage nearer to Vss (ground) The cause of delay is that any signal is an analog quantity which needs a finite amount of delay for voltage to change from one logic state to another. Two types of delays ◦ Propagation delay or transport delay ◦ Inertial delay or switching delay Transport Delay Causes of delay ◦ Transportation of charge carriers from source to drain in a control device ◦ Charging and discharging of various nodal capacitances The time interval between the generation of a signal transition at a gate output (source) and its arrival at the input of a fan-out gate (destination) is known as propagation delay. How does transport delay vary? Increases with increase in ◦ Operating temperature ◦ Marginal supply voltage ◦ Output load capacitance If the output is used to drive many other gates, the propagation delay increase drastically. Inertial Delay Minimum time for which the input signal persist in order for change to appear at an output. Pulse duration less than inertial delay does not contain enough energy to cause the device to switch. Combined effect of inertial and transport delay Since the pulse width is less than inertial delay, output does not switch for the first input pulse. Transport delay is around 10units RTL Gate delays In RTL also we can have timing description using behavioral model. RTL code : AND #5 a1 (e, a, b); OR #4 a2(out , e, c); NOTE : Here #5 means 5 units of delay.We have to assign unit of delay in RTL model. Ex : 1 unit = 1 ns AND gate have a delay of 5 units and OR gate have a delay of 4 units as shown in figure. Test bench and Waveform • • Test bench in RTL is the values of inputs given at different time. For the previous circuit the test bench can be this : Begin A= 1'bO; B= 1'bO; C= 1'bO; #10 A= 1'b1; B= 1'b1; C= 1'b1; #10 A= 1'b1; B= 1'bO; C= 1'bO; #20 $finish; end Waveform • Waveform shows the input and output signal at different instance of time • The waveform of the circuit shown previously when given the inputs of test bench is shown below. Rise and fall delay Each pulse has its rise and fall delay. • Rise and fall delay can also be modeled in RTL if needed : / / Rise and Fall Delay Specification and # (rise-delay, fall-delay) a2 (out, i1, i2) ; • and #(4,6) a2(out, i1, i2); / / Rise= 4, Fall = 6 Rise delay of output of gate is 4 units and fall delay of output of gate is 6 units. Procedural and Non-Procedural • RTL can be divided into two classes based on timing description : – Procedural : Statements are sequentially executed. A=B C = A. The value transferred to C is the new value of A – Non-Procedural : Statements are executed in parallel. A=B B = A. This leads to an exchange the value of A and B. Thank You