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STATISTICAL DESIGN AND YIELD
ENHANCEMENT OF LOW VOLTAGE CMOS
ANALOG VLSI CIRCUITS
Istanbul Technical University
Electronics and Communications Engineering Department
Tuna B. Tarim
Prof. Dr. Hakan Kuntman
Prof. Mohammed Ismail
The Ohio State University, Electrical Engineering Department
OUTLINE
• Introduction - Motivation
• The Statistical MOS (SMOS) Model and Statistical Design Techniques
- Statistical MOS model
- Statistical techniques
- Statistical design methodology
• Low Voltage Low Power Analog MOS VLSI Circuits
• Statistical Design of Analog VLSI Circuits
• Conclusion - Contribution
INTRODUCTION
Why low voltage and low power?
• Technology driven
Reduction of the minimum feature size to scale down the chip area
• Design driven
Millions of transistors are fabricated on the same chip; this will increase the power
consumption and cause excessive heating
• Market driven
Telecommunications, medical, consumer electronics, etc.
INTRODUCTION
• Despite the technological progress in the fabrication process steps, the fluctuation in each step that affects the device performances have not been scaled
down in proportion. The fabrication process is not easily characterized because
these variations are random in nature.
• Simulation
• Mass production - Monte Carlo Analysis, SMOS
• Yield
INTRODUCTION
• Due to inherent fluctuations in any integrated circuit manufacturing process,
the functional yield is always less than 100%. As the complexity of VLSI chips
increase, and the dimensions of VLSI devices decrease, the sensitivity of performance to process fluctuations increases, thus, further reducing the functional yield.
• With current trends of higher levels of integration leading to complete mixedsignal systems on a chip, yield loss due to the analog component must be minimized such that it has little effect on the yield of the mixed-signal chip
• Statistical models and techniques should be used to include random variations,
and to make robust analog IC designs
INTRODUCTION
• This study demonstrates the critical need to perform statistical design and optimization in order to enhance both the functional yield and reliability of low
voltage low power analog VLSI circuits
• The term “enhancing functional yield” stands for using tools and techniques
that will target a high functional yield, by reducing the standard deviation of
the circuit performance
• The term “statistical design” includes the whole process of making a robust
analog IC design
• The yield specification is not initially set. It is the goal to show that it is possible to enhance the yield by reducing the standard deviation of the performance
and optimizing the circuit
INTRODUCTION
Statistical design will enable the designer to
• Estimate the functional yield of the circuits before fabrication
-
What is functional yield?
• Quantify the contribution of each component to the yield of the circuit
• Focus on the layout of the most critical components
• Quantitatively estimate how much the yield can be improved by appropriately
selecting the areas of transistors
SMOS MODEL AND STATISTICAL DESIGN TECHNIQUES
• Statistical modeling (SMOS model)
• Statistical techniques (design of experiments, response surface methodology)
• Statistical design methodology
SMOS MODEL AND STATISTICAL DESIGN TECHNIQUES
Statistical modeling
• Random variations in integrated circuit processes result in random variations in
transistor parameters
• Building a statistical model requires knowledge of transistor parameter
variance
- Inter-die parameter variation
- Intra-die parameter variation
SMOS MODEL AND STATISTICAL DESIGN TECHNIQUES
• Building a statistical model requires knowledge of transistor parameter variance
PROCESS
LOT
WAFER
FAB
LINE-1
FAB
LINE-2
INTER-DIE VARIABILITY
DIE
INTRA-DIE
SMOS MODEL AND STATISTICAL DESIGN TECHNIQUES
• Inter-die parameter variation
• Intra-die parameter variation
SMOS MODEL AND STATISTICAL DESIGN TECHNIQUES
Standard deviation of parameter (P) mismatch between two transistors in
relationship to the device layout
ap
2 2
σ2(P)= -------- + s p D 12
WL
σ
ap, sp
W
L
D12
: Standard deviation
: Process dependent fitting constants
: Channel width
: Channel length
: Distance between transistors
SMOS MODEL AND STATISTICAL DESIGN TECHNIQUES
Statistical techniques
• Circuit designers would like to make as much experiments as possible by
changing the input variables of their circuit in a wide range, in order to optimize their circuit performances
• Building the circuit on silicon, to find the optimum solution, is too costly and a
difficult method to apply
• Statistical techniques can be employed to build the empirical model of the circuit; variables affecting the circuit performance will be the variables of the
empirical model
• It is possible to vary the input variables in a wide range
SMOS MODEL AND STATISTICAL DESIGN TECHNIQUES
• Design of experiments (DOE)
A widely used systematic method for experiment planning and making experiments in an efficient way. We will use DOE to screen out the most important variables (Placket-Burman screening experiment) in the empirical model that will
affect the circuit performance, and to build an empirical model (Box-Behnken
model building experiment) for the circuit.
• Response surface methodology (RSM)
Characterizes the relationship between the output and independent input variables of the system
SMOS MODEL AND STATISTICAL DESIGN TECHNIQUES
Placket-Burman and Box-Behnken designs;
• Used in industry and academia for a long time
• Both are fractional factorial designs
• Efficient number of runs over other candidates
SMOS MODEL AND STATISTICAL DESIGN TECHNIQUES
Statistical design methodology
• Circuit performance (e.g., offset)
• Which transistors in the circuit are
the most effective on the offset performance
• Input variables, levels, ranges
• Screening experiment
• Model building experiment
• RSM to characterize the relationship
between the output and the input variables
Current
mirror
LOW VOLTAGE LOW POWER ANALOG VLSI CIRCUITS
Vd
Id
Vg
Vtn+|Vtp|
Vs
- High equivalent threshold voltage
- Both n-well and p-well are needed
LOW VOLTAGE LOW POWER ANALOG VLSI CIRCUITS
Idn
Idn
Vsn
VB
Vsp
Idp
(a)
Idn=Idp
Vs1=Vs2
Vg-Vs > VTn + |VTp|
Idp
(b)
Idn=Idp
Vs2-Vs1=VB
Vg-Vs > VTn + |VTp| - VB
LOW VOLTAGE LOW POWER ANALOG VLSI CIRCUITS
IB
V1
V1
V2
V2
IB









2I B
V2=V1 - V T + --------K
V2=V1 -
∆
LOW VOLTAGE LOW POWER ANALOG VLSI CIRCUITS
VDD
Mpcm
Vg
Id2
Id1
Mn1
Vx
IB
Id (=Id1)
Vy
Mn2
Vs
Id3
Mp1
K eq
2
I d = ---------- ( V gs – V Teq )
2
1
1
1
-------------- = --------------- + --------------K eq
K n1
K p1
2( I B – I d )
V Teq = V Tp – -------------------------K n2
VSS
2I B
V Teq = V Tp – ---------K n2
LOW VOLTAGE LOW POWER ANALOG VLSI CIRCUITS
• Only n-well needed for transistor Mp1
• Equivalent threshold voltage is much less than the composite transistor
• IB>>Id
• Trade-off between low voltage operation and low power dissipation
LOW VOLTAGE LOW POWER ANALOG VLSI CIRCUITS
V G1
I1
V y1
Mn1
I o1
V 01 =V
V G2
I2
Mn2
V G2
I3
V y2
Mn2’
V G1
I4
Mn1’
I o2
V 02 =V
• Simple and effective way to realize resistors in a chip
• Provides electronically tunable terminal to compensate process and temperature variation
• Comprises four identical transistors operating in the triode region to replace resistors in
active RC filters
• MOS nonlinearities are canceled when the two output currents are subtracted
LOW VOLTAGE LOW POWER ANALOG VLSI CIRCUITS
• All transistors in the circuit are operating in the triode region
• Vo1=Vo2=V
• The operation of the circuit depends on the perfect matching of transistors
LOW VOLTAGE LOW POWER ANALOG VLSI CIRCUITS
Io = (I1 + I3) - (I2 + I4)
1
I 1 = K 1  V G1 – V y1 – V T – --- ( V – V y1 ) ( V – V y1 )


2
1
I 2 = K 2  V G2 – V y1 – V T – --- ( V – V y1 ) ( V – V y1 )


2
1
I 3 = K 3  V G2 – V y2 – V T – --- ( V – V y2 ) ( V – V y2 )


2
1
I 4 = K 4  V G1 – V y2 – V T – --- ( V – V y2 ) ( V – V y2 )


2
Io = K(VG1 - VG2)(Vy2 - Vy1)
LOW VOLTAGE LOW POWER ANALOG VLSI CIRCUITS
• For exact cancelation of nonlinearities, exact transistor matching is needed,
whereas random variations may not always allow for exact matching of transistors. It is important to quantitatively determine the effect of mismatch on nonlinearity cancelation.
STATISTICAL DESIGN OF ANALOG VLSI CIRCUITS
• Device mismatch is a function of the device area and separation distance
•
ab = W
W
L
a
b
a
--- = L
b
: Transistor channel width
: Transistor channel length
: Area of transistors
: Aspect ratio of transistors
2
5
W
5
e.g.; ----- = --- ⇒ a = 10µm b = --2
L
2
• Initial placement of transistors are included in the netlist
STATISTICAL DESIGN OF ANALOG VLSI CIRCUITS
VDD
Mpcm
V G1
I1
Vg
Id2
Id1
Mn1
Vx
IB
Id (=Id1)
Vy
Mn2
V y1
Mn1
I o1
V 01 =V
V G2
I2
Mn2
Vs
Id3
V G2
Mp1
I3
VSS
V y2
Mn2’
V G1
I4
Mn1’
I o2
V 02 =V
STATISTICAL DESIGN OF ANALOG VLSI CIRCUITS
• Statistical design of the low voltage square-law CMOS composite cell
Area and level assignment
Transistors
Mn1
Mn2
Mpcm
Mp1
IB
Area symbol
an1
an2
apcm
ap1
ancs
(-1)µm2
10
200
450
30
114
(+1)µm2
50
1000
2250
150
570
STATISTICAL DESIGN OF ANALOG VLSI CIRCUITS
σ(Icm) = 0.02487 - 0.0298an1 + 0.00081an2 + 0.02401an12 - 0.00009an22
+ 0.00145an1an2 + 0.00033an2ap1
• an1, an2 and ap1 are [10µm2, 50µm2], [200µm2, 1000µm2] and
[30µm2, 150µm2], respectively
• R2=93.3%
STATISTICAL DESIGN OF ANALOG VLSI CIRCUITS
APLAC 7.30 User: The Ohio-State Solid-State Microelectronics Lab.
0.5
0.5
APLAC 7.30 User: The Ohio-State Solid-State Microelectronics Lab.
Hold value for ap1=90um^
2.1%
0.4
0.4
2.3%
an1 (um^2)
an1 (um^2)
Hold value for an2=600um^
0.3
2.5%
0.2
2.35%
0.3
2.45%
2.55%
0.2
2.65%
0.1
2
4
6
8
10
0.1
0.5
0.75
an2 (um^2)
sigma(Icm)
1
1.25
1.5
ap1 (um^2)
sigma(Icm)
Response surfaces for pairs of transistors for the low voltage CMOS square-law
composite cell; a) an1 vs. an2 (ap1=90µm2), b) an1 vs. ap1 (an2=600µm2)
STATISTICAL DESIGN OF ANALOG VLSI CIRCUITS
There could be two ways to interpret and/or to make use of the graph:
• If there is a specific value that is preferred for each transistor, it is possible to
find those values from the x and y axis, and find the intersection point. The
value of the surface which crosses that intersection point gives the standard
deviation value of the current mismatch.
• If there is a certain current mismatch that is preferred, e.g., according to the
design specifications, the circuit cannot tolerate more than a certain value of
current mismatch, it is possible to find the surface that corresponds to that
value. Then, the areas that intersect on that surface will be the solution. Obviously, there will be more than one solution; this brings the preferred flexibility
of selecting the suitable values for different designs.
STATISTICAL DESIGN OF ANALOG VLSI CIRCUITS
• The average standard deviation seen from the contour curves is in the range of
2.3%, which means that the random process variations will affect the circuit
performance with a 2.3% variation. The lowest standard deviation value which
can be achieved from the curves, though, are 2.1% with the appropriate sizing
of the transistors. The designer has the flexibility of deciding if those values are
actually appropriate for the circuit, and if not, to be prepared for the variation
on the performance.
STATISTICAL DESIGN OF ANALOG VLSI CIRCUITS
• It is possible to use the standard deviation information to enhance the yield. Let
us assume that the goal of optimization is to obtain the minimum device area
while achieving Icm<5%, with a functional yield of 95%, or equivalently, to
achieve the standard deviation of the relative drain current mismatch of 2.5%,
since 95% is approximately ±2σ . The minimum point on the response surface
corresponding to 2.5% is found to be an1=10µm2, an2=300µm2, and
W
5
ap1=90µm2. From the definition of W and L given previously,  -----
= --- ,
 L  n1
2
W
122
26
W
-----
= ------- . Thus, when these aspect ratios are used
= --------- , and  -----
 L  n2
 L  p1
2.5
3.5
for transistors Mn1, Mn2 and Mp1, the standard deviation will not exceed 2.5%,
and the functional yield will be 95%.
STATISTICAL DESIGN OF ANALOG VLSI CIRCUITS
• Statistical design of the four-MOSFET structure
The statistical simulations were done for different sizing of the transistors for the
nonlinearity performance. The nonlinearity that is calculated from the transfer
curves for different sizing of transistors is very low, however, nominal simulations do not include the random process variations, thus, the effect of these variations are not reflected to the results.
STATISTICAL DESIGN OF ANALOG VLSI CIRCUITS
4.5
l=2um
l=4um
l=6um
l=8um
l=10um
l=15um
l=20um
4
sigma(alpha1)/G (10−2 V−1)
3.5
3
2.5
2
1.5
1
0.5
4
6
8
10
12
W (um)
14
16
18
20
STATISTICAL DESIGN OF ANALOG VLSI CIRCUITS
Experimental results
• MOSIS 2µm process
• W/L=4/4 and W/L=20/4
• 28 samples of the four-MOSFET structure with the aspect ratio of 4/4, and 32
samples for the aspect ratio of 20/4 were fabricated on 4 tiny MOSIS chips
• Measurements were taken using the HP4145B parameter analyzer
STATISTICAL DESIGN OF ANALOG VLSI CIRCUITS
nonlinearity (W/L=4/4)
Chip A
Chip B
Chip C
Chip D
mean (µA/V2)
1.0886
1.0517
0.7164
0.9707
standard deviation/G (%V-1)
3.3801
3.0978
2.282
2.4589
nonlinearity (W/L=20/4)
Chip A
Chip B
Chip C
Chip D
mean (µA/V2)
0.95
4.5907
1.562
4.546
standard deviation/G (%V-1)
0.6061
2.3317
1.3726
2.8147
STATISTICAL DESIGN OF ANALOG VLSI CIRCUITS
CONCLUSION - CONTRIBUTION
• Development of a statistical optimizer of the functional yield
• The optimizer enhances the functional yield of intra-die random variations
(device mismatches)
• The optimizer uses design of experiments (DOE) to minimize the number of
inputs to the optimizer to those that are most signficant; an empirical model is
then built using the response surface methodology (RSM) relating the output of
interest to a set of input variables
• Robust design of analog MOS integrated circuits has been demonstrated using
the optimizer
• The emphasis has been on low voltage low power MOS circuits where random
variations do not scale down with feature size or power supply voltage making
statistical design and optimization a critical step towards achieving manufacturable, robust designs with high yield