Download review for elec 105 midterm exam #1 (fall 2001)

ELEC 350
Electronics I
Fall 2011
Final Exam Information
Rough breakdown of topic coverage:
40-70%
10-20%
10-20%
10-20%
BJT fundamentals and biasing, MOSFET small-signal modeling
MOSFET fundamentals and biasing
Diodes (pn-junction diodes, zeners, attenuator circuits)
Op-amps, including non-ideal effects
See the “Course Outcomes” section of the Course Description page at the ELEC 350 web site for
a more detailed list of specific competencies that are likely to be assessed.
The exam will take place 8:00-11:00 am on Wednesday, December 14 in Dana 113 (Gardner
Lecture Hall). The exam will be designed to be approximately 1.5 hours in length, but you will
have the full three hours to complete it.
You will be allowed to use up to four 8.5 x 11-inch review sheets with text on the front and back
of each. There are no restrictions on the material placed on the review sheets. Please note that all
review sheets will be collected at the end of the exam.
The final exam grade cannot be dropped.
Review Topics for Final Exam
The following is a list of topics that could appear in one form or another on the exam. Not all of
these topics will be covered, and it is possible that an exam problem could cover a detail not
specifically listed here. However, this list has been made as comprehensive as possible. You
should be familiar with the topics on the previous review sheets in addition to those listed below.
General small-signal modeling
- definition of “incremental signal” (fluctuations are a small fraction of bias level)
- separation of bias considerations (quiescent levels; output voltage swing range) from
small-signal considerations (gain, input and output resistance)
- replacement of DC voltage sources with short circuits (because voltage across a DC
voltage source can’t change)
- replacement of DC current sources with open circuits (because current through a DC
current source can’t change)
- replacement of large capacitors with short circuits (if capacitive reactance is
insignificant at operating frequency)
- replacement of large inductors with open circuits (if inductive reactance is very large
at operating frequency)
- DC voltage sources are typically bypassed at AC (i.e., at signal frequency) using
capacitors to ensure that the source acts as an AC ground.
- small-signal models of FETs and BJTs are only valid when device operates in the
constant-current region (saturation for MOSFETs, active for BJTs)
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-
small-signal models are not valid in the cut-off region or in the triode region for FETs
or the saturation region for BJTs
- derivation of small-signal voltage gain vo/vin
- simplifications can sometimes be made in gain expressions when one term is much
greater/smaller than another term
Small-signal modeling of MOSFET circuits
- gate-source path modeled as an open circuit
- small-signal transconductance gm
i
o basic definition: g m  D
vGS v V
GS
GS
o equivalent formulas (for NMOS devices; similar for PMOS):
2I D
g m  k nVOV  k n VGS  Vt  
 2k n I D ,
VGS  Vt
W
W
  n C ox
where k n  k n
L
L
o derivations of these formulas
- incremental drain-source resistance ro
o represents non-zero slope of iD-vDS characteristic in the saturation region
o typically 20-100 k for MOSFETs
o can be much lower for some types of FETs
V
o ro  A , where VA = Early voltage
ID
- effect of source degeneration resistor (RS) on gain
- common-source (CS) and common-drain (CD) amplifiers
Internal structure of bipolar junction transistor (BJT)
- npn: thin p-type base sandwiched between n-type emitter and collector
- pnp: opposite of npn
Qualitative understanding of operation of BJT
- turn-on voltage (VD0) of base-emitter junction (approx. 0.7 V for Si)
- effect of changing base current iB
- effect of changing collector-emitter voltage vCE
- directions and polarities of important currents and voltages (iB, iC, iE, vBE, vCE)
- thin base region required to allow electrons (npn) or holes (pnp) to flow from emitter
to collector
- emitter more heavily doped than base – allows base to fill with minority carriers when
base current flows
- base-emitter junction is forward biased if vBE is at turn-on voltage (VD0)
- i-v characteristic of B-E junction is the same as that of a pn-junction diode
- collector-base junction is usually reverse biased (produces depletion region) or lightly
forward biased
- collector current related to base current by iC = FiB in the active region
- F = forward DC current gain (values are typically 20-300, but vary among BJT
types, even among individual units of a given type within the same manufacturing
batch)
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BJT i-v characteristic (iC vs. vCE for selected values of iB)
- cut-off region (vBE < VF, where VF = turn-on voltage of BE junction; iB = iC = 0)
- active (constant-current) region (iC = iB)
- saturation region (vCE ≈ 0.2-0.3 V and iC < iB, but iC is nonzero)
npn vs. pnp BJTs
- circuit symbols (arrow indicates emitter; arrow of npn is “not pointing in”)
- vBE, and vCE of pnp BJTs have negative values in normal operation
- iB and iC flow out of base and collector terminals of pnp BJTs
- i-v characteristics of npn and pnp BJTs have voltages of opposite sign
General analysis techniques for BJT circuits
- determination of region of operation (cutoff, active, or saturation)
- vCE (for npn BJTs) is always positive (negative for pnp)
- graphical analysis techniques (load lines) can be applied
- vBE = 0.7 V (for npn) in the active and saturation regions
- in active region, iC = iB
- in saturation region, vCE = vCE|sat ≈ 0.2-0.3 V and iC < iB
BJT inverter circuits
- can be used as logical NOT gates
- transfer characteristic (vo vs. vin) has negative slope (or zero slope in some regions)
- BJT version is also called a common-emitter amplifier
- has an almost linear transfer characteristic in active region
BJT biasing circuits
- design for quiescent output voltage, collector current, and/or voltage drop across
emitter resistor (if present)
- usually bias BJT for operation in the active region
- must pay attention to swing range of vC (collector node voltage) to avoid cutoff and
saturation regions
o in cutoff region, iC = 0; also applies at the boundary between the cutoff and
active regions
o active-saturation boundary defined by (for npn devices): VCE activesat .  0.3 V
-
o the parameter  has strong temperature dependence and device variation
parameter-independent biasing (emitter degeneration) using “4-resistor” bias network
o makes use of negative feedback via emitter degeneration resistor
o consists of
 collector resistor, usually labeled RC
 emitter resistor, usually labeled RE
 base biasing “voltage divider,” often labeled R1 and R2; quotes because
IB ≠ 0 (i.e., R1 and R2 do not form a true voltage divider)
o current through R1 and R2 is typically designed to be 0.1 to 1 times IE (or
10-100 times IB)
o trade-off: higher current through R1 and R2 leads to more stable quiescent
point but lower input resistance and higher current demand from power supply
o key goal: try to keep quiescent voltage VB from varying significantly
o B JT in active region satisfies IC = IB
1
o common design rule of thumb: I C RC  I E RE  VCC , although the voltage
3
across RE is sometimes designed to be less than this
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-
-
o for analysis purposes, can represent base biasing network by a Thévenin
R2
equivalent circuit consisting of: VBB  VCC
and RB  R1 R2
R1  R2
o variation for bipolar (pos./neg.) power supplies: use RE and RC but only a
single resistor (RB) from base to ground
collector-to-base feedback resistor
o simpler than four-resistor network
o does not work well for wide variation in 
o improvement: add third resistor from base to ground
constant current sources also used for biasing
Relevant course material:
HW:
Labs:
Textbook:
Lecture notes:
Web Links:
Mathcad:
Matlab:
#8
#12
Sections 5.5, 5.6, 5.8; 6.1 through 6.4; 6.7
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