Download EEEE 482 Lab7 Rev2015 1 - RIT - People

EEEE 482 – Electronics II
Experiment #7: Propagation Delay in CMOS Circuits
Objective
The goal of this lab experiment is to explore CMOS inverter propagation delay (also called gate
delay). Propagation delay through a CMOS inverter will be calculated by hand and simulated using
SPICE. A CMOS ring oscillator will be analyzed, simulated using SPICE and then built and tested.
The resulting propagation delay results will be compared.
Introduction
The system speed is determined by many factors but the basic parameter that determines the speed of
the system is the individual gate propagation delay, td. The propagation delay is often used as a
figure of merit to compare different technologies. For example in 1997 IBM reported their measured
ring oscillator propagation delay of 9.5ps the fastest reported to date for CMOS at room temperature.
The definition of gate propagation delay is the average of tdHTL and the tdLTH for the output of a gate
(typically an inverter).
Thus: td = ½(tdLTH + tdHTL)
These times are so fast they are hard to measure so td is typically extracted from the measured period
of a ring oscillator. A ring oscillator is an odd number of inverters (N) in series with the output
connected back to the input, which will oscillate with period T.
thus:
td = T/2N
When a change is applied to the input(s) of a digital gate, such as a CMOS inverter, the output
cannot respond instantaneously. In order for the voltage at the output node to change, gate internal
capacitance must be charged or discharged. However, we know from circuit theory that a capacitor
cannot be charged or discharged instantaneously — it would require an infinite amount of energy to
do so. Instead, current flows into or out of a capacitor, and the instantaneous voltage across the
capacitor is related to the instantaneous current by this familiar relationship:
dv t 
it   C C . (if C is constant.)
dt
The time that it takes to achieve a given voltage change across a capacitor can be approximated as
CV
t 
I avg
where Iavg is the average current flowing to/from the capacitor. In the inverter the current to or from
the output node is through the PMOS or NMOS transistor to the internal capacitance at the output
node.
The propagation delay td through a logic gate, then, is determined by the magnitude of the
capacitance that must be charged/discharged, the required voltage swing, and the available current.
When the output is transitioning from its low state (VOL) to its high state (VOH), the low-to-high
propagation delay tdLTH is taken to be the time required for Vout to rise from VOL to V50%, where V50%
V  VOH
is the halfway point between VOL and VOH — i.e., Vs or V50%  OL
. Likewise, when the
2
output is transitioning from VOH to VOL, the high-to-low propagation delay tdHTL is taken to be the
time required for Vout to fall from VOH to V50%. These definitions assume rapidly rising or falling
inputs, and must be refined somewhat for more realistic input waveforms.
The internal capacitors for a MOSFET are associated with the gate-to-channel, Gate overlap with the
Drain, Source and substrate, and the source and drain junction capacitance to the substrate. The
values of these capacitors depend on the length, L, width, W, Overlap in the length and width
directions, Area and perimeter of the drain and source. Further, these capacitors change with voltage
(with junction space charge width) and with the circuit topology including voltage gain Miller
capacitance. The models are complex however this complexity is imbedded in the more advanced
SPICE models used for simulation.
The calculation of the internal capacitance of a CMOS gate is explained in detail in your textbook
and lecture notes. For the transistors we will use in lab, inside the CD4007 chip, we can use a value
of ~2pF for the inverter internal capacitance, Cint. Cint is the sum of the inverter input capacitance,
Cin and the inverter output capacitance, Cout. This does not include other unknown capacitance such
as that associated with the input and output pad driver, electrostatic discharge circuitry (ESD),
wiring, etc. This capacitance will be called the load capacitance, CLoad, and has a value of ~23pF
for the CD4007 chip. The total capacitance at the output node for each inverter with a fan out of 1
will be called the effective internal capacitance, Ceff which is Cint + CLoad, and has a value of ~25pF
SPICE models for the transistors in the CD4007 chip are provided.
Electronics II – EEEE 482 — Lab #7: Probagation Delay in CMOS Circuits — Rev 2015_1
Rochester Institute of Technology
Page 2 of 12
Dr. Lynn Fuller, et.al.
Pre-Lab Before coming to lab, do all of the following (Parts (1)–(4)):
Part 1: Analysis of a CMOS Inverter’s Propagation Delay
Calculate the propagation delay for the inverter in Fig. 1.
M2
CD4007P7
Cint
M1
V2
V1
10 Vdc
CD4007N7
Figure 1. CMOS Inverter
The propagation delay tdLTH for a CMOS inverter can be calculated as:
td LTH = Cint V / Iave
where Iave is the average current through the PMOS, for low to high, and NMOS, for high to low,
transitions. V is ½ of the supply voltage and Cint is the inverter internal capacitance, ~2pF for the
CD4007 inverters, not including the internal capacitance associated with the ESD circuitry, pad
driver circuitry, wiring, etc. which is approximately 23pF.
 Use the NMOS and PMOS transistor data provided and calculate the expected propagation
delays, tdLTH and tdHTL. Use an effective internal capacitance value of 25 pF. Compare your
calculated values to the 30 ns value from the CD4007 data sheet. You shouldn’t expect perfect
agreement, but they should agree to within a factor of two or three.
 Calculate approximate propagation delays, tPHL and tPLH, using the text approach of treating the
NMOS device as an effective resistance of 12.5 kΩ/□ and the PMOS device as an effective
resistance of 30 kΩ/□, respectively. Use a load capacitance value of 25 pF, as well as the W and
L values given above for the CD4007 NMOS and PMOS devices. Compare your calculated
values to the 30 ns value from the CD4007 data sheet and to your calculated values from above.
Note: this approach will not work very well because the width of the transistors is very large
giving channel resistances that are small as a result the series resistances in the drain and source
cannot be neglected and should be added to the channel resistance. Use a total of 1000 ohms for
the resistance of the drain plus resistance of the source.
Electronics II – EEEE 482 — Lab #7: Probagation Delay in CMOS Circuits — Rev 2015_1
Rochester Institute of Technology
Page 3 of 12
Dr. Lynn Fuller, et.al.
Part 2: Analysis of a CMOS Ring Oscillator
Relate the period of a ring oscillator to properties of individual inverter stages.
VDD = 10 V
IC1
IC=10
25 pF
25 pF
25 pF
25 pF
25 pF
Figure 2. Five-Stage Ring Oscillator
A five-stage ring oscillator is shown in Figure 2. Each stage is comprised of a CMOS inverter like
the one shown in Figure 1. The output node of every inverter stage has a number of internal
capacitances connected to it — e.g., the drain-to-substrate junction capacitance of both the NMOS
and the PMOS devices. Additionally, the output of a given inverter stage is driving the succeeding
inverter in the ring and all the capacitance associated with that input node. In addition there is
capacitance associated with the ESD circuitry, wiring, etc. The 25 pF capacitance attached to the
output node of every inverter stage in Figure 2 represents the effective capacitance at that node, Ceff,
the combined MOSFET internal capacitance, the input capacitance of the next inverter, and the
capacitance associated with the ESD circuitry, pad driver circuitry, wiring, etc.
In order to measure the effective load capacitance Ceff at the output of a single inverter stage,
additional external capacitance Cext can be added at each output, as shown in Figure 3. This
increases the total load capacitance at each driven output node by the same amount and has a direct
impact on the measured delay per gate. Comparison of the delay per gate with and without the
additional known external capacitance Cext leads directly to an estimate of the effective inherent
capacitance Ceff at the output of the inverter stage.
VDD = 10 V
IC1
IC=10
(Ceff)
25 pF Cext
(Ceff)
25 pF Cext
(Ceff)
25 pF Cext
(Ceff)
25 pF Cext
(Ceff)
25 pF Cext
Figure 3. Five-Stage Ring Oscillator with Additional Load Capacitance Cext
 Derive a simple equation that relates the propagation delay td through a single inverter stage to
the period T of the measured ring oscillator signal and the number N of inverter stages
 Derive a simple equation that relates the ring oscillator period, T1, to the internal effective
capacitance, Ceff, at the output node of each inverter. A second equation relating ring oscillator
period, T2, with both Ceff and an external capacitor, Cext, at the output of each inverter can be
combined with the first equation to give a single equation with Cint, Cext, T1 and T2 which will be
used to find Cint knowing Cext, T1 and T2.
Electronics II – EEEE 482 — Lab #7: Probagation Delay in CMOS Circuits — Rev 2015_1
Rochester Institute of Technology
Page 4 of 12
Dr. Lynn Fuller, et.al.
Part 3: SPICE Simulation of a CMOS Ring Oscillator
Compare hand calculations from the analysis of a ring oscillator to SPICE simulation.
Use the SPICE models for the transistors in the CD4007 chip. Add the additional 23pF to each
inverter output node to represent the capacitance of the ESD circuitry, pad driver circuitry, wiring,
etc. Create the schematic with the MbreakN and MbreakP transistors in the BREAKOUT library.
Change the name from MbreakN to RIT4007N7 and MbreakP to RIT4007P7. Edit the properties for
each transistor using the L, W, Ad, As, Pd, Ps given in the SPICE model text file and choose to
display on the schematic.
Create a simulation profile, giving it a name of your choosing. Choose the analysis type to be Time
Domain (Transient), and chose the time increment to provide good resolution, with the duration of
the simulation chosen taking the calculations of Parts (1) and (2) into consideration. Under the
configuration Files tab select Include and browse to the location on your computer of the text file
that has the SPICE models (RIT_Models_For_LTSPICE.txt) that you have downloaded from Dr.
Fuller’s webpage, Add to Design.
 Run the simulation (of the circuit in Figure 2) and view the results. Use your analysis from Part
(2) to relate your measured period T to the propagation delay per inverter stage, tP.
Electronics II – EEEE 482 — Lab #7: Probagation Delay in CMOS Circuits — Rev 2015_1
Rochester Institute of Technology
Page 5 of 12
Dr. Lynn Fuller, et.al.
Make sure that you save/print any schematic diagrams and simulation results that are needed
before modifying your circuit!!
 Re-run the simulation for a total of three different VDD values: 5V, 7.5V and 10V. From the
simulated waveform, determine the delay per stage and compare the three delay values that you
have obtained thus far. Does the delay per stage scale proportionately to VDD? Briefly explain
why or why not.
 Reset VDD (and IC1) to 10 V. Edit your circuit and add Cext = 47 pF to each output node (in
addition to the 25pF). The location of Cext is shown in Figure 3. Run the simulation and view the
results. Using the analysis done in Part (2), determine the value of the inherent effective load
capacitance, Ceff. Compare this result to the known value of 25 pF that was used for Ceff in the
simulation to verify that the relationship between Cext and Ceff was correctly derived.
Part 4: Preparation for Building and Testing a CMOS Ring Oscillator
Determine in advance the wiring connections required for building a CMOS ring oscillator.
The pin-out diagram and specifications for the CD4007 chip are shown in Figure 4(b). A larger,
more legible version of the pin-out diagram is shown in Figure 4(a). Study the pin-out diagram
carefully, making sure you understand the various substrate and source pin-out locations. Note that
the source and substrate for each of the leftmost NMOS and PMOS devices are hard-wired together.
 Sketch the transistor-level schematic of the CMOS ring oscillator (as in Figure 2) and indicate on
your diagram the corresponding pins on the CD4007 chips. You will need to use two CD4007
chips. Take care to ensure that all NMOS substrate (body) connections are wired to the lowest
system supply voltage — in this case, ground — and that all PMOS substrate connections are
wired to the highest system supply voltage — in this case, VDD.
Electronics II – EEEE 482 — Lab #7: Probagation Delay in CMOS Circuits — Rev 2015_1
Rochester Institute of Technology
Page 6 of 12
Dr. Lynn Fuller, et.al.
Lab — Measurement of Ring Oscillator Gate Delay
In this lab, we will build and measure certain characteristics of a CMOS ring oscillator using
CD4007 chips. Refer to Figures 4(a) and 4(b) for the CD4007 chip pin-out. There are three NMOS
and three PMOS devices on each chip. Pay particular attention to the substrate connections for the
NMOS and PMOS devices, pins 7 and 14, respectively. Note that the p-substrate connection (pin 7)
is common to the three NMOS devices; also, the n-substrate connection (pin 14) is common to the
three PMOS devices.
Required Electronic Components:
2 — CD4007 chips
5 — 47 pF capacitors
14
2
13
1
6
11
10
3
8
5
7
4
12
9
Figure 4(a). Enlarged CD4007 Pin-Out Diagram
Electronics II – EEEE 482 — Lab #7: Probagation Delay in CMOS Circuits — Rev 2015_1
Rochester Institute of Technology
Page 7 of 12
Dr. Lynn Fuller, et.al.
Figure 4(b). CD4007 Pin-Out and Specifications
Electronics II – EEEE 482 — Lab #7: Probagation Delay in CMOS Circuits — Rev 2015_1
Rochester Institute of Technology
Page 8 of 12
Dr. Lynn Fuller, et.al.
Figure 4(c). Additional CD4007 Data Sheet Specifications
Electronics II – EEEE 482 — Lab #7: Probagation Delay in CMOS Circuits — Rev 2015_1
Rochester Institute of Technology
Page 9 of 12
Dr. Lynn Fuller, et.al.
CD4007 SPICE MODELS
*Used in Electronics II for CD4007 inverter chip
*Note: Properties L=10u W=170u Ad=8500p As=8500p Pd=440u Ps=440u NRD=0.1 NRS=0.1
.MODEL RIT4007N7 NMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=4E-8 XJ=2.9E-7 NCH=4E15 NSUB=5.33E15 XT=8.66E-8
+VTH0=1.4 U0= 1300 WINT=2.0E-7 LINT=1E-7
+NGATE=5E20 RSH=300 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-8 MJ=0.5 PB=0.95
+CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5
+CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10)
*
*Used in Electronics II for CD4007 inverter chip
*Note: Properties L=10u W=360u Ad=18000p As=18000p Pd=820u Ps=820u NRS=0.54 NRD=0.54
.MODEL RIT4007P7 PMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=5E-8 XJ=2.26E-7 NCH=1E15 NSUB=8E14 XT=8.66E-8
+VTH0=-1.65 U0= 400 WINT=1.0E-6 LINT=1E-6
+NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-8 MJ=0.5 PB=0.94
+CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 PCLM=5
+CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10)
Measured ID versus VD Family of Curves
Electronics II – EEEE 482 — Lab #7: Probagation Delay in CMOS Circuits — Rev 2015_1
Rochester Institute of Technology
Page 10 of 12
Dr. Lynn Fuller, et.al.
(Parts (1)–(4) were done as part of the Pre-Lab preparation)
Part 5: CMOS Ring Oscillator
Build the CMOS ring oscillator shown in Figure 5 using two CD4007 chips. Refer to your
schematic diagram prepared in Part (4) of the pre-lab work, which shows appropriate pin
connections for constructing the circuit. The 25 pF capacitances shown in Figure 2 represent
parasitic and load capacitances for simulation purposes, and should not be included in the
assembled hardware circuit of Figure 5 since they are inherently part of the devices used to
build the circuit.
VDD
Figure 5. Five-Stage Ring Oscillator
 Make sure that you have correctly wired the circuit before proceeding.
 For three values of VDD — 5 V, 7.5 V, and 10 V — measure the period of the ring oscillator
signal and calculate the three corresponding per-gate delay values. Compare these values to your
expected values from hand calculations and simulations.
 Set VDD = 10 V if it is not already. Add Cext = 47 pF capacitance to every inverter stage’s output
node, as shown in Figure 6. Measure the period of the ring oscillator and calculate the
corresponding delay per gate. Use this loaded delay value and the unloaded delay value from
your previous measurement at VDD = 10 V to determine the inherent effective capacitance, Ceff.
(Use the relationship developed in Part (2) of the pre-lab work.)
VDD = 10 V
Cext
Cext
Cext
Cext
Cext
Figure 6. Five-Stage Ring Oscillator with Additional Load Capacitance Cext
Electronics II – EEEE 482 — Lab #7: Probagation Delay in CMOS Circuits — Rev 2015_1
Rochester Institute of Technology
Page 11 of 12
Dr. Lynn Fuller, et.al.
Tech Memo
Summarize the hand calculations of propagation delays through the CMOS inverter. Compare the
CV
values obtained by (1) t 
analysis, and (2) effective resistance-based calculations to each
I avg
other and to expected delay values.
Summarize the relationships derived for the ring oscillator circuit that allow the determination of
(1) the delay per inverter stage, and (2) the effective load capacitance, Ceff. Summarize the results of
your simulations with respect to (1) the effect of VDD on delay per stage, and (2) the impact of
additional load capacitance, Cext.
Include diagrams and calculations required in the pre-lab preparation. Summarize the results from
your experimental measurements of the CMOS ring oscillator circuit. All information detailed on
the check-off sheet should be included in a logical and professionally-organized fashion and should
be briefly discussed.
Check-Off Sheet
A. Pre-Lab
 Analysis of CMOS inverter dynamic behavior: (a) calculation of propagation delays tdLTH
CV
and dPTHL from t 
approach; (b) calculation of propagation delays tPTLH and tdHTL
I avg
from effective resistance approach; (c) comparison of delay values obtained from the two
methods to expected values.
 Analysis of CMOS ring oscillator: (a) relationship of propagation delay per gate to the
period T of the measured ring oscillator signal and the number N of inverter stages;
(b) relationship of effective load capacitance Ceff at the output of a single inverter stage to the
delay per stage without external capacitive load, tdelay(no load), the delay per stage with external
capacitive load, tdelay(load), and the amount of external capacitive load per stage, Cext.
 Simulation of CMOS ring oscillator: (a) schematic; (b) output waveforms showing proper
operation of the circuit; (c) results from simulated VDD variations (d) results from simulation
of additional load capacitance, Cext — calculate the effective load capacitance Ceff at the
output of each inverter stage and verify the proper derivation of the Ceff relationship.
 Preparation for CMOS ring oscillator construction: schematic diagram with CD4007 pin
numbers indicated for all transistor nodes.
B. Experimental
 CMOS ring oscillator circuit: (a) output waveforms for VDD variations; (b) delay per
inverter stage for VDD variations; (c) output waveform for VDD = 10 V with additional 47 pF
load capacitance, Cext; (d) calculated value of inherent effective load capacitance, Ceff.
Electronics II – EEEE 482 — Lab #7: Probagation Delay in CMOS Circuits — Rev 2015_1
Rochester Institute of Technology
Page 12 of 12
Dr. Lynn Fuller, et.al.