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OUTPUT Pad and Driver CONCORDIA VLSI DESIGN LAB 1 CLOCK DRIVER CONCORDIA VLSI DESIGN LAB 2 Buffering S = scaling or tapering factor CL = SN+1 Cg ……………… CONCORDIA VLSI DESIGN LAB All inverters have identical delay of to = delay of the first stage (load =Cd+Cg) 3 Buffering If the diffusion capacitance Cd is neglected, S = e = 2.7 5 S 4 3 0 1 2 3 Cd/Cg CONCORDIA VLSI DESIGN LAB 4 Layout of Large Device CONCORDIA VLSI DESIGN LAB 5 Large Transistor Layout CONCORDIA VLSI DESIGN LAB 6 Output Drivers Standard CMOS Driver Open Drain/Source Driver: Single Transistors Tri-state Driver Bi-directional Circuit CONCORDIA VLSI DESIGN LAB 7 Tri-state Driver Tri-state or High impedance Used to drive internal or external busses Two inputs: Data In and Enable Various signal assertions En Two types: In C2MOS En CMOS with Control Logic VDD Out C2MOS CONCORDIA VLSI DESIGN LAB 8 Tri-state Driver VDD Control logic could be modified to obtain En Inversion/non-inversion Active low/high Enable Out For large load, pre-drivers are required PAD En In CONCORDIA VLSI DESIGN LAB 9 Latch-up: Trigger Factors which trigger latch-up transmission line reflections or ringing voltage drop on the VDD bus “hot plug in” of unpowered circuit board electrostatic discharge sudden transient on power and ground busses leakage current across the junction radiation: x-ray, cosmic CONCORDIA VLSI DESIGN LAB 10 Input PAD CONCORDIA VLSI DESIGN LAB 11 Protection Circuitry Principles Punch Through CONCORDIA VLSI DESIGN LAB Avalanche 12 Protection Circuitry CONCORDIA VLSI DESIGN LAB 13 Protection Circuitry CONCORDIA VLSI DESIGN LAB 14 Input protection Electrostatic discharge can take place through transfer of charges from the human body to the device. Human body can carry up to 8000V. Discharge can happen within hundreds of nanoseconds. Critical field for SiO2 is about 7X106 V/cm. For 0.5u CMOS process the gate oxide can withstand around 8V Some protection technique is required with minimum impact on performance 1.5K 1M Vesd DUT 100pF Human Body model CONCORDIA VLSI DESIGN LAB 15 ESD Structures Basic technique is to include series resistance and two clamping diodes. The resistance R is to limit the current and to slow down the high voltage transitions. R could be polysilicon or diffusion resistance Diffusion resistance could be part of the diode structure Typical values of R: 500 to 1k VDD R PAD CONCORDIA VLSI DESIGN LAB 16 Layout of ESD Structure This structure uses transistors as clamping diodes PAD n+ p+ Guard Ring Guard Ring p+ p+ CONCORDIA VLSI DESIGN LAB n+ n+ 17 Layout of ESD Structure VDD PAD n+ p+ Guard Ring Guard Ring p+ p+ n+ n+ GND CONCORDIA VLSI DESIGN LAB 18 Another ESD Structure VDD PAD R1 R2 Thick FOX MOS Transistor CONCORDIA VLSI DESIGN LAB 19 Bi-direct PAD VDD Pre-drivers IN EN ESD Protection Input Buffer Control Logic CONCORDIA VLSI DESIGN LAB PAD 20 Thank you ! CONCORDIA VLSI DESIGN LAB 21