Download CSE 431. Computer Architecture

CSE 431
Computer Architecture
Fall 2005
Lecture 01: Introduction
Mary Jane Irwin ( www.cse.psu.edu/~mji )
www.cse.psu.edu/~cg431
[Adapted from Computer Organization and Design,
Patterson & Hennessy, © 2005, UCB]
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Course Content
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Content
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Course goals
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Principles of computer architecture: CPU datapath and control
unit design (single-issue pipelined, superscalar, VLIW),
memory hierarchies and design, I/O organization and design,
advanced processor design (multiprocessors and SMT)
To learn the organizational paradigms that determine the
capabilities and performance of computer systems. To
understand the interactions between the computer’s
architecture and its software so that future software designers
(compiler writers, operating system designers, database
programmers, …) can achieve the best cost-performance
trade-offs and so that future architects understand the effects of
their design choices on software applications.
Course prerequisites

CSE 331. Computer Organization and Design
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What You Should Know - CSE271 and CSE331
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Basic logic design & machine organization
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Create, assemble, run, debug programs in an
assembly language
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logical minimization, FSMs, component design
processor, memory, I/O
MIPS preferred
Create, simulate, and debug hardware structures in a
hardware description language
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VHDL or verilog
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Create, compile, and run C (C++, Java) programs
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Create, organize, and edit files and run programs on
Unix/Linux
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Course Structure
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Design focused class
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Various homework assignments throughout the semester
Simulation of architecture alternatives using SimpleScalar
Lectures:
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2 weeks review of the MIPS ISA and basic architecture
2 weeks pipelined datapath design issues
3 weeks superscalar/VLSI datapath design issues
2 week memory hierarchies and memory design issues
2 weeks I/O design issues
2 weeks multiprocessor design issues
1 week exams
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How Do the Pieces Fit Together?
Application
CSE 421
Compiler
Memory
system
Operating
System CSE 411
Firmware
Instr. Set Proc.
Instruction Set
Architecture
I/O system
CSE 331 & 431 & 472
Datapath & Control
CSE 447 & 477
Digital Design CSE 271 & 471 & 478
Circuit Design
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Coordination of many levels of abstraction
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Under a rapidly changing set of forces
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Design, measurement, and evaluation
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Where is the Market?
Millions of Computers
1200
1122
1000
892
Embedded
Desktop
Servers
862
800
600
488
400 290
200
0
93
3
1998
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114
3
1999
135
4
2000
129
4
2001
131
5
2002
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By the architecture of a system, I mean the complete and
detailed specification of the user interface. … As
Blaauw has said, “Where architecture tells what
happens, implementation tells how it is made to
happen.”
The Mythical Man-Month, Brooks, pg 45
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Instruction Set Architecture (ISA)
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ISA: An abstract interface between the hardware and the
lowest level software of a machine that encompasses all
the information necessary to write a machine language
program that will run correctly, including instructions,
registers, memory access, I/O, and so on.
“... the attributes of a [computing] system as seen by the
programmer, i.e., the conceptual structure and functional
behavior, as distinct from the organization of the data flows and
controls, the logic design, and the physical implementation.”
– Amdahl, Blaauw, and Brooks, 1964
 Enables implementations of varying cost and performance to run
identical software
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ABI (application binary interface): The user portion of the
instruction set plus the operating system interfaces used
by application programmers. Defines a standard for
binary portability across computers.
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ISA Type Sales
Other
SPARC
Hitachi SH
PowerPC
Motorola 68K
MIPS
IA-32
ARM
1400
Millions of Processor
1200
1000
800
600
400
200
0
1998
1999
2000
2001
2002
PowerPoint “comic” bar chart with approximate values (see
text for correct values)
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Moore’s Law
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In 1965, Gordon Moore predicted that the number of
transistors that can be integrated on a die would double
every 18 to 24 months (i.e., grow exponentially with
time).
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Amazingly visionary – million transistor/chip barrier was
crossed in the 1980’s.
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2300 transistors, 1 MHz clock (Intel 4004) - 1971
16 Million transistors (Ultra Sparc III)
42 Million transistors, 2 GHz clock (Intel Xeon) – 2001
55 Million transistors, 3 GHz, 130nm technology, 250mm2 die
(Intel Pentium 4) - 2004
140 Million transistor (HP PA-8500)
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Processor Performance Increase
Performance (SPEC Int)
10000
Intel Pentium 4/3000
DEC Alpha 21264A/667
DEC Alpha 21264/600
Intel Xeon/2000
1000
DEC Alpha 4/266
100
DEC AXP/500
DEC Alpha 5/500
DEC Alpha 5/300
IBM POWER 100
HP 9000/750
10
IBM RS6000
SUN-4/260
MIPS M2000
MIPS M/120
1
1987
1989
1991
1993
1995
1997
1999
2001
2003
Year
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DRAM Capacity Growth
512M
256M
128M
1000000
64M
Kbit capacity
100000
16M
10000
4M
1M
1000
256K
64K
100
16K
10
1976 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002
Year of introduction
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Impacts of Advancing Technology
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Processor
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logic capacity:
performance:
increases about 30% per year
2x every 1.5 years
ClockCycle = 1/ClockRate
500 MHz ClockRate = 2 nsec ClockCycle
1 GHz ClockRate = 1 nsec ClockCycle
4 GHz ClockRate = 250 psec ClockCycle
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Memory
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DRAM capacity: 4x every 3 years, now 2x every 2 years
memory speed: 1.5x every 10 years
cost per bit:
decreases about 25% per year
Disk
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capacity:
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increases about 60% per year
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Example Machine Organization
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Workstation design target
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25% of cost on processor
25% of cost on memory (minimum memory size)
Rest on I/O devices, power supplies, box
Computer
CPU
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Memory
Devices
Control
Input
Datapath
Output
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PC Motherboard Closeup
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Inside the Pentium 4 Processor Chip
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MIPS R3000 Instruction Set Architecture
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Registers
Instruction Categories
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Load/Store
Computational
Jump and Branch
Floating Point
-
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R0 - R31
coprocessor
PC
HI
Memory Management
Special
LO
3 Instruction Formats: all 32 bits wide
OP
rs
rt
OP
rs
rt
OP
rd
sa
funct
immediate
jump target
Q: How many already familiar with MIPS ISA?
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Next Lecture and Reminders
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Next lecture
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MIPS ISA Review
- Reading assignment – PH, Chapter 2
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Reminders
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HW1 out next lecture, due September 13th
Evening midterm exam scheduled
- Tuesday, October 18th , 20:15 to 22:15, Location 113 IST
- Please let me know ASAP (via email) if you have a conflict
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