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ABSTRACT
Title of Thesis:
DESIGN OF PIXEL LEVEL CMOS
READOUT CIRCUITRY FOR
CONTINUOUS BIAS UNCOOLED
BOLOMETRIC LWIR FOCAL PLANE
ARRAYS
Troy Alexander Chesler, Master of Science,
2004
Thesis Directed By:
Professor Martin Peckerar, Department of
Electrical and Computer Engineering
Modern IC foundries do not provide large analog storage capacitors and
therefore limit the charge well capacity for modern LWIR infrared readout integrated
circuits. A technique for increasing the effective capacity and integration times while
maintaining linearity for a continuous biased bolometric LWIR focal plane arrays is
presented. Increasing integration times in the pixel reduces noise bandwidth and
effectively increases dynamic range without saturating the integration capacitor.
Background suppression techniques, such as current skimming and charge subtraction
reduce the overall temporal noise by subtracting the DC input current. This thesis
addresses the following: a) the practicality of continuous bias uncooled pixel designs
b) optimum skimming implementation and c) the impact of background suppression
on temporal and spatial noise.
ii
DESIGN OF PIXEL LEVEL CMOS READOUT CIRCUITRY FOR CONTINUOS
BIAS UNCOOLED BOLOMETRIC LWIR FOCAL PLANE ARRAYS
By
Troy Alexander Chesler
Thesis submitted to the Faculty of the Graduate School of the
University of Maryland, College Park, in partial fulfillment
of the requirements for the degree of
[Master of Science]
[2004]
Advisory Committee:
Professor Martin Peckerar, Chair
Professor Pamela Abshire
Professor Timmer Horiuchi
iii
© Copyright by
[Troy Alexander Chesler]
[2004]
iv
Acknowledgements
1) Family
2) Jon Pfeifer
3) Tyler Erickson
4) Philippe Pouliquen
5) Tobi Delbruck
6) NVESD(Paul Blasé, Dr. Paul Norton, Kent McCormack, and Dieter
Lohrmann)
7) UMD (Marty, Pam, and Timmer)
5
Lists of Tables, Figures / Illustrations
Begin Here
6
Table of Contents
Acknowledgements ................................................................................................. 5
Table of Contents .................................................................................................... 7
Chapter 1: Uncooled Infrared Imaging ................................................................... 9
Thesis Contributions: .......................................................................................... 9
Background ......................................................................................................... 9
Origins of Uncooled Thermal Imaging ................................................................ 9
Military & Commercial Developments .............................................................. 9
Bolometer Operation ......................................................................................... 11
Pulse Biased .................................................................................................... 15
DC Biased....................................................................................................... 16
Temperature Sensitive Resistive Materials ....................................................... 17
Vanadium Oxide (VO2).................................................................................... 17
Amorphous Silicon (-Si) ................................................................................ 18
Uncooled Systems: Figures of Merit ................................................................ 19
Responsivity ................................................................................................... 19
NEP................................................................................................................ 20
D* ................................................................................................................... 20
NET & TCR ................................................................................................. 20
Thermal Time Constant ................................................................................... 22
Chapter 2: Fundamentals of Infrared Imaging ...................................................... 23
Introduction ....................................................................................................... 23
Wavelength Spectrum & Atmospherics............................................................ 26
Readout Systems ............................................................................................... 27
Chapter 3: Background Suppression in the LWIR ............................................... 33
Justification for Current Skimming & Charge Subtraction .............................. 33
Spatial & Temporal Noise ................................................................................ 34
Sensitivity & Dynamic Range .......................................................................... 36
DC Suppression Concepts ................................................................................ 38
Current Skimming............................................................................................. 45
Fundamentals .................................................................................................. 45
Self-Biased Cascode Origin & Fundamentals .................................................... 46
Analysis of Pixel Circuitry................................................................................ 53
DC Bias Point of DI FET ................................................................................. 53
Conductances of DI FET .................................................................................. 60
DC Bias Point of SCFET ................................................................................. 62
Conductances of SCFET .................................................................................. 62
Single MOS Skimming Pixel ............................................................................ 62
Self-Cascode Skimming Pixel .......................................................................... 62
Self-Cascode with MOS Capacitor ................................................................... 62
Pixel Comparisons ........................................................................................... 62
Charge Subtraction Concept with Non-Linear MOSCAP .............................. 62
MOS Capacitor System .................................................................................... 62
Circuit Description .......................................................................................... 62
7
Chapter 4: Associative Issues & Limitations with Current Skimming ................. 63
Subthreshold Transistor Mismatch ................................................................... 63
Subthreshold Region Operation ........................................................................ 65
Current Mismatch vs. Voltage Mismatch........................................................... 67
Body Effect in Self-Cascode ............................................................................ 69
Effects of MOS Scaling .................................................................................... 71
Power Supply .................................................................................................. 72
Gate Oxide Thickness ...................................................................................... 73
Layout &Geometry of SCFET ......................................................................... 74
Noise ................................................................................................................. 77
Temporal Noise ............................................................................................... 78
Spatial Noise ................................................................................................... 78
Sensitivity ......................................................................................................... 79
NET ............................................................................................................. 80
Bolometer Bias Variations ............................................................................... 81
Chapter 5: Signal & Noise ................................................................................... 82
Signal ................................................................................................................ 82
Bolometer Transfer Function ............................................................................ 82
Pixel Transfer Function .................................................................................... 82
Noise Sources.................................................................................................... 82
Flicker Noise ................................................................................................... 83
Shot Noise ...................................................................................................... 84
Reset Noise ..................................................................................................... 85
Thermal Noise................................................................................................. 88
Theoretical Noise Analysis ............................................................................... 88
Single MOS .................................................................................................... 88
Self-Cascode Current Mode Skimmer ............................................................... 88
Chapter 6: IC Test CHIP Design ......................................................................... 89
IRCHIP1 ........................................................................................................... 89
Chip Description & Function ............................................................................ 89
Simulation & Test Results ................................................................................ 92
IRCHIP2 ........................................................................................................... 99
Chip Description & Function ............................................................................ 99
Test Results .................................................................................................... 99
IRCHIP3 ........................................................................................................... 99
Chip Desription & Function ............................................................................. 99
Test Results .................................................................................................... 99
Future Considerations ......................................................................................... 100
Conclusion .......................................................................................................... 101
References ........................................................................................................... 102
8
Chapter 1: Uncooled Infrared Imaging
Thesis Contributions:



Development and demonstration of appropiate scaling techniques for selfbiased cascode transistors.
Designed a novel long wave infrared readout current skimming pixel
specifically for continuous bias uncooled bolometer focal plane arrays.
Introduced charge subtraction as another alternative for background
suppression as well as combining this with current skimming.
Background
Origins of Uncooled Thermal Imaging
Feeling heat waves emitted from hot objects yet seeing no visible light
gave clues to early scientists that light is a form of radiation and exists beyond our
eye’s response range. These heat waves emanating from a recently distinguished
fire, a hot rock, or molten iron ore elucidated the emissive nature of
“invisible”(infrared) light.
Military & Commercial Developments
Before World War II, there had been considerable research for uncooled
imaging systems including sensing materials, electrical readout, and system
packaging. The two most prominent areas of uncooled materials research are 1)
ferroelectric & pyroelectric bolometry and 2) resistive bolometry [1]. The
pyroelectric effect (not covered in this study) is a result of electrical polarization
of opposing faces on certain types of polarized crystals that can have a “transient”
electrical charge induced by means of a change in temperature [2]. The resistive
bolometer, which is the detector of choice for this study, is essentially a
9
temperature sensitive resistor. As the resistor absorbs electromagnetic radiation it
heats up and changes its electrical properties thus changing the electrical
resistance. Usually, the material will be a thin metal or semiconductor film
suspended over a air gap to provide adequate thermal isolation and minimize
thermal conductance to its surroundings. The thin film temperature rises when
radiations impinges on the detector element. With a rise in detector temperature, if
the sensing film is a metal, the resistance increases while semiconductor film’s
resistance decreases. In the absence of radiation, the detector temperature
decreases which causes the resistance to decrease (metal) and increases
(semiconductor) [2]. For the remainder of this thesis, characterization of the
CMOS readout process will focus only the semiconductor resistive bolometric
detector.
Efforts began in the mid 1970’s to create room temperature 2-D imaging
arrays for both military and commercial applications. At the time, cooled arrays
had much better performance. However, for most staring applications NET’s
(discussed later) of 0.01 K to 0.1 K with f/1 optics would be adequate for most
military applications [4]. 1983 marked the year for Honeywell’s vanadium oxide
(VOx) bolometric arrays implementing a solid-state readout. This was one of the
first attempts of a silicon MEMS device, (Micro-Electro-Mechanical System)
which promised to offer a new era of low cost monolithic imaging arrays. By
implementing silicon micro-machining, the highest thermal isolation could be
attained thus leading to high array performance [4]. Throughout the 70’s and 80’s,
most of this research was classified under DOD guidelines for the military. The
10
US Army Night Vision Laboratory (now NVESD) and DARPA saw a great
advantage for developing potentially low-cost monolithic uncooled infrared focal
plane arrays. Moving from bump bonding the detector array to the readout to a
monolithic approach improved the cost and yield of the array.
An important point that allowed uncooled infrared imaging to flourish
from the 80’s, 90’s, and up until 2004 was the rapid improvement of the silicon
process technologies (e.g. Moore’s Law). The move to using CMOS over mature
bipolar readouts provided better cost effective arrays with higher overall
performance advantages (e.g. lower power consumption). BiCMOS processes are
expensive and require several additional mask steps. Chief reasons for CMOS
over bipolar and BiCMOS for uncooled applications are: 1) effective cost 2)
availability 3) yield and 4) well defined and easy access to process parameters.
The industry standard is currently CMOS, however this does not discount bipolar
or BiCMOS readouts for future applications. Moore’s Law has scaled the device
dimensions to sub-micron levels and now 1000 x 1000 element arrays or greater
are realizable today. There are have been considerable advancements in MEMS
and material science providing extreme precision and high performance out of
uncooled infrared focal plane arrays.
Bolometer Operation
The mathematical expressions describing the physics of bolometer
operation are not the focus of this thesis. The process is governed by several
parameters and constants while being controlled by several partial differential
11
equations. Therefore, the mathematics will be kept to minimum and only used to
emphasize a point. If the reader is interested please consult sources [1,2,4].
The transduction of (long wave) infrared radiation into electrical signals is
described by the following two circuits. The following two circuits considered
explain different methods of bolometer operation. Figure 1.1a shows a constant
bias voltage VB and Figure 1.1b shows an ideal constant bias current IB.
IB
VB
Vb
Rbol
Ib
Figure1.1: a) Ideal constant bias
Rbol
b)Ideal constant current
The detector resistance is a function of temperature Rbol(T). In figure 1.1b
the potential drop appearing across the bolometer is Vb  Ib Rbol (Ohm’s Law).
Therefore a change in detector voltage due to a tiny change in bolometer
temperature is:
VB  I b
where   
dRbol
V dRbol
T  B
T  VBT
dT
Rbol dT
(1.1)
1 dR
is called the (TCR) temperature coefficient of resistance
R dT
(discussed in figures of merit section). From figure 1.1a, the current through the
bolometer is I b 
Vb
. A tiny change in bolometer current due to a tiny change in
Rbol
bolometer temperature results in:
12
Ib 
d  Vb

dT  Rbol

Vb dRbol
T   I bT
 T   2
R bol dT

(1.2)
The bolometer is governed by the following 1st order linear differential
equation (applying energy conservation) in (1.3). The goal now is to solve the
linear differential equation and determine T caused by a heat source from a
distant scene. The result may be substituted back into equations (1.1) and (1.2).
Cth





dT
 Gmech Tbol  Tsub   Ws  Vb I b
dt
(1.3)
Gmech is the total thermal conductance due to the bolometer support legs
Ws is power absorbed by the bolometer due to any radiation that
represents the interesting signal component. In infrared imaging systems,
Ws is dependent on camera optics, infrared passband, detector area,
absorption efficiency, and scene temperature variation.
Tbol is the bolometer temperature suspended over the readout and Tsub is
the underlying substrate temperature.
Cth is the total heat capacity of the bolometer. The bolometer is composed
of layers of individual material each with its own heat capacity.
VbIb is the power dissipated by the bolometer due to the bias current. This
is the unwanted signal and has no practical information content for the
readout to process.
Equation (1.3) has the well known solution which consists of the

t
homogeneous solution Ae where the time constant is  

Cth
. The
Gmech
particular solution caused by GmechTsub is Tsub . The temperature response due to
absorbed infrared radiation is governed by a first order low pass filter with a
3dB cutoff frequency of  3dB 
1

. The temperature response as a function of
frequency caused by a small amount of absorbed radiation is:
13
T  T ( ) 
Ws  
Gmech
1
1  j
(1.4)
where the absorbed infrared radiation signal Ws   is sufficiently small so
that it induces small temperature changes in the bolometer. Also, these small
changes are such that the current response of the bolometer is able to reach
steady state and establish an equilibrium point of operation. The current
response of figure 1.1a and b respectively is the following:
T
 W   1 
VB  VB  s
;
 Gmech 1  j 
T
 W   1 
I b   I b  s

 Gmech 1  j 
(1.5)
Take for example the following situation. We have a 50 um x 50 um pixel
with Gmech 10-7 W/K, no transmission loss and F/1 optics [Kruse, pg 50
reference Klein]. With a one degree scene temperature change (assumes
scene is a perfect black body) and the pass band is 8 um to 12 um, this causes
approximately a 10 mK change in bolometer temperature. If the TCR = 2.5%
and our desired resolution of scene temperatures is 20 mK we see a 200 uK
change in bolometer temperature. Therefore the ratio of changes in bias
voltage or current to either a bias voltage or current is:
Ib
VB
 T ;
 T
Vb
Ib
(1.6)
which says that T  (0.025)(2 x104 )  5 parts per million. Take the
situation for an uncooled bolometer operation at 300 K where the bias current
 20nA. Given the above information and using equation (1.2) we find that
14
the change in current as a result of a 200 uK change in bolometer temperature
with a 20 mK resolution the
I b  (20 109 )  (.  025%
K )  (200 10 6 K )  100 fA
The bolometer bias has two components:


Ib (DC bias current)
Ib (change is bolometer current as a result of infrared radiation)
The first term has no practical use for signal processing and also presents a
serious problem when considering an array of bolometers which have
variation in there resistances (process induced mismatch). This leads to a term
called fixed patter noise. The second current is the most important signal and
contains the relevant scene changes an actual infrared absorption. Therefore,
this thesis introduces a way to subtract the unwanted DC bias current and
integrate only the signal of interest. This method is known has current
skimming.
Pulse Biased
When large format arrays are fabricated, pulsed bias operation is the
usually used. However, detector current only flows within brief pulse durations.
In pulse biased systems, integration time is determined by the line read time
defined as:
 line 
 frame
(2.1)
 rows
For example, in a 640 x 480 array, at 60 Hz frame rate the line read time is
34.7 us. As a consequence, pulse biased integration times are not very long. In
15
pulse bias operation the detector resistances are in the range of 20-500 k. The
electrical bias (1 V or more) causes joule heating of the sensor as well as heat
from the incoming infrared radiation. The bolometer’s temperature rises several
degrees within the pulse duration. Thus in pulse bias operation there is no stable
equilibrium point. The infrared signal is several orders of magnitude lower than
the generated bias signal. Power dissipation for pulse bias operation is on the
order of 10-6 W.????????
DC Biased
Detector bias is continuously on so that a stable operating point is reached. Small
fluctuations in the observed scene induce the same fluctations around the
bolometer operating point set by DC bias across the bolometer. Detector
resistances are on the order of 10-60 M. We assume that the substrate which
houses the readout circuitry is thermally stabilized to some known temperature
reference we will call Tsub ( 300 K). We can view a series resistor from the
battery as its own internal resistance and will call this Rload. [BOLOMETER
CIRCUIT]With no radiation present, the initial dc current that flows through the
bolometer will heat up the resistor thus altering the resistance and raising the
bolometer temperature to Tbol. So now, without any infrared radiation we have a
temperature difference T1 = Tbol - Tsub. Adding IR radiation will further raise
bolometer temperature to T3 = T2 - T1. Bias currents for these detectors can be
on the order of 10-50nA with power dissipation in the range of 1-100nW. [for
what size-a pixel or array…120x160 & 480x460]
16
Temperature Sensitive Resistive Materials
One desirable property of a good quality detector is to have a high
temperature coefficient of resistance, which is described in detail in the next
section. Vanadium oxide and amorphous silicon are the current industry standards
for the uncooled market. Vanadium oxide is the more mature material whereas
amorphous silicon is gaining wide support for very low power applications. The
materials are both semiconductor resistive materials. The differences between
them lie in the growth process and final resistance values. Vanadium oxide
bolometers tend to have lower resistances and higher power dissipation.
Amorphous silicon bolometers have much larger resistances and have very low
power dissipation. 1/f noise seems to be at higher concentrations in amorphous
silicon bolometers. The non-uniformities responsible for fixed pattern noise are
lower in amorphous silicon. This thesis addresses the associative issues of
reducing spatial and temporal noise by employing background suppression
techniques. CMOS readouts in this thesis were designed based upon the
amorphous silicon detector.
Vanadium Oxide (VO2)
In 1982 R. Andrew Wood and his team at Honeywell Technology Center
originally developed the micro-bolometer composed of sputtered thin films of
oxides onto a silicon nitride bridge structure. Chemical vapor deposition is the
preferred processing mechanism. This material has a high room temperature
coefficient of resistance (TCR) around 2-2.2% and is a more mature technology
as well as the industry choice.[Kruse book].
17
Amorphous Silicon (-Si)
[Kent cit]One advantage this detector has is the compatibility with
conventional silicon processes and CMOS foundries while offering low-cost
compatible solutions. This thermally sensitive resistor has a room temperature
coefficient of resistance of 2.5-6 %/K. Material resistances are several orders of
magnitude larger (order of 106 ) and thus find applications in continuous bias
designs aimed at low power designs. The processing mechanism used is RF
sputtering. Problems with this detector are the 1/f noise.
Figure 2.1: 25u x 25u micro-bolometer array photomicrograph
from Dr. Paul Norton at NVESD.
18
Thermal Isolation
Support Legs
Via Contact to
Readout Input
Absorbing Resistive
Element (VOx or -Si)
Via Contact to
Voltage supply
Figure 2.2: Single uncooled pixel element from Dr.
Paul Norton at NVESD.
Uncooled Systems: Figures of Merit
The following are commonly used benchmarks to compare the uncooled
camera systems on the market today. These definitions were taken from [Kruse
7-9]
Responsivity
Defined as the signal output from a single pixel of an array divided by the
incident radiation falling onto that pixel:
 W   opt ff abs Adet 1  det I bias int Vs



4F 2
Gth
Cint
Po
 T 
19
V 
 
W 
(2.2)
NEP
The radiation power incident on a pixel gives rise to a signal to the rms pixel
noise within the system bandwidth.
PN 
VNoise

W 
(2.3)
D*
The detectivity is the detector’s signal-to-noise ratio normalized to an area of 1
cm2 and a bandwidth of 1 Hz.
D 
*
 AD f 
VNoise
1

2
cm

Hz

 W


AD f

PNoise





(2.4)
where AD is the area of the detector and f is the system bandwidth. There are
two types of D*; blackbody and spectral. Blackbody D* is a raw measurement
from a blackbody source. The spectral D* says how much detectivity response
given at a certain wavelength. Kruse states that in practice thermal detectors have
a wavelength dependence due to the spectral response of the absorbing layers[].
NET & TCR
The first is noise equivalent temperature difference and can be expressed
for a single pixel or the average of the pixels in the array. NET has two formal
definitions: 1) “The NETD is the change in temperature of a blackbody of infinite
lateral extent which, when viewed by a thermal imaging system, causes a change
in signal-to-noise ratio of unity in the electrical output of the pixels of a focal
plane array, or else of the readout electronics which receives an input signal from
20
the pixels of the array” and 2) “The NETD is the difference in temperature
between two side-by-side blackbodies of large lateral extent which, when viewed
by a thermal imaging system, gives rise to a difference in signal-to-noise ratio of
unity in electrical outputs of the two halves of the array viewing the two
blackbodies.” It is the measurement of the smallest temperature difference of
target that produces a gain of unity at the pixel output.
NE T 
4 F 2VNoise
 P 
 o AD  

 T 
K 
o is the optical transmission, AD is the pixel area and F 
(2.5)
1
where  is the
2sin 
angle which the marginal ray from the system optics makes with the optical axis
at the focal point of the image.
P
is the change in power per unit area radiated
T 
by a blackbody at temperature T, with respect to T in a particular waveband.
The TCR is defined as the temperature coefficient of resistance.

1 dRdet
Rdet dT
% / K 
(2.6)
This quantifies the bolometer dependence of resistance on temperature. Typical
values for vanadium oxide material are 2-2.2% and amorphous silicon are 2.56%[Kent]. Figure 2.3 below was taken from a course on detectors given by Paul
Norton from NVESD. The graph shows various bolometer material resistance vs.
temperature.
21
Thermal Time Constant
Figure 2.3: The semiconductor has negative TCR inferred from the
graph.
The bolometer has a response time or relaxation time defined by the following:
 thermal 
Cth
Geff
s
(2.7)
Cth is the total heat capacity of the bolometer. The detector can be considered a
composite of several layers each contributing some thermal capacitance. Geff is
the sum of the thermal conductances containing all the heat loss mechanisms.
Units of C are
J
W
and the units of thermal conductance G are
. The reader
K
K
may consult the following sources for a more thourough explanation; [Kruse and
Skatrud/Kruse].
22
Chapter 2: Fundamentals of Infrared Imaging
Introduction
Maximum performance in today’s and future uncooled infrared staring
focal plane arrays are limited by available well capacity storage. Terrestrial IR
imaging applications contain high levels of background radiation and impose high
dynamic range requirements on the readout electronics. Achieving maximum
signal dynamic range at the pixel level is paramount. However, these imaging
arrays are limited on what the semiconductor foundry has to offer in terms of
active or passive storage devices and process parameters. This thesis focuses on a
specific infrared band called the long wavelength infrared region or LWIR. This
region spans from 8 m – 14 m and contains a very high flux concentration
throughout the day’s diurnal cycle; heating during the day and cooling at night.
Therefore to accommodate such high flux applications, appropriate electrical
readouts must be designed. The direct injection readout design was chosen for this
thesis based on the excellent injection efficiency, minimal area, and low power
dissipation in the LWIR. The direct injection readout utilizes a common gate pchannel current buffer to isolate any variations from the detector to the integration
node.
Because of the lack of increased charge storage capacity in modern day
sub-micron CMOS geometries, saturation of the integrating well occurs
frequently. This precludes attaining long integration times in the readout.
Currently, integration times are a few hundred micro-seconds to a few milliseconds at best with today’s pulse-biased readouts and some DC bias readouts.
23
This thesis explores innovative low-power uncooled DC bias readout designs
focused on increasing the integration times up to and exceeding uncooled
bolometer time constants. Pixel time constants are governed by this simple
mathematical relationship:
 int 
CintVmax
I det
(1.1)
As the resultant current which charges the well decreases, the available
time to charge the well will increase. By allowing this to happen the overall noise
bandwidth of the thermal detector will reduce and increase the signal-to-noise
ratio. In terms of broadband noise or white noise, the signal is proportional to the
integration time whereas the noise is proportional to the square root of integration
time and the signal increases faster than the noise. At present, the bolometer
material contains a large 1/f noise component, which causes a problem for long
integration times. The 1/f or pink noise is proportional to integration time. At 1Hz
or 10Hz, the noise is indistinguishable from a low signal. Therefore it seems
increasing integration times may not increase the signal-to-noise ratio. However,
recent and future advancements are reducing the 1/f noise to acceptable levels to
achieve johnson noise limited performance. The benchmark for sensitivity used
by state-of-the art military and commercial markets is called Noise Equivalent
Temperature Difference or NET, which are on the order of 20-100 mK changes
in a 300 K background. Two methods reported in this thesis of helping to achieve
these sensitivities require background suppression schemes called current
skimming and charge subtraction. Current skimming subtracts the input DC
current signal to some reference point; usually the substrate. This allows a much
24
smaller signal representative of the tiny infrared temperature scene change to
accumulate onto the integrating capacitor. Charge subtraction, utilized by a MOS
capacitor, is another method of extending the integration times by siphoning
charge from the integration node. The active storage element is the gate oxide of a
MOSFET where the source and drain are electrically connected. Ironically, the
MOS capacitor has the highest capacitance per unit area but has an inherent nonlinear nature. The non-linearity is not a problem as long as the capacitor is
operated in its linear regime. The nice feature of the MOS capacitor is its
dynamic operation. Effective storage capacity may be increased or decreased by
driving the MOS capacitor between depletion and inversion. The goal of this
work is to design, fabricate, and test pixels that achieve successful background
suppression techniques. Suppression mechanisms investigated are:

Single MOS transistor

MOS cascode transistor

Self-biased cascode transistor

MOS capacitor
Optimized layout and design in the above suppression schemes are
discussed. The study includes discussion of the practicality of per-pixel skimming
and the related biasing mechanisms. To date, there is no viable per-pixel
skimming CMOS readout in the military or commercial uncooled markets.
Chapter 4 explains best the present situation on the many design challenges and
hurdles for per-pixel skimming in uncooled focal plane arrays.
25
Wavelength Spectrum & Atmospherics
Figure 1.1 shows the atmospheric transmission of the infrared spectrum
and respective bands. Absorption occurs when molecules such as water vapor,
ozone, carbon dioxide, carbon monoxide, and nitrous oxide collide and exchange
energy with the incident photon thus causing a temperature rise in the molecule
[driggers]. The band gap energy of the photon must be greater than or equal to
the molecular band gap in order for absorption to occur. Band gap energy is
defined from Einstein’s energy relation, which is proportional to Planck’s
constant multiplied by the frequency of the wave.
Eg  h
[eV ]
(1.2)
Wavelength can be determined from frequency by the following relation:

c

[ m]
(1.3)
Scattering is when large particles such as pollution, dust, smoke, precipitation,
and various man-made or natural aerosols collide with incoming radiation are
redirected with a different energy. The extent to which the infrared radiation is
redirected has to do with the mass of the molecule and wavelength of the
incoming photon [cit]. Of course since energy is conserved in these collisions
whether it is absorption or scattering, these mechanisms are important functions
of wavelength. Various factors influence the atmospheric transmission of the
incoming infrared radiation. These include ambient temperature, altitude,
humidity, atmospheric pressure, and refractive index fluctuations (turbulence)
[Driggers, Cox, 127]. As seen by the figure the long wave infrared has a high
26
transmission factor and is also the largest band (but not evident from a log scale in
wavelength).
Figure 1.1: Reprinted from Introduction to Infrared and Electro-Optical Systems.
The spectrum breakdown shows the different infrared bands
extending from .8 m to >30 m.
Readout Systems
Imaging systems employ a readout integrated circuit that translates the
infrared detector output to an electrical signal that represents the observed scene.
A primary function of the readout is to provide pre-amplification (detector signal
conversion), gain, and some cases A/D conversion. Below Figure 1.2 shows an
example of a typical single readout signal path from pre-amplification to video
output.
27
Pixel
Column Multiplexer
Video Amplifier & A/D and D/A
A/D D/A
Video Amplifier Output Pad
Idet
Column Bias
Rdet
Video Display
Infrared Photons
Vdet
Readout Process Electronics
The function of the pixel (sometimes referred to as the unit cell) is a
Figurecurrent-to-voltage
1.2: ROIC & image
system level
description.
conversion
or voltage-to-current
conversion. Two methods of
pixel readout are voltage and charge mode output. The first method usually
employs a current-to-voltage conversion on the integration capacitor and
subsequently buffers the voltage signal from the integration node to the output
through a source follower. Doping concentration of the source & drain diffusions
and the substrate determine source follower gain levels for a given CMOS
foundry. To achieve maximum dynamic range, designers should utilize native
transistors that yield approximately 98% gain for n-channel transistors (due to low
threshold voltage). If native transistors are unavailable, the next best option is
28
using p-channel transistors, which have signal gains of > 90%. The current-tovoltage conversion is performed by the direct injection transistor (common gate
current amplifier) and capacitor combination. The direct injection transistor has a
current gain of  unity.
Vdd
Vdibias
Vdd
Voltage Mode
Readout with
Current Skimming
Rdet
Row_Sel
Vreset
Iskim
0
Cint
Col_Amp
0
0
Column Bias
0
0
Figure 1.3: Voltage mode readout. For lower noise, designs should employ p-channel
(well transistors) where possible.
One immediate draw back using a voltage buffer is the body effect. In essence,
the threshold raises and gate overdrive reduces which translates to lower source
follower gain and loss of integration signal. Using a p-channel buffer will
eliminate this problem (by connecting the well and source) as well as being a
better candidate for lower noise. Another method of readout is to operate in
current or charge mode. Some reasons for implementing this architecture is to 1)
minimize power consumption by eliminating the source follower, 2) lower noise,
and 3) decreased pixel area so as to increase the integration capacitor size. The
29
above reasons are valid in choosing a charge mode approach over the voltage
mode, but the voltage mode achieves higher dynamic range than the charge mode
readout. In charge mode readout, when the row select switches are open and
closed, the integration capacitors are exposed to the column integrators where
charge injection could occur (loss of signal). Also, the integration capacitor
contains a noise floor and therefore does reset down to ground. Usually, the
power supply swings in the pixels do not cover the full range. Therefore when
using charge mode readout, designers have a decreased voltage swing due to the
integration node sharing its capacity with the column capacitance when being
read. Therefore V 
Q
, which reduces the available dynamic
Ccolumn  Cint_ node
range. Both readout modes have their advantages and disadvantages.
30
Vdd
Vdibias
row_sel
Charge Mode Readout
with Current Skimming
Rdet
Col_Amp
Vreset
Iskim
0
Cint
0
0
Figure 1.4: Charge mode (also called current mode). Output signal is charge
rather than voltage. The reset of the integration capacitor is part
of the readout operation. The advantage of charge mode is less
pixel area, lower power consumption, and lower noise. The disadvantage is the decrease in dynamic range on the column as a
result of integration node capacitance shared with column
capacitance.
31
Pixel_a1
Pixel_a1
column_bias
column_bias
0
0
Pixel_a2
Pixel_a2
Sample & Hold
Sample & Hold
Cs/h
0
Cs/h
Column
Amplfier
Column
Amplfier
Output
Pad
0
0
0
Video
Buffer
column_select
column_select
0
0
Figure 1.5: Example 2x2 array at the chip level.
We have discussed the system architecture and will now explain the two
modes of the readout process; rolling and snapshot. Rolling mode is a sequential
read where the system software clocks the first row to be read then moves onto
the next row. So as we cycle to a new row for readout, the previous row has
begun to integrate again. This method reads one row at a time, and integration is
staggered over the frame for individual rows. Snapshot mode is where each row
integrates in parallel and then is readout after all the pixels have integrated
simultaneously. Snapshot mode requires a hold capacitor per unit cell and more
sophisticated clocking electronics [Calist.MSEE].
32
Chapter 3: Background Suppression in the LWIR
Justification for Current Skimming & Charge Subtraction
Background suppression is implemented to improve signal-to-noise by
extending integration times and hence dynamic range. The difficulty of
background suppression is extracting the low contrast IR signal from a high
background photon concentration without introducing significant additional noise
to the pixel. One solution for background suppression involves current mode
skimming implemented by MOS transistor current sources. Another form of
suppression is charge subtraction, which is implemented by connecting a
MOS capacitor’s source and drain to the integration node while biasing the
gate. Charge subtraction augments the pixel signal sensitivity by maintaining
high dynamic range from a smaller effective capacitance.
Due to response non-uniformity of the detectors, the background pedestal
varies from pixel to pixel and requires (off focal plane) non-uniformity correction
methods to keep track of pixel bias levels to interpret the appropriate injection
levels. Usually off-chip DSP circuitry is implemented for non-uniformity
correction. Associative issues of current skimming are investigated (Chapter 4) to
better explain the advantages and disadvantages for improving detector nonuniformity. Current skimming should improve pixel performance by reducing the
overall temporal (white or broadband) noise by longer integration times leading
to higher signal-to-noise, while charge subtraction enhances signal sensitivity and
achieves higher signal-to-noise as well. This chapter explores the details of
33
background suppression methods for continuous bias uncooled infrared focal
plane arrays, which aim to improve pixel signal-to noise.
Spatial & Temporal Noise
Without careful design, adding background suppression circuitry to the
pixel runs the risk of not improving the performance. The reality of per-pixel
skimming (discussed in CH 4) raises questions as to whether this will be effective
in reducing the fixed pattern noise from the detector array. Per-pixel skimming is
possible with smart analog functions, adaptive skimming pixels, and accurate
subthreshold design and modeling, [Philippe’s explanation].
A limiting factor in current uncooled focal plane arrays is the detector
resistance variations. These micro-bridge structures are not fabricated with equal
resistances. Inherent in the growing phase of these sensors are process variations
that inevitably may cause a 2-3% variation in detector resistance across the staring
array [Kent McCormack]. The ideal situation is to have all the pixels in the
staring array to be subtracting the same dc background pedestal. Capturing the
finer details of the re-created scene image requires a great deal of sensitivity in the
detector and CMOS readout electronics. For resistive bolometers to operate with
20-100 mK sensitivities within a 300 K background, uniformity is paramount.
Therefore it is imperative that detectors maintain similar performance.
Neighboring pixels as a result of different resistance values absorb different
photon flux intensities, which translates to a variable spectral response across the
array contributing to fixed pattern noise. Fixed pattern noise is considered a
spatial noise component, which includes the detector, pixel, column, row, and
34
output CMOS readout electronics noise [4]. The following are some physical
mechanisms that result in responsivity non-uniformity.
Detector bias non-uniformities due to transistor matching impact the
image quality by adding to the spatial noise component. For example, if the
detector bias in pixel11 is 1 V and pixel12 bias is 980 mV, the injection currents
will differ. The results are different magnitudes of charge storage in the well.
Threshold voltage non-uniformity causes certain spatial fixed pattern noise within
the pixel elements. Threshold variations for a given modern CMOS process on a
given 8 wafer typically are less than 5 mV. Threshold variations may vary
from process to process and wafer to wafer. From a camera system point of view,
integrating as much of the low-contrast IR signal translates to increased
sensitivity and image quality, therefore a significant array variation in well
integration negatively affects dynamic range. There are non-uniformity correction
techniques, which alleviate fixed pattern noise in the detector array. Correction
voltages in the form of a digital code are clocked at the output pixel rate and
introduced back into the pixel to adjust the non-uniform injection currents and
attempt to make them equal [4].
Some pixels in the array may need to skim more or less than others as a
result of the following:

Detector resistance non-uniformity

Detector bias variations

Pixel location on the array

Transistor threshold voltage non-uniformity
35
Since the skimmers will operate in subthreshold (high gain and low
power), current mismatch may be as great as 10% between neighboring pixels in
the worst case [Vittoz stat]. Maintaining individual skimming current level
relative to the level of injection current is critical for successful operation.
Design for continuous bias arrays with extended integration times makes
the design more flexible for reducing the temporal noise as opposed to the spatial
noise requirement because of the inverse relationship of noise bandwidth to
integration time. Noise bandwidth for the uncooled integrator pixel is defined as:
N BW 
1
 Hz 
2 int
(3.1)
This thesis describes pixel-level concepts that achieved integration times
on the order of bolometer time constants (thermal time constant in equation 2.7).
Sensitivity & Dynamic Range
These two concepts are very important referring to the ability of the
detector and processing electronics to attain high signal-to-noise.
Chapter 2
covered sensitivity figures of merit measured by  , NEP, D*, NET, and thermal
response time. Envision the signal path from the scene to the column amplifier
electronics. As an infrared photon is collected by the detector, noise accumulates
on (summed in quadrature) the detector, pixel, and column electronics. A goal for
the readout designs is to have the rms noise levels at the output of the column
amplifiers to be less than the noise contributed from the detector (detector
limited). Sensitivity cannot fully be explained by one or two parameters, but
rather a combination of system parameters that result in a particular camera
36
performance level. However, a good figure of merit that states a direct sensitivity
measurement referring to the pixel is NET, which relates signal to temporal
noise. NET is defined as the smallest temperature difference from a target that
produces a signal-to noise ratio of unity at the pixel output. Detecting minute
temperature changes may be expressed as NET for a single pixel or the average
of pixels in the array [5].
Dynamic range can have several meanings depending on the area of
engineering. Essentially it is the ratio of some maximum parameter (power,
voltage, or current) to some minimal detected level of that parameter. In
terms of uncooled thermal systems and for the remainder of this thesis the
dynamic range of an uncooled bolometer pixel or array will be:
 Tmax_ scene 
DRdb  20log 

 NET 
where
Tmax_ scene  85 C
(3.2)
For current state-of-the art uncooled thermal systems we see 72dB as the industry
standard for dynamic range at the maximum scene temperature [3]. Therefore at
the maximum scene temperature we should maintain a NET = 90 mK. In terms
of the pixel dynamic range the well capacity can be envisioned as a storage bucket
whereby charge is accumulated as a voltage signal. The goal is to integrate as
much charge as possible without saturating the integration capacitor. In the case
of a voltage mode style readout operation the well signal is buffered out by a
source follower, which typically has 80-97% gains depending on the process and
type of FET used. In a sub-micron process such as a 0.25 um mixed-signal, a
native MOSFET provided by the foundry, which enables a lower Vt., have 97%
37
gain. Vendors which do not supply native transistors typically provide devices
that will give gains ~ 80-95%. In terms of dynamic range and signal-to-noise, a pchannel transistor would be a better choice because the body effect can be
eliminated, has a higher gain, and lower noise (as a result of lower mobility). An
n-channel transistor suffers from the body effect and usually drops the signal by
an amount equal to its threshold. Process parameters from a given foundry
directly impact the performance of pixel dynamic range and sensitivity.
DC Suppression Concepts
This section offers details of the background suppression schemes and highlights
the preferred methods. An important aspect of implementing a current source in
MOS technology is to maintain precision matching in layout, which reduces
channel conductance fluctuations. Maintaining a stable constant current source
requires non-minimum channel lengths to increase the Early voltage1 [6] which
essentially flattens the I-V curves. Analog design usually requires minimum
lengths to be roughly 2-5 times the size of Lmin for a given process technology.
However designs may have area constraints. If the design is not constrained by
area requirements making the channel longer than required increases the output
resistance further.
The first concept is the single MOS transistor skimmer. Figure 3.1 below
illustrates a single n-channel transistor current skimmer connected in a common
gate configuration. Since these skimmers are operating in subthreshold, the
1
Jim Early discovered modulation effects in bipolar conductance as a result of reduction in the
neutral base region. This mimics the effect of channel length modulation in above and below
threshold MOSFET’s where the channel is “pinched-off” at the drain end and effectively
decreases Leff while an increase inVds causes an increase in the drain current.
38
channel currents are exponentially related to the gate voltage and are quite
sensitive to gate bias. Fluctuations in drain-to-source voltage will cause the
skimmer to have an incremental output current where the slope in the I-V curve is
the output resistance. Figures 3.2 and 3.3 highlight the effects of the output
resistance as channel length is increased. A major drawback of this configuration
is that all signal changes on the integration node will be reflected through the
skimmer’s channel therefore reducing signal sensitivity by having a non-linear
current.
Vdibias
VDD
Single FET DI Skimming Pixel
Vskim
Vreset
Vskim
0
Cint
Vout
0
Figure 3.1: Description of a direct injection pixel with a single MOSFET current
skimmer. This skimming suffers from channel length modulation at
the integration node and therefore has a non-linear current. Also, any
time varying capacitances will adversely affect current skimming. No
matter how long the channel is, it is exposed to the integration node.
39
1.200E-08
Simulated single MOS transistor current skimmer
Subthreshold Operation
Vgs = 700mV
1.000E-08
(W/L) = 5.1u/5.1u
(W/L) = 5.1u/9.9u
(W/L) = 5.1u/15.6u
(W/L) = 5.1u/19.5u
(W/L) = 5.1u/27u
(W/L) = 5.1u/37.5u
(W/L) = 5.1u/43.05u
Ids
8.000E-09
6.000E-09
4.000E-09
2.000E-09
4.84
4.59
4.33
4.08
3.82
3.57
3.31
3.06
2.8
2.55
2.29
2.04
1.78
1.53
1.27
1.02
0.77
0.51
0.26
0
0.000E+00
Vds
Figure 3.2: As the channel lengths increase, the I-V curves have lower area
conductance; hence the increased area decreases the percentage of
the channel affected by channel length modulation. The area most
affected will be the area closest to the drain where the electric field is
strongest.
Transistor width would have to be kept at a minimum and the length
increased to where the I-V curves are flat. Also, the single transistor must remain
in subthreshold. The skimming transistor’s intended region of operation is utilized
to achieve very low power dissipation and the highest transistor gain. Since the
drain current is exponentially related to gate voltage, controlling the gate bias is
the most difficult task in the per-pixel skimming concept.
40
5.1 um
Conductance(gds)
pA/V
207
Output
resistance
(G)
2.19
9.9 um
258
5.55
15.6 um
90.9
11
19.5 um
64.2
15.6
27 um
38.4
26.1
37.5 um
22.7
44.1
43.05 um
18.1
55.1
Leff (um)
Table 3.1
The second method of current skimming to use a MOS cascode current
source in Figure 3.4.
41
Conventional MOS Cascode
VDD
Rload
Vou t
M2
Vcasco de
0
0
Vm
M1
Vinp ut
0
0
Figure 3.4: The cascode refers to the series connection of a common
gate and common source amplifiers. Vcascode is constant.
An important design criteria for uncooled readout arrays is low power
consumption, which begins at the pixel level. Besides the increased area, a major
disadvantage of the above configuration is the increased voltage at the output
node required to keep M1 and M2 in saturation. This condition translates to
increased power consumption and decreased dynamic range within pixels. In lieu
of increased power, an additional bias line must be added called Vcascode to
compensate for various input swings from M1. The following explanation and
42
quantitative analysis is duplicated here for clarification of basic cascode operation
and thoroughly explained in reference [7].
Vmin  Vinput  Vmax
(3.3)
We assume that there is a swing around some minimum and maximum
value that will be applied at the gate. Simultaneously, the cascode voltage will be
moving up and down as a result of this swing.
Vmin  Vcascode  VM   Vmax
(3.4)
As mentioned above, our goal is to keep M1’s drain in saturation as well
as the output at M2. For this to happen, Vcascode must be greater than (VSAT + VM)
at the drain of M1 to compensate for the drop from M2’s gate-to-source and
Vinput’s gate-to-source. Therefore M1’s condition to remain in saturation is the
following.
(Vcascode  VM )  Vsat
(Vcascode  (Vsat  Vmax ))
(3.5)
Keep in mind that in order to provide a constant current source the
transistors’ Vds must reach a saturation voltage. In the case of minimum swing the
following occurs:
Vcascode  Vsat  Vmin
Vcascode

 VM  Vmin
(3.6)

(VM  Vcascode  Vmin )
43
So now at minimum swing, the cascode gate must increase its overdrive
(Vgs –Vt) to keep the M1 and M2 series connection in saturation. Maintaining
Vout in saturation the following criteria must happen:
Vout  Vsat  VM
(3.7)
If we substitute the result of Eq. 4.5 and 4.6 into 4.7 we obtain the
necessary output voltage to maintain M2 in saturation:
Vout  (2Vsat  Vmax  Vmin )
(3.8)
Since M2 is in a common gate configuration it has a gain Acg and therefore the
total output conductance is
g ds
.
Acg
The third dc suppression concept incorporates a self-cascode current
skimmer and a MOS capacitor. The MOS capacitor facilitates the charge
subtraction concept, which is supposed to increases the integration node
sensitivity.
Vmoscap
Vdd
Vdibias
Vdd
0
Rdet
Vreset
Cint
0
Vskim
Low Power SCFET
Skimming Pixel w/
Charge
Subtraction
0
0
Vout
0
Figure 3.5: This experimental pixel was used to verify the dual use of current
Skimming and charge subtraction.
44
Current Skimming
Fundamentals
The detector current is comprised of a large dc background component in
addition to a small ac scene dependent signal containing the IR signature. This ac
signal represents the tiny temperature change from the target to the bolometer.
[reference the circuit for explanation]. Without the skimming FET the voltage
swing on the integration capacitor is:
V 
I
dc
 I ac _ scene   tint
(3.9)
Cint
If we include the skimmer the relationship simply becomes
V 
I
dc
 I ac _ scene  I skim   tint
Cint
where I dc  I ac _ scene  I det
(3.10)
If we assume that 100% of the background pedestal is subtracted the equation
shows us that we can integrate for a much longer time without saturating the
integration capacitor and the signal being integrated is entirely from the scene.
 int 
V  Cint
I ac _ scene
(3.11)
There are two methods of obtaining a skimming current. The first is simple and
uses a bias voltage on the gate directly and the second method uses an external
resistor, PFET current buffer and a current mirror. Using a current mirror provides
better sensitivity for temperature variations and is less noisy. Chapter 6 describes
in detail the operation of the individual chip functions.
45
Self-Biased Cascode Origin & Fundamentals
Present and future mixed-signal analog foundry processes have reduced
supply headroom. The ability to implement traditional methods of impedance
increasing circuits such as cascoding are extremely difficult and impractical.
Movement towards low power design comes as a result of the wireless
communication market demand for PDA’s, laptops, LAN’s, and cell-phones,
which require low power and low weight devices.
As result of this ultra-low power consumer demand, a new era in mixedsignal design has arrived. Current process geometry nodes (.25um, .18um, and
.13um) and ones on the near horizon (90nm and 65nm) are posing many
challenges to analog designers due to a decrease in power supply and significant
problems with the device physics. Voltage mode design is being heavily
augmented in present and future designs by current-mode philosophy and
techniques.
These current-mode circuit designs are built upon the translinear
principle, which Barrie Gilbert first initiated in early bipolar circuit design in th e
1970’s. Device transconductances are linearly proportional to the current through
the conducting channels with vertical carrier transport for the bipolar transistors
and surface carrier transport through the MOS device [8]. Modern designs in
conventional CMOS or BiCMOS applications apply this principle for transistors
operating in weak to moderate inversion regions. In section 4.2.1, we discussed
why a conventional cascode needs an extra bias line to overcome the Vdssat
problem. In recent years, there were not many concerns of voltage headroom
46
because of the large operating voltages for many early foundry processes.
Available supply voltage for present day sub-micron nodes .35um down to 90nm
decreases to 3.3V, 2.5V, 1.8V, and 1.5V on core supplies. The supply voltage and
threshold range do not scale proportionally therefore leaving very small voltage
swings available [9] and not much option for simple cascoding techniques.
A clever way to decrease the output conductance (increasing ro) of a
MOSFET is to use series connected FETs with a trapezoidal like geometry and
their gates connected by a single poly-silicon gate. This configuration is known as
a self-biased cascoded MOSFET (SCEFT) [10]. The first reports of this device
structure originated in the early 1990’s from NASA’s Jet Propulsion Laboratory
and was mathematically explained and verified by the Swiss Federal Institute of
Technology’s Eric A Vittoz [11,12]. Since then, the SCFET, as it is called is
beginning to gain much attention for its high performance in low power systems.
Shown in Fig 4.4 is an example of the SCFET.
Self-Cascode FET(SCFET)
Vd
Mcascode
0
Vscfet
Vm
0
Mbias
0
Figure 3.6: Two series connected transistors with a
common gate Configuration.
47
To operate effectively as a current source the transistors need to be in
saturation while incurring small changes in output conductance. To minimize
power consumption designers look to operate circuits in the weak to moderate
regions while taking advantage of high
gm
I channel
ratios and the low currents.
Fortunately, FETs in weak inversion only require a Vds  4Vthermal to operate as a
constant current source, which places them in the subthreshold saturation region.
The drain of the Mbias (VM) is shielded from large voltage swings on the output as
a result of subthreshold physics and the symmetrical exponential relationships
between the source & drain implant regions. VM also must approximately
equilibrate to approximately 4Vthermal to operate effectively as a current source.
Fluctuations in output conductance complicate stability in designing low-level
current sources. This effect is known as channel length modulation; a problem
caused by the Early effect which we mentioned in section 4.2.1. Modulation of
the effective channel length is defined as:
gds _ bias 
Leff
 Leff
I ds
I
I
 ds 
  ds  
Vds Leff Vds
Leff  Vds

I ds

 VEarly
(3.12)
The current relationships will be explained in section 4.2.3a, but it is important to
understand the impact of channel conductance on the saturation current in weak
inversion.
Including channel conductance the weak inversion saturation current effects is as
follows:

V
I ds  I sat  g dsVds  I sat 1  ds
 VEarly

48



(3.13)
Designers may consider the Early voltage to be proportional to length of
FET. Analog transistors studied in a standard CMOS 0.5um process and relevant
to the widths and lengths of the FET’s in this thesis will have Early voltages in the
range of 40-100V for NMOS and 80-100V for PMOS [13]. For large channel
lengths the Early voltage is large and the term in parenthesis becomes
insignificant. Therefore a result of minimal g ds demands a long effective
channel to maintain a stable current source. Because Mcascode acts as a shield and
an output impedance multiplier, the
in the SCFET while the ratio
Weff
Leff
ratio of Mbias sets the actual current level
Lbias
determines the effective output impedance
Lcascode
level [10]. Increasing the ratio increases the output impedance (see section 4.2.3d)
of the SCFET. Another interpretation is the output impedance relies exclusively
on Mcascode’s ability to shield Mbias from large output voltage swings. The bias
transistor has a much lower output resistance than the cascode transistor. Mcascode
performs better than a conventional cascode because of the inverse exponential
behavior of the junctions and the very low gate overdrive voltage required to keep
Mcascode in weak inversion. Weak inversion MOS physics aid in understanding
why Mcascode’s output resistance is so high though it has a shorter channel length
than the bias transistor [14]. A very thorough explanation as well as an
informative source for the physical mechanisms of the SCFET is found in [10]
[RC Schober source task plan 80.3295 @ JPL].
Carrier diffusion (there is no drift component in weak inversion) is the
dominant transport mechanism in weak inversion. A gradient of charge carriers
49
exists and applied bias that causes directional motion. Even with no applied
external bias, thermal jitter causes carriers to shift around their respective local
positions, which creates random thermal motion. The MOSFET operates
accordingly with increasing applied gate potential for an NMOS: (s < 0) the
device is in accumulation, (0  s  f) the device is in depletion mode, (f  s 
2f) the device is in weak inversion (subthreshold), and (Vt  s  VDD) the device
is in triode or saturation2. The inversion channel between the SiO2 – Si interface
does not completely form in weak inversion and is negligible relative to the
depletion region width. Therefore the surface potential is dependant on the
applied gate voltage by the mathematical relationship in Eq. 4.10. Kappa is the
inverse of the familiar subthreshold slope factor parameter and is viewed as a
correction factor or capacitance divider of the gate’s ability to control surface
potential.
 surface
Cox
1
  n, p 

n
Vgate
Cox  Cdep
Cdep 
qN A, D si
(3.14)
(3.15)
2 surface
Appendix A provides a derivation of MOS subthreshold equations including the  correction
factor.
2
50
Connective diffusion  4Vt
Must maintain high
barrier energy for
electrons to climb.
barrier
Figure 3.4: Shown above is a physical description at the self-biased cascode
FET. The cascode transistor operates in weak inversion while
The bias transistor operates in moderate inversion. The channel
Conductance (gds) in the bias transistor is much larger than the
Cascode transistor. The bias transistor sets the reference current
For the skimmer.
In Figure 3.4, we see a physical view of the SCFET as well as its
associated potential-well diagram3.
It should be noted that the values for  n   p as a result of starting wafer
material type and respective doping concentrations; either NA (p-type) or ND (ntype). This is evident in equations 3.14 and 3.15. Figure 3.5 on the following page
shows a MOS capacitor system representative for weak inversion operation,
which shows the capacitive divider. The capacitor network on the left includes
two terms not usually applied, though negligible need to be addressed [15] as
3
Potential well diagram adapted from Fig 2.3-2 pg. 69 in Bedabrata Pains’ PhD Thesis in ref [13].
51
process geometries are scaled down. Cn and Cp (depending on semiconductor
type) is the capacitance due to attracted electron charge or hole charge
respectively and Cit is the interface trap capacitance due to trapped interface
charges in the SiO2 layer. The gate potential drop is divided between the oxide
and the depletion region, which is represents the surface potential. Section 4.4.4
discusses the fact that as process geometries scale down n and p reduce due to
increased doping densities required to maintain threshold voltage scaling.
Therefore transconductance is reduced and makes subthreshold operation difficult
to maintain. Future advanced UIFPA’s that utilize subthreshold operation FETs
for pixel electronics will be faced with serious analog circuit design challenges.
Weak Inversion MOS Capacitance System
Vgate
Vgate
Cox
Cox
Cdep
Cn / Cp
Cit
Vsurface
Cdep
0
0
Low Frequency Operation
Figure 3.5: The dominant capacitances are the depletion and oxide.
52
Analysis of Pixel Circuitry
This section presents the pixel on a circuit level examining small signal
properties and investigating elements of the proposed pixel design. The design
presented here was fabricated using an AMI C5N 0.5um process available from
the MOSIS foundry. The process is a 3 metal, 2 poly offering two special options:
1) a linear capacitor between poly2 and poly1 which gives  950 aF/um2 and 2) a
Hi-Res layer option for resistors up to  1k.
DC Bias Point of DI FET
MOS Injection circuits perform charge integration onto some storage
element through the channel of an MOSFET. This thesis uses two kinds of storage
capacitors: 1)PiP4 linear capacitor and a 2) MOSFET capacitor. The injection
PFET in Figure 3.6 on the following page acts as a unity gain current buffer
operating in weak inversion (common gate configuration) that shields detector
node variations from stored signal on the integration node. Direct injection is a
readout architecture chosen to accommodate large photon fluxes in the LWIR
(8um-12um) spectrum. Therefore, a design goal is to maintain a fairly high and
non-volatile gm (trans-conductance), which results in low input impedance
presented to the detector as well as aiding in providing stable detector bias.
Maintaining low input impedance is to have the approximate FET input
resistance, Rin 
4
1
gm
Rdet to ensure proper injection efficiency. Otherwise, if
A PiP capacitor is a silicon-dioxide layer used as the dielectric between two layers of polysilicon.
53
Rin
Rdet then input current will be diverted or shunted across the detector [16].
Injection efficiency is thus dominated by the following equation.

I electric
r g
 det m
I photon 1  rdet g m
(3.16)
Shunted charges across the detector result in less charge integrated which
equates to a lower SNR at the pixel output.
Vdi
Rdet
Figure 3.6: Maintaining good
injection efficiency equates to a stable
and low input impedance relative to
the detector.
Iac
Rin ~ 1/(gm+gmb)
Vreset
Iskim
Cint
VDD
The detector node is considered the source of the injection PFET. Utilizing
KVL starting with the positive terminal on Vbias and summing the drops we derive
the following:
Vdet_ bias  VDI  (Vthp )  VDD  0

KVL
(3.17)
Vdet_ bias  VDI  (Vthp )  VDD
Vs of the injection FET has been absorbed by Vdi , the gate to source bias of the
injection PFET in Fig 4.8.
54
Input KVL Loop
Vdet_bias
Vdi
VDD
Vthp
Figure 3.7: Kirchoff’s
Voltage Law shows
proper bias polarity to
maintain good
injection efficiency.
We start on the
positive terminal of
Vdet_bias.
As we can see, detector bias is controlled by the direct injection bias,
threshold voltage, and the supply. Section 4.4.1 deals in detail with VTH
mismatch in all regions of MOS operation, which can pixel performance
contributing to an increased spatial noise component and reduced SNR.
Detector resistances for the amorphous silicon micro-bolometers are
approximately 50M while maintaining a 1V bias across the detector. With
known detector resistance values and Vdet_bias, the detector current is solved by:
I det 
Vdet_ bias
Rdet

VDI  (Vthp )  VDD
Rdet
(3.18)
Current ranges flowing through the detector from –20 C to 65 C
environments are approximately 2nA to 45nA respectively. As a figure of merit,
room temperature (23 C) should conduct approximately 19nA. Assuming 100%
injection efficiency I det  I DI can be assumed.
With DI PFET body effect eliminated because the well is tied to the
source input, we focus our attention on the symmetrical source & drain implant
regions which contribute two independent streams of diffusion current; a forward
and reverse current [17]. If (forward current) originates from the source and
55
terminates at the drain and Ir (reverse current) originates from the drain and
terminates at the source. The barrier height is smaller at the source implant than
the drain implant therefore I f  I r (see Figure 3.4) [18]. Thus the fundamental
equation governing weak inversion current is the difference in the forward and
reverse currents.
I channel  I forward  I reverse
 Vg Vs 
I f  Ioe
Vthermal
(3.19)
Vg Vd 
I r  Ioe
Vthermal
(3.20)
The term Io is considered a process dependent “accumulated pre-exponential” [17]
defined as:
Io 
W
dN
qtchannel Dn , p
L
dz
(3.21)
where tchannel is the depth of the channel (or inversion layer thickness), Dn or Dp is
the diffusion constant for electrons or holes respectively, and
dN
is the carrier
dz
concentration gradient from source to drain [17]. This scaling current may also be

2 n , p CoxVthermal 2 
defined as  I o 
 the forward current of a “unity shape factor


n
,
p


 Weff

 1 operating in the center of moderate inversion [13]. This predevice” 
 Leff



exponential term is process dependent and shows little dependence on the aspect
ratio W/L. The pre-factor term notation will be adjusted to consider the W/L
aspect ratio.
56
It
Io 
Weff
qtchannel Dn
Leff
 Weff
dN
 It 
 Leff
dz




(3.22)
By associating current flow as two independent processes using the above
equations will be helpful in weak inversion circuit analysis and in understanding
associated noise mechanism processes in weak inversion [18]. The carriers must
overcome barrier potentials at the junctions to achieve conduction. Therefore
combining the two current equations in eq 4.16 and accounting for the Early
affect mentioned in eq. 4.11 we come to:
I DI
 Weff
 It 
L
 eff


 e


 p (Vb Vg )
Vthermal
(e
 (Vb Vs )
Vthermal
e
 (Vb Vd )
Vthermal

V 

)  1  ds 


  VEarly 

Since the well is tied to the source we can eliminate the term e
 (Vb Vs )
Vthermal
(3.23)
. As far as
saturation is concerned for the S/D implants; the source is biased a constant 4V
while the drain (or the integration node) is time dependent. The integration node
assumes a reset value of 1.024V and maximizes around 3.9V. Because the
detector node (Vsource) is at a stable voltage of 4V and
1
 Rdet , the DI FET is at
gm
maximum injection efficiency. We may also assume the injection FET to be
saturated and with the body effect eliminated we may now substitute Vb = Vs:
I DI
 Weff
 It 
L
 eff


 e


 p (Vs Vg )
Vthermal
(1  e
 (Vs Vint ( int ))
Vthermal

V 

)  1  ds  where Vs  4V


  VEarly 

(3.24)
The voltage mode output elucidated some nonlinear effects as a result of a
low column bias Vds and gate overdrive of the source follower. Therefore a
reference voltage of 1.024V was implemented to raise the signal level to avoid
57
any such non-linearity. The Vint node charges from 1.024V to  3.9V. As a result,
I have decreased the dynamic range on purpose, but only to demonstrate a concept
while maintaining linearity. In Eq. 3.24, the term (1  e
 (Vs Vint ( int ))
Vthermal
) may be
neglected due to the inverse exponential behavior as a result of increased drain
barrier height relative to the source barrier. Thus the injection current is
independent of the integration node voltage.
1
(1 
e
(4V 1.024V )
.025V
1
(1 
e
(4V 3.9V )
.025V
)  2.00256 1052  1  min
)  .981684
 max
Therefore we may neglect the term in parenthesis at the onset of integration (min)
and conclude its value to be unity. At maximum integration time (max) we assume
that we do not charge all the way to 4V otherwise the term in parenthesis would
mathematically result in zero current which is physically incorrect. Without loss
of generality max  min as a result of the inverse exponential relationships at the
drain implant region. If we solve eq 4.9 for the Early voltage and substitute
into eq. 4.20 we can see some 2nd order effects of how subthreshold current is
in fact somewhat dependant on channel geometry. However enhanced effects
will ultimately be seen with very small channel lengths. A reason the Early effect
in weak inversion is considered a 2nd order effect is because g ds
g m (where the
source is the reference since there is no body effect here) [19]. The Early effect is
more enhanced at process geometries below .25um rules. For the AMI .5um
58
process considered in this thesis, the gate voltage and temperature play a much
stronger role in affecting conduction current than does the Early effect.
I DI
I DI
W
 I t  eff
L
 eff
  Weff
  Ito 
  Leff

 e


 e

 pVg Vs
Vthermal
 pVg Vs
Vthermal

V 
1  ds 
 VEarly 
 Weff
 I to 
 Leff


 e

 pVg Vs
Vthermal
(3.25)
 Vds Leff  

 
L

V
eff
ds

 
(3.26)
Eq. 4.21 purposely exhibits the inverse relationship between the channel
current and effective channel length. The first term is the saturation current and
the second term represents 2nd-order effects involving the depletion region
encroachment into the channel for short channels and how this affects Leff and
output conductance5. The second term is insignificant for large channel lengths
but needs to be addressed for deeper sub-micron geometries where the Early
effect and channel length modulation will become important subthreshold design
criteria. If the second term is insignificant then the equation reduces to eq. 4.20.
Early voltages decrease for smaller processes and to maintain the same levels of
gain for previous generation amplifiers, designers must design with longer
channel lengths to maintain gain from reduction in Lmin. This move inevitably
affects MOS conductance levels.
5
CLM 
Wdepletion
1
1
. Lambda is proportional to the inverse of the


Vds

V
V
ds
Early
 Leff
Leff
effective channel length. Units are usually expressed in um/V.
59
Conductances of DI FET
Small signal conductances are ratios of small changes in current to the
terminal voltages. Most circuit texts reference the changes to the source rather
than the bulk, however the bulk may be considered as another gate called the
backgate. Since the bulk is connected to the source this effect is eliminated and
the reference is taken from the source. The trans-conductance in weak inversion is
thus proportional to the current by the following relation and can be considered
independent of W/L by reasons of the partial derivative. The reason for calling it a
“trans-conductance” is because the gate indirectly controls the resultant channel
current. According to eq. 4.11, the design should maximize trans-conductance to
achieve high injection efficiency. Unlike bipolar, the  effect reduces the
apparent MOS input gain.
gm 
I channel
Vgs
Io

 pVg
Vthermal
  Weff
 q

tchannel D p N1 e
Vgs 
Leff


Vs
 VVint
Vthermal
thermal
e

e









(3.27)
I channel
gm 
p
Vthernmal
 V V
 Weff
 p g s  p I DI q
tchannel Dp N1  e Vthermal 
 q

Leff
kT


(3.28)
Examining the drain and source conductances are a result of the reverse
and forward currents respectively. As opposed to the “trans-conductance”, the
source and drain conductances are true conductances and measure directly, the
small signal adaptations to tiny perturbations. Therefore the source conductance
represented by the forward current is:
60
gs 
I f
Vs

 
 Ioe
Vs 

 pVDI Vs
 pVDI Vs
 I e Vthermal
 o

Vthermal

Vthermal

I DI
Vthermal
(3.29)
The drain conductance dominated by the reverse current includes the Early effect.
In weak inversion saturation this is essentially zero.
gd 
I r
 
 Ioe

Vd Vd 

 pVDI Vint
Vthermal
 pVDI Vint
 I e Vthermal
  o

Vthermal


I DI
VEarly
(3.30)
When trying to formulate a 1st order approximation for output impedance we may
use the “residual source-drain conductance” [19]. Since the drain conductance is
very small and contributes very little, the difference between drain and source
results in this residual conductance. Therefore, to first order the channel
conductance in saturation is the saturated current divided by the Early voltage.
g ds 
I DI
VEarly
(3.31)
In lieu of bulk referenced conductance vs. source referenced conductance, the
channel conductance in weak inversion may be represented by the drain
conductance in eq 4.25. The bulk transconductance is only dependant on the
forward current from the source and the gate correction factor while it neglects
the reverse current term from the drain conductance and the Early effect.
gb  g s  g m  g d 
1    I
p
Vthermal
61
DI
(3.32)
DC Bias Point of SCFET
Conductances of SCFET
Single MOS Skimming Pixel
Self-Cascode Skimming Pixel
Self-Cascode with MOS Capacitor
Pixel Comparisons
Charge Subtraction Concept with Non-Linear MOSCAP
MOS Capacitor System
Circuit Description
62
Chapter 4: Associative Issues & Limitations with
Current Skimming
This chapter explores important design information for current mode
skimming in the long wave infrared. To date there has been no uncooled dc bias
array that has implemented a per-pixel current skimming scheme. There is much
debate in the field as to whether current skimming is 1) feasible on the pixel level
and 2) whether it contributes more spatial noise due to process variations. The
chief goal of this chapter is to help designers avoid various obstacles, ability to
understand, and weigh tradeoffs for implementing a successful current skimming
approach.
Subthreshold Transistor Mismatch
Operating under room temperature conditions, uncooled readout arrays
may suffer significantly from device[is this true] mismatch, which translates into
a spatial noise variation across the array. Mismatch may be organized into four
categories according to Pavasovic et al [3]: random variations, edge, striation, and
gradient effects. Defining the above mismatches from Pavasovic, we have the
following explanations: 1) edge effects are when transistors behave differently
from the die borders to their centers. 2) The striation effect is a variation in
channel current which follows a “sinusoidal variation in the space domain.” 3)
gradients are referred to as “long range variations” across the die[3, pg. 78].
Migration to large format IR focal plane arrays [e.g. 1024 x 1024] require smaller
process geometries[e.g. .25um or .18u]; therefore required pixel sizes of many
63
uncooled readout arrays have been reduced from 50um2 to 20um2. Again
Pavasovic concludes from [3,pg.82] that “purely random variations can be used to
predict the dependence of transistor matching on device area.” The standard
deviation of subthreshold channel current is inversely proportional to transistor

1
area 
 Leff Weff


 . Therefore smaller uncooled readout pixels will suffer a


reduction in pixel-to-pixel current matching due to smaller individual elements.
This matching will include the direct injection input FET, the SCFET skimmer,
and the source follower. The fact that a self-biased cascode is added to the pixel
circuitry would be included in the spatial noise component by the above definition
because the skimmer too would be subject to scaling and random variations while
it adds in an uncorrelated fashion.
Small device geometries operating at subthreshold current causes the drain
current to be “strongly dependent” on process parameter variation. Adreou et al.
points out that the drain current is especially dependent on the pre-accumulated
exponential (zero-bias current) Io current [1] which is process dependent. The
following analog design guide was labeled for optimal matching by Eric A.
Vittoz[5]. These pertain to all IC technologies and are an excellant rule to follow
where applicable.
Layout Design Guide for High Performance Analog Design:
1) Devices to be matched must have the same structure.
2) Devices should maintain the same operating temperature (assumes power
dissipation is very low).
3) Devices must have same physical size; (e.g. capacitors must have same
aspect ration and transistors have same W and L).
64
4) Layout must incorporate a minimum distance rule to “take advantage of
spatial correlation of fluctuating physical parameters.”
5) Implement common-centroid geometries used to cancel parameter
gradients.
6) Identical orientation eliminates “dissymmetries” as a result of anisotropic
etching in the manufacturing process. In particular, the channel currents
(Isd) be parallel to achieve optimal matching.
7) Devices to must have the same physical surroundings in the layout. For
example a row of current mirrors will have dissimilar currents from the
transistors on the ends.
8) Analog devices must be non-minimum geometries. This helps to reduce
the “effect of edge fluctuations and to improve spatial averaging of
fluctuating parameters.”
Subthreshold Region Operation
One of the most difficult challenges in controlling the self-biased cascode
current mode skimmer is the required precision in manipulating the gate potential.
This section will briefly explain the more subtle details of why subthreshold
operation contains higher mismatch. We begin by restating the fundamental
equation for the self-cascode current mode skimmer:
I scfet









   nVg    Vs   Vd  


  U t    U t   U t     Vds 2  

I to e
e
e
1  


   VE 2  
  Vds 2   



1  
  

V
E
2




   



V
ds1


1 


V
  E1   

(4.1)
where
W 
  
 L 1
and
W 
  
 L 2
65
Because the channel current is exponentially related to the gate voltage the
gate would need to have a very fine tuning capability on the order of 1-3mV. The
skimming current will be fundamentally set by Io and proper SCFET geometry..
IRCHIP2 implemented a test pixel with 17 parallel SCFETs in row. A problem
with this design are edge effects where the currents may not divide equally and
were not equipped with dummy transistors. IRCHIP3 incorporated a common
centroid current mirror array biasing the self-cascode skimmer. By connecting
several SCFET’s in parallel and using an off chip variable resistor I was able to
induce changes on the gate of the skimmer. The improved design uses a 1M
potentiometer, which has 25 turns and therefore a sensitivity of 40k. The
accuracy experimentally is set by a single turn in the variable resistor. One turn of
the off-chip resistor yields about a V  2mV on the SCFET gate which translates
to a I  1nA in channel current. Two turns approximately yield V  5mV and a
I  2nA in channel current. A major draw back is the bias array occupied a
considerably large area. The advantage is that this biasing scheme is insensitive to
temperature variations, lower noise, decreased edge effects, and decreased
random variations by incorporating a common centroid layout scheme. Using an
external voltage supply may introduce AC line noise on the order of 10-3 volts,
which decreases sensitivity in the skimming control. Fundamentally, for per-pixel
skimming in the LWIR to be feasible the control on the skimmer gate will be such
that the skimming sensitivity is  1nA. Less sensitive approaches will function,
but calibration will be very difficult. [how does this compare to using a
straight power supply with mV accuracy] what is the effect on the gate.
66
Long channel lengths help to reduce channel length modulation by
  Vds 2  
1  

  V 
VE 2  


increasing the Early Voltage. Therefore the term
and 1   ds 2  
  Vds1  
  VE 2  
1 

  VE1  
become insignificant. The SCFET current can be reduced to:
I scfet
  nVg 

U t 
   

 I to e
   
  Vs   Vd  
 e U t   e U t  




(4.2)
The last section in this chapter explains the approaches on per-pixel
skimming concepts. The next section explains the inherent mismatches when
attempting to match either currents or voltages and which is the best approach to
take in a low power design.
Current Mismatch vs. Voltage Mismatch
Focal plane readout circuits are structured (p16) in a 2-D matrix such that
patterns are repeated. Therefore matching properties of transistors and devices
alike are critical to high analog performance. According to [5], matching of
similar adjacent transistors are characterized by two “statistical values”: the
threshold mismatch VT which could account for 1-20mV and
 Weff
 Leff

   Cox 
 
which falls in the range of .5-5%. With processes
 ;


constantly maturing the threshold mismatch should be vary small.
67
The rms value for threshold mismatch is labeled  VT and


labeled as
  . Vittoz also suggest that these parameters are very weakly correlated and their
mean value is zero in an efficient layout. Drain current mismatch is when two
devices have the same gate and source voltages like in a current mirror for
example [5,9].
 Ids   
2
g

  m  VT 
 I ds

2
(4.3)
Subthreshold region operation results in a maximum of drain current mismatch
around 12% for an rms threshold  VT of 5mV[6] . This is not surprising
considering the
gm
ratio is at a maximum in weak inversion. As the transistor
I ds
enters strong inversion it’s rms mismatch approaches limits imposed by the
mobility and settle to  2% represented by   . Flicker noise in weak inversion
may cause the rms threshold voltage mean to increase to larger levels as opposed
to strong inversion.
The gate voltage mismatch of two transistors (differential pair for
example) with identical currents exhibit rms mismatch of:
V  
g
2
VT
I

  ds   
 gm

2
(4.4)
Thus weak inversion transistors have minimum mismatch in gate voltages
of  VT and increase in strong inversion as transconductance decreases.
68
Body Effect in Self-Cascode
There are few processes occurring in the self-cascode to explain why body
effect is not really an issue, in fact the apparent floating source voltage on the
cascode transistor seems to improve the common gate gain. Depending on the
self-cascode configuration will determine whether body effect could be a
problem. Since the design was implemented in an n-well process (p-type
substrate), the bulk of an nfet cannot be connected to its source unless it lies in a
well. The bulk is at substrate potential and therefore may be neglected from the
equations. However, the source voltage is 4Vt (100mV) above the substrate
potential and forward biases the source-substrate junction. The body effect can
also occur if the substrate potential is static and the source varies with respect to
the substrate [10]. The source voltage is extremely stable for the range of applied
gate voltages for this particular application. The source potential of the cascode
transistor is exclusively determined by the difference in gate potential of the
composite device and surface potential required to bias the cascode transistor.
Excluding both the body and Early effect the voltage gain of the cascode is
determined by the ratio of its source to drain conductance.
Acg  
  
     Ioe


Vt
Vg Vs
Vt
gs

Vg
gd
  
Vt
     Ioe


VE

VE
Vt
If we factor the body effect in the equation the result is as follows:
69
(4.4)
Acg  
gs

gd
  

 Ioe
   
Vt
Vg Vs
Vt
Vg
  
Vt
     Ioe


VE
 I f

Vt
If

VE
Vt
(4.5)
VE
Since the self cascode is operating in subthreshold the Vbs = -4Vt is not
significant enough to cause noticeable body effect. The structure is unique in the
sense that the floating node remains saturated and stable enough to allow the
source junction to provide a constant stream of electrons in subthreshold while
having extremely large output resistance. Increasing the gate potential would
eventually increase the floating nodes’s potential and could possibly suffer from
some body effect by increasing the cascode’s threshold voltage. The result would
be a reduction in cascode gain, output resistance, and integration times would not
be as long.
70
Vd
0
Vg
Vs = 4Vt ~ 100mV
Vb = 0V
Vbs = -4Vt
0
Figure 4.1: The floating node’s potential may rise with
increasing gate voltage or the cascode slipping into moderate
inversion. Both mechanisms may cause some body effect for
the cascode transistor by raising its threshold voltage and
slightly increasing its conductance.
Effects of MOS Scaling
Readout design relies mostly on analog features to pre-process the
photonic signal. Therefore non-minimum geometries are often used. Scaling may
be beneficial for the self-cascode current skimmer in some instances since it
requires so little supply to operate and provides excellent output resistance. Above
all, gate lengths below .25um will dominated by short channel effects. As supplies
decrease the gate oxide is made thinner which results in a higher oxide
capacitance. The doping is increased to maintain the proper electric fields. The
current design uses a standard 0.5um 5V process as a test bed. The following
subsections highlight some of the most important aspects of scaling down the selfcascode skimmer which gives the designer background for improved operation.
71
Power Supply
The table below gives a very good description of minimum gate lengths
and corresponding power supply. Some foundries offer a thicker oxide mask,
which allows the process to tolerate a higher supply or modified pads to handle a
higher voltage for I/O pads. With decreasing supply, available signal dynamic
range for readouts is reduced. For example, designing readouts that incorporate
source followers in a voltage mode readout will suffer from reduced analog swing
and larger offset (a result of fixed pattern noise) [11]. Since supply is reduced gate
overdrive Vgs  Vt is reduced for the same reduction in threshold voltage.
Therefore static off-state leakage currents increase due to increased subthreshold
leakage current[7]. In fact, tunneling currents such as junction and gate oxide will
increase with the decrease in minimum lithographic feature size [11]. Along with
the reduction in threshold, the threshold variations will increase. This effect
would render the self cascode useless if no control was possible on the gate. To
assuage the reader and designers, current state of the art infrared readouts are
currently using .25um design rules and are beginning to migrate towards .18um
rules. Though no scaling tests have been performed on the current mode skimmer
at these geometries, the self cascode skimmer should perform very well.
Implementing this design below 2.5V would definitely pose many design
challenges.
Standard CMOS Process Voltage Supply
.13um (~2003)
1.2V/(2.5V)
.18um (2002)
1.8V/(3.3V)
72
.25um (~1998)
2.5V/(3.3V)
.35um (~1997)
3.3V(5V)
.5um (~1995)
5V/(3.3V)
.8um
5V
1.5um/2um (~1990)
5V
Table 4.1: Table was adapted from the MOSIS foundry. http://www.mosis.org
In lieu of decreasing the supply and threshold voltage, the doping levels
are increased which reduces overall effective mobility and subthreshold slope
increases.
1
 
n
Cox
qN  si
Cox 
2 s
(4.6)
This means that  will decrease [7] resulting in more leakage current.
Gate Oxide Thickness
As the gate oxide is made thinner there are some advantages and
disadvantages. The capacitance per unit area is greatly increased, but these
capacitors are inherently non-linear. A .25um process can provide  5fF/um2
which is a lot of capacitance in a smaller area compared to the linear capacitor
options in a .5um process of  1-2fF/um2 .With proper layout, biasing and
operating range, the non-linearity may be avoided. As LWIR uncooled infrared
readouts are scaled, the MOS capacitor is the only useful charge storage element
able to handle the high photon density.
73
Layout &Geometry of SCFET
Early voltage may increase as technology scales down as a result of
increased substrate doping concentration [12]. This would allow a scaling of the
SCFET skimmer to occupy a smaller area with the same performance.
Maintaining proper geometrical ratios of the self-cascode are essential to
successful current subtraction. Cascode ratios of 14:1 to 116:1 versus output
conductance have shown a decreasing output conductance relationship with
increasing cascode ratio [Philippe]. Also, reports indicate that as the ratio of the
bias transistor length to cascode length increases, the effective output resistance
increases and saturates for a ratio about 6:1[Pain’s Phd]. Uncooled infrared
readout pixel sizes are limited between 20um and 50um unit cells, therefore
minimum ratio and maximum performance are desired.
A true self-cascode must a have a large aspect ratio of cascode transistor
to bias transistor to function properly, otherwise the device cannot operate
effectively. Ideally, one should make the width of the cascode as wide as possible
and have a small length while making the bias transistor length as long as possible
and a narrow width. Having the geometry where both strips of polysilicon are
identical is not a true self-cascode and will suffer from a non-flat I-V curve
indicating a non-ideal current source for skimming applications at any
temperature. Designers will argue the fact that a regular cascode structure has
similar if not lower output conductance than the self-cascode. The fact remains
the self-cascode saturates more quickly and requires less voltage headroom while
utilizing a single poly gate. The self-cascode also assumes the “best bias voltage
74
for the cascaded device” [JHU]. There have been reports on successful current
skimming (implementing a cooled LWIR QWIPs array) with the configuration in
part c of figure x below. This however is not representative of a true self-cascode
design. The results emulate a self-cascode, but are essentially a regular cascode.
Proper cascode to bias transistor geometry must be maintained and
1. The
shielding property or screen gate effect is reduced by a reduction in early voltage
(e.g. shorter channel length on the bias transistor and/or unity ratio). The
transistors in this configuration must be operating in the same region. Correct
operation must have the cascode transistor in weak inversion and the bias
transistor in moderate inversion. In a scaled down version (as a current skimmer),
this design ratio would not function properly due to increased conductance
variations in the output. The fact of their apparent success was more than likely a
result of cooling the array down to 84 K where circuit operations perform much
better than at room temperature.
75
gds vs.SCFET ratio
2.000E-08
1.500E-08
Vgs = 700mV
gds (A/V)
Vgs = 800mV
1.000E-08
5.000E-09
0.000E+00
1.29412
3.03193
6.39446
14.1211
SCFET ratio
(W/L)c/(W/L)b
Figure 4.2: Output Conductance versus self-cascode ratio. Vds was varied from 0-5V in
100mV increments. Much improvement with SCFET operation can be obtained with
ratios of 32:1 and greater. The original idea of the self cascode called for large ratios on
the order of 100:1[JHU, JPL], but excellent self-cascoding can be achieved for values
less than this. More than likely, the self-cascode implemented in a LWIR uncooled
skimming pixel will have a ratio of no more than 8:1. This condition is set by the pixel
area requirement.
76
Figure 4.3:
Noise
This thesis focuses on high background uncooled applications in the
LWIR that suffer from high dynamic range requirements, detector bias control,
and large charge handling capacity. [Pains Phd]. The background suppression’s
function is to allow the pixel to integrate more signal charge. As a result, the
77
integration times will increase and front end noise bandwidth (includes detector to
pixel output) should integrate mostly signal.
Temporal Noise
Skimming primarily reduces the temporal noise indirectly through the
noise bandwidth by integrating longer. Excluding detector noise components, the
temporal components in the pixel are generated by the transistor white noise (or
channel thermal noise). Longer integration times will increase SNR thus
increasing pixel sensitivity. Factors that could adversely affect the integration
times are parasitic variation. The main temporal noise component to contend with
will be the
kT
noise of the pixel.
C
Spatial Noise
Before background suppression is even applied there are spatial noise
components such as fixed pattern noise due to non-uniform detector input currents
and fixed pattern noise due to gain non-uniformity (source follower)[13] that
negatively impact the array’s performance. First, the assumption that the selfcascode skimmer will be subtracting the same background cannot be implemented
due to various flux levels over the entire uncooled array. The section of
Programmability addresses very important concepts of implementing background
suppression techniques. Adding the skimmer to the pixel presents the challenge of
not introducing additional noise to the pixel. The self-cascode will add some
additional noise, but the hope is that this will be offset by the reduction in
temporal noise components.
78
Threshold voltage mismatch will lead to different drain currents of the
skimmer, which also lead to a spatial component. These randomly distributed
time-invariant offsets are caused by variation in doping concentrations and Cox
gradients [Calist]. Slight variation in oxide capacitance could translate to less or
more charge required to create an inversion layer, which subsequently alters the
threshold voltage.
Ways to reduce the reset noise (temporal noise component) is to
implement a CDS or correlated double sampling technique. Implementing NUC
or non-uniformity correction methods will reduce the spatial noise component.
There are several mechanisms to reduce the readout noise, however the goal is to
limit the amount of power dissipation and chip area.
Sensitivity
Noise equivalent temperature difference is essentially the benchmark for
pixel and array sensitivity. There are some issues to be addressed on the direct
injection current and skimming current resolution and their associated junction
leakages.
I di  I IR _ signal   I jlk _ di  I N _ det 
(4.7)
The concern is the noise from the leakage currents at the junctions plus the
current noise due to the detector. To resolve sensitive changes in bolometer
resistance, the current noise due to leakage at the source (input) of the direct
injection transistor plus the current noise due to the detector must be less than the
resultant IR current signal change. The junction leakage current is computed by
79
multiplying the area of the junction by the leakage per unit area. A typical 0.5um
process junction leakage parameter is  10fA/um2.
A basic assumption for this thesis is the substrate of the readout array is
thermally stabilized to a known value ~ 300K. Therefore leakage currents should
not be a problem unless the substrate temperature is left floating. At high
temperatures and with a variable substrate temperature, skimming would be
useless due to a high level of leakage currents.
NET
Noise equivalent temperature is inversely related to the integration time.
The following equation shows the noise bandwidth of the pixel integrator.
N BW  

0
sin  f  int 
 f  int
df 
1
2 int
 Hz 
(4.8)
Current skimming will directly impact the pixel sensitivity by making the
effective charge capacity larger. This assumes that the implementation
mechanisms of per-pixel skimming are successful. With no skimming and 20nA
input current, a maximum well potential of 5V, and a 1pF storage capacitor we
have the following result.
 int 
5V 1 pF
 250us
20nA
and
N BW  2kHz
Current Skimming at 97.5% would yield an increase in integration time by
a factor of 40.
 int 
5V 1 pF
 10ms
500 pA
and
80
N BW  50 Hz
In practice the, the maximum well potential is usually not achieved for the
direct injection pixel because of reverse biasing the drain junction of the direct
injection transistor. With a 1V bias maintained across the detector, this leaves a
charge well up to about 4V. The designs in this thesis were able to have dynamic
ranges of about 2.5-3V. The reason for not achieving full well capacity was that a
reference was implemented to prevent non-linear outputs at the source follower.
Nonetheless, this increased sensitivity may be achieved by designing a smaller
capacitor without saturating the well by skimming. We can state the obvious fact
that the noise equivalent temperature difference is limited by well capacity.
Bolometer Bias Variations
LWIR detectors benefit from a constant bias during integration with control
on the order of millivolts[13]. Large bias variations could severely affect injection
efficiency by altering the transconductance, 1/f noise of the detector, and the
responsivity. Variations in pixel input current could make current skimming very
difficult. Therefore tight control over the gate node maintains stability. With both the
direct injection and current skimmer operating in subthreshold, detector variations are
especially undesired.
81
Chapter 5: Signal & Noise
Signal
Thermal Bandwidth and Electronics Bandwidth
Bolometer Transfer Function
H bolometer ( ) 

1 
1


GE  j th  1
where  th 
Cth
GE
(5.1)
Pixel Transfer Function
H e   
1
j e  1
where  e  RC
(5.2)
Noise Sources
The following section presents the dominant noise sources resulting from
the readout pixel and does not include the detector or other system noise sources.
The basic function of this pixel is a current–integrating bolometer thermally
suspended over the readout pixel. Depending on the actual readout method
(voltage or charge mode) defines the output variable. In this thesis, the readout
method chosen was the voltage mode. The emphasis is on subthreshold noise
mechanisms, however above threshold noise equations will be presented as well.
Thermal and shot noise sources are assumed to be white, while 1/f noise is pink
(for low frequency operations). All of the noise mechanisms are assumed
uncorrelated and may be summed by the root-mean-square method. In the ideal
case, noise introduced by the readout should be negligible compared to the
detector and background noise (detector limited readout).
82
Flicker Noise
The power spectrum varies inversely with frequency and is found in all
active devices and some discrete passive devices[7]. Since uncooled staring arrays
operate at low frequency, much of the dominant noise mechanisms in the readout
are 1/f. The source of 1/f noise has been a debated topic for many years. The
generally accepted view is that carriers gain enough energy to occupy surface
traps within the gate oxide or surface states and then are released some time
constant later. These events occur between the silicon and silicon dioxide
interface. The process is always associated with a DC current. 1/f noise theory is
divided into two main components: 1) carrier density fluctuation model
(McWhorter) and 2) mobility fluctuation model (Hooge). The carrier density
model is based off of a tunneling probability of a carrier being captured and
emitted from the gate oxide. The amount of time a carrier is held in a trap is
directly related to its tunneling distance from the oxide. In lieu of this
dependence, there is a spatial distribution of trap time constants across the oxide.
This explains the power spectral density of fluctuations in the concentration of
carriers [16]. The mobility fluctuation theory applies to fluctuations in bulk
mobility. In general, p-channel devices have lower 1/f noise within the same
process and similar geometries. The tunneling barrier for holes is much larger
than electrons as well as different electron and hole effective masses, which lead
to different tunneling parameters and oxide trap densities. Another interesting
viewpoint of flicker noise is that the trapped charges that exit and enter the defect
states essentially modulate the surface potential and hence the threshold voltage.
83
Therefore, flicker noise may be viewed as a “dynamically changing threshold
voltage” [7]. Flicker noise in n-channel devices are dominated by the carrier
density fluctuation model, while p-channel device noise is dominated by bulk
mobility fluctuations [17]. The carrier density fluctuation model assumes no gate
bias dependence ranging from subthreshold to strong inversion. The current
power spectral density for drain current fluctuations is assumed to be:
S I _1/ f
f

 A2 


 Hz 
K f ID
fCox L2eff
(5.3)
The Kf is a experimentally determined coefficient and is the same for all
regions of operation. The integrated noise band  f is assumed for a 1Hz. One
can refer the noise to gate by the dividing by the transconductance factor. Noise
power spectral densities are inversely proportional to area. So to achieve superior
analog performance and lower 1/f noise one must consider making the device
dimensions large.
SVg _1/ f
f

S I _1/ f
gm2
V2 


 Hz 
(5.4)
Shot Noise
Shot noise is considered to be discrete random arrivals of carriers crossing
and energy barrier. This noise must contain a DC current flow (where thermal
noise does not)[7]. The pixel contains subthreshold transistors and the channel
thermal noise is really considered a 2-sided shot noise term rather than a thermal
noise. Interestingly enough, measurements for 100fA-100pA current levels
observed only white noise (hence shot noise), but for larger subthreshold currents
84
(> 4nA) flicker noise was only observed [7]. The level of subthreshold currents
depends on the W/L ratio and gate voltage. This theory is based upon two
independent carrier processes occurring at the source and drain: a forward current
If from drain to source and a reverse current Ir from source to drain. In the linear
region of weak inversion, the shot noise component is:
SI _ thermal
f
 4qI sat
Vds  4Vt
(5.5)
As we transistion from linear to saturation the shot noise component from
the drain disappears.
SI _ thermal
f
 2qI sat
Vds  4Vt
(5.6)
Both the direct injection and self-cascode transistors will use the above equation.
Reset Noise
Capacitors do not generate any noise themselves, however they do
accumulate noise from other noise sources. The integrating current bolometer
functions as a first order low pass filter containing a resistor in parallel with the
Equivalent Noise Model
Vno(f)
R
C
0
0
Figure 5.1: Capacitor noise model of a 1st order low pass
Filter.
85
integration capacitor. Any reset operation that contains a switch will suffer
from kTC noise. This noise is represented by the residual noise left on the
capacitor the moment the switch is turned off.
VR ( f )  4kTR
(5.7)
The noise bandwidth is given by integrating the thermal noise of the
resistor over all frequencies multiplied by the system transfer function. The
transfer function of a first-order low pass filter is:
Vno
1
1
(f)

VR
1  sRC 1  j 2 fRC
(5.8)
We then multiply the white noise source (resistor thermal noise) and the
square of the system transfer function to obtain the noise power. To obtain the
power spectral density, the noise power is integrated over all frequencies. The
integrated noise power is called the noise power spectral density (or noise power
spectrum).
V
So ( f )  S R ( f )  no
VR

Vc  4kTR 
2
0

dx
 1 x
2
2
 4kTR 
1
1   2 fRC 
Vc 
df
 arctan()  arctan(0) 
0
Vc 2 
2
1
1  4 f 2 R 2C 2
2

2
; x 2 fRC; df 
dx
2 RC
4kTR  kT
 
2 RC 2 C
kT
C
(5.9)
(V rms)
86
The rms noise voltage across the capacitor terminals is eq(?) regardless of
the resistance seen across it. This implies a set fundamental limit of noise seen
across a capacitor [19]. Smaller resistances have a lower noise spectral density
but a higher bandwidth. Larger resistances have larger noise spectral densities but
lower bandwidths. Contrary to statements made in [Calist], smaller integration
capacitances will increase kTC. One point to make clear about capacitor size,
pixel sensitivity, and current skimming is that reducing pixel size implies a
smaller capacitor. This increases sensitivity, however the kTC will increase no
matter what. In addition, this pixel size reduction implies a process scaling to a
lower supply which further limits dynamic range. The benefit of current
skimming is seen when the supply is unchanged and the capacitor is reduced; this
does not decrease kTC noise but increase it. Reset noise is also eliminated by the
method of correlated double sampling (CDS). Circuitry measures the output
before and after reset and then subtracts the difference to cancel out the residual
noise present on the capacitor. Another method of reducing the kTC noise is to
reduce operating temperature. This method is unacceptable for uncooled
applications and should not be considered. A final method of reset noise reduction
is by implementing a switched capacitor filter. If many samples are taken during a
frame and then averaged over the frame, the final result is a reduced noise level.
The reason this technique is effective is the sampled values add linearly, but the
noise adds as the root of the sum of the squares. This method increases circuit
timing and complexity[10,19]
87
Thermal Noise
Thermal noise is caused by random thermal motions of carriers when the
net average current remains zero. The spectrum of thermal noise is proportional to
absolute temperature.
Vn 2
 4kTR
f
 V 


 Hz 
Theoretical Noise Analysis
Single MOS
Self-Cascode Current Mode Skimmer
88
(5.10)
Chapter 6: IC Test CHIP Design
IRCHIP1
Chip Description & Function
This first test chip’s goal was to demonstrate the concept of current
skimming by utilizing a linear array of self-cascode current mirrors to bias the
self-cascode in the pixel. The input current was set by an off chip potentiometer
whose current was driven through a p-channel current buffer (common gate
configuration). The current buffer’s geometry was identical to the direct injection
transistor to achieve uniformity and relatively equal currents. The diode
connected current mirrors generated a voltage drop sufficient to bias the gate of
the self-cascode with reasonable accuracy.
89
Integration
Capacitor
(Poly2-Poly1)
Well Contact
Direct Injection
Transistor
Vref
Reset
SelfCascode
Skimmer
Source Follower
Substrate
Contact
Figure 6.2: LWIR direct injection current skimming pixel.
MOS
Capacitor
Figure 6.3: LWIR direct injection current skimming pixel with experimental MOS
capacitor The MOS capacitor is used as another form of background
suppression called charge subtraction.
90
 13.2u 
Mc  

 5.1u 
 10.2u 
Mb  

 25.2u 
 13.2u 
Mc  

 5.1u 
 10.5u 
Mb  

 12.3u 
 13.2u 
Mc  

 5.1u 
 10.2u 
Mb  

 5.1u 
 13.2u 
Mc  

 5.1u 
 10.2u 
Mb  

 5.1u 
 13.2u 
Mc  

 5.1u 
 10.2u 
Mb  

 55.65u 
Figure 6.4: Experimental self-cascode transistors with a fixed cascode ratio
and a variable bias transistor ratio.
Common Gate Current Buffer (p-channel)
SCFET Current Mirror Array
Current Mode Skimmer
Figure 6.5: The skimmer is biased by an off-chip resistor. Then the current is
buffered into a current mirror being divided into 17 paths.
sensitivity is controlled by the number of current paths in the mirror.
91
Simulation & Test Results
The following self-cascode I-V data was taken from MOSIS run T3AJ
(AMI C5N 0.5um) with device dimensions above in Figure 6.4. The curves
generated were taken at various gate voltages ranging from 500mV to 2V.
92
Vgs = 600mV
1.80E-08
1.60E-08
1.40E-08
1.20E-08
Mc: 13.2u/5.1u Mb: 10.2u/5.1u
1.00E-08
Ids
Mc: 13.2u/5.1u Mb: 10.5u/12.3u
Mc: 13.2u/5.1u Mb: 10.2u/25.2u
8.00E-09
Mc: 13.2u/5.1u Mb: 10.2u/55.65u
6.00E-09
1.40E-091.40E-09
1.20E-091.20E-09
1.00E-091.00E-09
8.00E-108.00E-10
4.00E-09
6.00E-106.00E-10
4.00E-104.00E-10
3 . 5 0 E+ 0 0
3 .. 0
50
0E
E+
+0
00
0
0
0 . 0 0 E+ 0 0
2.00E-102.00E-10
0.00E+00
0.00E+00
2.00E-09
4.80E+00
4.50E+00
4.20E+00
3.90E+00
3.60E+00
3.30E+00
3.00E+00
2.70E+00
2.40E+00
2.10E+00
1.80E+00
1.50E+00
1.20E+00
9.00E-01
6.00E-01
3.00E-01
0.00E+00
0.00E+00
Vds
Vgs = 700mV
1.60E-07
1.40E-07
1.20E-07
Ids
1.00E-07
Mc: 13.2u/5.1u Mb: 10.2u/5.1u
Mc: 13.2u/5.1u Mb: 10.5u/12.3u
8.00E-08
Mc: 13.2u/5.1u Mb: 10.2u/25.2u
Mc: 13.2u/5.1u Mb: 10.2u/55.65u
6.00E-08
4.00E-08
2.00E-08
0.
00
E
3. +0
00 0
E
6. -0
00 1
E
9. -0
00 1
1. E-0
20 1
E
1. +0
50 0
E
1. +0
80 0
E
2. +0
10 0
E
2. +0
40 0
E
2. +0
70 0
E
3. +0
00 0
E
3. +0
30 0
E
3. +0
60 0
E
3. +0
90 0
E
4. +0
20 0
E
4. +0
50 0
E
4. +0
80 0
E+
00
0.00E+00
Vds
Figure 6.7:
93
Vgs = 800mV
8.00E-07
7.00E-07
6.00E-07
5.00E-07
Mc: 13.2u/5.1u Mb: 10.5u/12.3u
4.00E-07
Mc: 13.2u/5.1u Mb: 10.2u/25.2u
Mc: 13.2u/5.1u Mb: 10.2u/55.65u
3.00E-07
2.00E-07
1.00E-07
4.80E+00
4.50E+00
4.20E+00
3.90E+00
3.60E+00
3.30E+00
3.00E+00
2.70E+00
2.40E+00
2.10E+00
1.80E+00
1.50E+00
1.20E+00
9.00E-01
6.00E-01
3.00E-01
0.00E+00
0.00E+00
Vds
Vgs = 900mV
2.50E-06
2.00E-06
Mc: 13.2u/5.1u Mb: 10.2u/5.1u
Mc: 13.2u/5.1u Mb: 10.5u/12.3u
1.50E-06
Mc: 13.2u/5.1u Mb: 10.2u/25.2u
Ids
Mc: 13.2u/5.1u Mb: 10.2u/55.65u
1.00E-06
5.00E-07
0.00E+00
0.
00
E
3. +0
00 0
E
6. -0
00 1
E
9. -0
00 1
1. E-0
20 1
E
1. +0
50 0
E
1. +0
80 0
E
2. +0
10 0
E
2. +0
40 0
E
2. +0
70 0
E
3. +0
00 0
E
3. +0
30 0
E
3. +0
60 0
E
3. +0
90 0
E
4. +0
20 0
E
4. +0
50 0
E
4. +0
80 0
E+
00
Ids
Mc: 13.2u/5.1u Mb: 10.2u/5.1u
Vds
94
Figurexxx
95
Time (s)
9.53E-04
8.52E-04
7.52E-04
6.52E-04
5.51E-04
4.51E-04
3.50E-04
2.50E-04
1.50E-04
4.92E-05
-5.12E-05
0.8
-1.52E-04
-2.52E-04
-3.52E-04
-4.53E-04
-5.53E-04
-6.54E-04
-7.54E-04
-8.54E-04
-9.55E-04
Pixel Output (V)
0.9
Current Skimming @ 78.5%
(Iskim = 15.7nA, Idi = 20nA, DR = 680mV, tint = 212us)
Pixel Output (V)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
96
97
98
IRCHIP2
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Chip Description & Function
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Test Results
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IRCHIP3
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Chip Desription & Function
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Test Results
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99
Future Considerations
100
Conclusion
101
References
102
103