Download 3. Crystal Oscillators for Industrial Applications

B.TECH II YEAR II SEM
ACADEMIC PLANNER FOR
AY-2013-2014
DEPARTMENT OF
ELECTRONICS & COMMUNICATION ENGINEERING
CMR ENGINEERING COLLEGE
KANDLAKOYA (V), MEDCHAL (M), R.R DIST. - 501401
Vision
Vision of the Department:
To promote excellence in technical education and scientific research in electronics
and communication engineering for the benefit of society.
Mission of the Department:
 To impart excellent technical education with state of art facilities inculcating
values and lifelong learning attitude.
 To develop core competence in our students imbibing professional ethics and
team spirit.
 To encourage research benefiting society through higher learning
Quality Policy
Our quality policy is to continuously strive for over-all development of the department
and the students. Our policy is to provide best inputs to the students and to develop them
to imbibe the spirit of professionalism, dedication & commitment.
Dress Code


We encourage our students to be formally dressed on and off campus. This
nurtures the feeling of equality and belongings among the students fraternity.
All students are required to carry Photo Identity card at all the time while in the
campus.
A Bird's Eye view about the Institution
CMR Engineering College, popularly known as CMREC is the brain child of the
clairvoyant CH.Narasihma Reddy. CMR Engineering College is one of the best
engineering Colleges for aspiring engineering students. It is one of the newly established
Colleges by CMR Engineering Educational Society. CMR Engineering College was
established in 2010 in 10 Acres and built up area of 4,785.78 Sq.m. with a single minded aim to provide a perfect platform to students in the field of Engineering,
Technology for their academic and overall personality development. The college has a
very good academic activity which focuses for the campus placement.
The college is approved by the All India Council for Technical Education, New Delhi
and is affiliated to JNT University Hyderabad. The CMREC is offering the three under
graduate courses in ECE, CSE and MECH, and post graduate course in ECE and CSE.
Today, CMREC has grown in leaps and bounds and it is no wonder that CMREC has
become cynosure of the eyes of many, hankering for the distinguished centre of
technological
learning.
Discipline, Character and Education are the three tenets for which CMREC stands, is
certainly the haven where values blend seamlessly to churn out engineers for future.




Collaborating with Institutions and Industries.
Promoting research and development programme for the growth of economy.
Disseminating technical knowledge in the region by continuing education
programmes.
Aiming at continual improvement of all round development of students
Department Profile
Our Department was established in the year 2010 with the U.G Programme B.Tech in
Electronics and Communication Engineering with an intake of 120 students, it was
increased to 180 in the year 2012 and in the year 2013, the intake was increased to 240
students. P.G Programme M.Tech in Embedded Systems with an intake of 24 students
was introduced in the year 2012.Our department has a strength of 708 students guided by
a team of devoted and diligent staff members and they work hard to bring out competent,
disciplined and superlative quality Engineers to fulfill the expectation of the society. The
Department has well equipped laboratories such as e-CAD & VLSI, Simulation, DSP,
Microwave, Communication system, Microprocessor, Microcontroller, Linear and digital
IC, Electronic Devices & circuits and Electrical Labs. Advanced software’s like, MAT
lab, Cadence are the pride of the department. The Electronics and Communication
Association Organization (ECMRON) instituted in the department conducts regular
Technical activities like Quiz, Paper Presentation and weekly Seminars. Workshops are
conducted in the department to keep faculty and students updated with latest
developments in various technologies.
Academic Regulations 2009 for B. Tech (Regular)
(Effective for the students admitted into I year from the Academic Year 2009-2010 onwards)
1.
2.
3.
Award of B.Tech. Degree
A student will be declared eligible for the award of the B. Tech. Degree if he fulfils the following
academic regulations:
2.
. Pursued a course of study for not less than four academic years and not more
than eight academic years.
ii.
Register for 200 credits and secure 200 credits
Students, who fail to fulfil all the academic requirements for the award of the degree within eight
academic years from the year of their admission, shall forfeit their seat in B.Tech course.
Courses of study
The following courses of study are offered at present for specialization for the B. Tech. Course:
Branch Code Branch
I
Aeronautical Engineering.
II
Automobile Engineering.
III
Bio-Medical Engineering.
IV
Biotechnology.
V
Chemical Engineering.
VI
Civil Engineering.
VII
Computer Science and Engineering.
VIII
Electrical and Electronics Engineering.
IX
Electronics and Communication Engineering.
X
Electronics and Computer Engineering.
XI
Electronics and Instrumentation Engineering.
XII
Electronics and Telematics Engineering.
XIII
Information Technology.
XIV
Instrumentation and Control Engineering.
XV
Mechanical Engineering (Mechatronics).
XVI
Mechanical Engineering (Production).
XVII
Mechanical Engineering.
XVIII
Metallurgy and Material Technology.
and any other course as approved by the authorities of the University from time to time.
4.
Credits
I Year
Theory
Practical
Drawing
Mini Project
Comprehensive
Viva Voce
Seminar
Project
5.
Periods /
Week
03
02
03
02T/03D
Credits
---
---
Semester
Periods /
Credits
Week
03
03
--03
02
03
02
06
04
-02
-02
---
---
6
15
06
04
04
04
02
10
Distribution and Weightage of Marks
i.
The performance of a student in each semester / I year shall be evaluated subject –wise
with a maximum of 100 marks for theory and 75 marks for practical subject. In addition,
Industry oriented mini-project, seminar and project work shall be evaluated for 50, 50 and
200 marks respectively.
ii.
For theory subjects the distribution shall be 25 marks for Internal Evaluation and 75 marks
for the End-Examination.
iii.
For theory subjects, during the semester there shall be 2 mid term examinations. Each
mid term examination consists of one objective paper, one subjective paper and one
assignment. The objective paper is for 10 marks and subjective paper is for 10 marks,
with a duration of 1 hour 20 minutes (20 minutes for objective and 60 minutes for
subjective paper). Objective paper is set for 20 bits of – multiple choice questions, fill-in
the blanks, matching type questions – for the 10 marks.
Subjective paper of each semester shall contain 4 full questions (one from each unit) of
which, the student has to answer 2 questions, each carrying 5 marks.
First mid term examination shall be conducted for 1-4 units of syllabus and second mid
term examination shall be conducted for 5-8 units. 5 marks are allocated for Assignments
(as specified by the concerned subject teacher) – first Assignment should be submitted
before the conduct of the first mid, and the second Assignment should be submitted
before the conduct of the second mid. The total marks secured by the student in each
mid term examination are evaluated for 25 marks, and the better of the two mid term
examinations shall be taken as the final marks secured by each candidate.
However, for first year, there shall be 3 mid term examinations (each for 25 marks),
along with 3 assignments in a similar pattern as above [1st mid shall be from 1-2 units,
2nd mid from 3-5 units and 3rd mid shall be from 6-8 units], and the average marks of the
best two examinations secured (each evaluated for a total of 25 marks) in each subject
shall be considered as final marks for the internals / sessionals.
iv.
For practical subjects there shall be a continuous evaluation during the semester for 25 sessional
marks and 50 end examination marks. Out of the 25 marks for internal, day-to-day work in the
laboratory shall be evaluated for 15 marks and internal examination for practical shall be evaluated
for 10 marks conducted by the concerned laboratory teacher. The end examination shall be
conducted with external examiner and laboratory teacher. The external examiner shall be
appointed from the cluster of colleges as decided by the University examination branch.
For the subject having design and / or drawing, (such as Engineering Graphics, Engineering
Drawing, Machine Drawing) and estimation, the distribution shall be 25 marks for internal
evaluation (15 marks for day-to-day work and 10 marks for internal tests) and 75 marks for end
examination. There shall be two internal tests in a Semester and the better of the two shall be
considered for the award of marks for internal tests. However in the I year class, there shall be
three tests and the average of best two will be taken into consideration.
There shall be an industry-oriented mini-Project, in collaboration with an industry of their
specialization, to be taken up during the vacation after III year II Semester examination. However,
the mini project and its report shall be evaluated with the project work in IV year II Semester. The
industry oriented mini project shall be submitted in report form and should be presented before the
committee, which shall be evaluated for 50 marks. The committee consists of an external examiner,
head of the department, the supervisor of mini project and a senior faculty member of the
department. There shall be no internal marks for industry oriented mini project.
There shall be a seminar presentation in IV year II Semester. For the seminar, the student shall
collect the information on a specialized topic and prepare a technical report, showing his
understanding over the topic, and submit to the department, which shall be evaluated by the
Departmental committee consisting of Head of the department, seminar supervisor and a senior
faculty member. The seminar report shall be evaluated for 50 marks. There shall be no external
examination for seminar.
v.
vi.
vii.
viii.
There shall be a Comprehensive Viva-Voce in IV year II semester. The Comprehensive
Viva-Voce will be conducted by a Committee consisting of (i) Head of the Department (ii) two
Senior Faculty members of the Department. The Comprehensive Viva-Voce is aimed to assess the
students’ understanding in various subjects he / she studied during the B.Tech course of study. The
Comprehensive Viva-Voce is evaluated for 100 marks by the Committee. There are no internal
marks for the Comprehensive viva-voce.
ix.
Out of a total of 200 marks for the project work, 50 marks shall be for Internal Evaluation and 150
marks for the End Semester Examination. The End Semester Examination (viva-voce) shall be
conducted by the same committee appointed for industry oriented mini project. In addition the
project supervisor shall also be included in the committee. The topics for industry oriented mini
project, seminar and project work shall be different from each other. The evaluation of project work
shall be conducted at the end of the IV year. The Internal Evaluation shall be on the basis of two
seminars given by each student on the topic of his project.
ix.
Laboratory marks and the sessional marks awarded by the College are not final. They are
subject to scrutiny and scaling by the University wherever necessary. In such cases, the
sessional and laboratory marks awarded by the College will be referred to a Committee. The
Committee will arrive at a scaling factor and the marks will be scaled as per the scaling factor.
The recommendations of the Committee are final and binding. The laboratory records and
internal test papers shall be preserved in the respective institutions as per the University norms
and shall be produced to the Committees of the University as and when the same is asked for.
6.
Attendance Requirements:
i.
A student shall be eligible to appear for University examinations if he acquires a minimum
of 75% of attendance in aggregate of all the subjects.
ii.
Shortage of Attendance below 65% in aggregate shall in NO case be condoned .
iii.
Condonation of shortage of attendance in aggregate up to 10% (65% and above and
below 75%) in each semester or I year may be granted by the College Academic
Committee.
iv.
A student will not be promoted to the next semester unless he satisfies the attendance
requirement of the present semester / I year, as applicable. They may seek re-admission
for that semester / I year when offered next.
v.
Students whose shortage of attendance is not condoned in any semester / I year are not
eligible to take their end examination of that class and their registration shall stand
cancelled.
vi.
A stipulated fee shall be payable towards condonation of shortage of attendance.
7.
Minimum Academic Requirements:
The following academic requirements have to be satisfied in addition to the attendance
requirements mentioned in item no.6
i.
A student shall be deemed to have satisfied the minimum academic requirements and
earned the credits allotted to each theory or practical design or drawing subject or project
if he secures not less than 35% of marks in the end examination and a minimum of 40% of
marks in the sum total of the internal evaluation and end examination taken together.
ii.
A student shall be promoted from II to III year only if he fulfils the academic requirement of
37credits from one regular and one supplementary examinations of I year, and one
regular examination of II year I semester irrespective of whether the candidate takes the
examination or not.
iii.
A student shall be promoted from third year to fourth year only if he fulfils the academic
requirements of total 62 credits from the following examinations, whether the candidate
takes the examinations or not.
a. Two regular and two supplementary examinations of I year.
b. Two regular and one supplementary examinations of II year I semester.
c. One regular and one supplementary examinations of II year II semester.
d. One regular examination of III year I semester.
iv.
A student shall register and put up minimum attendance in all 200 credits and earn the 200
credits. Marks obtained in all 200 credits shall be considered for the calculation of
percentage of marks.
v.
Students who fail to earn 200 credits as indicated in the course structure within eight
academic years from the year of their admission shall forfeit their seat in B.Tech course
and their admission shall stand cancelled.
i.
The entire course of study is of four academic years. The first year shall be on yearly
pattern and the second, third and fourth years on semester pattern.
ii.
A student eligible to appear for the end examination in a subject, but absent at it or
has failed in the end examination may appear for that subject at the supplementary
examination.
iii.
When a student is detained due to lack of credits / shortage of attendance he may be
re-admitted when the semester / year is offered after fulfilment of academic
regulations, whereas the academic regulations hold good with the regulations he was
first admitted.
9.
Award of Class:
After a student has satisfied the requirements prescribed for the completion of the program
and is eligible for the award of B. Tech. Degree he shall be placed in one of the following four
classes:
Class Awarded
% of marks to be secured
First Class with Distinction
70% and above
From the aggregate
First Class
Below 70% but not less than 60%
marks secured for the
Second Class
Below 60% but not less than 50%
best 200 Credits.
Pass Class
Below 50% but not less than 40%
The marks in internal evaluation and end examination shall be shown separately in the marks
memorandum)
10.
Minimum Instruction Days:
The minimum instruction days for each semester / I year shall be 90/180 clear instruction
days.
There shall be no branch transfers after the completion of admission process.
There shall be no place transfer within the Constituent Colleges and Units of Jawaharlal Nehru
Technological University Hyderabad.
13.
General:
i. Where the words “he”, “him”, “his”, occur in the regulations, they include “she”, “her”, “hers”.
ii. The academic regulation should be read as a whole for the purpose of any interpretation.
iii. In the case of any doubt or ambiguity in the interpretation of the above rules, the decision of the
Vice-Chancellor is final.
11.
12.
The University may change or amend the academic regulations or syllabi at any time and the
changes or amendments made shall be applicable to all the students with effect from the dates
notified by the University
Academic Regulations for B. Tech. (Lateral Entry Scheme)
(Effective for the students getting admitted into II year from the Academic Year 2009-2010 and
onwards)
1.
The Students have to acquire 150 credits from II to IV year of B.Tech. Program (Regular) for
the award of the degree.
Register for 150 credits and secure 150 credits.
2.
Students, who fail to fulfil the requirement for the award of the degree in 6 consecutive
academic years from the year of admission, shall forfeit their seat.
3.
The same attendance regulations are to be adopted as that of B. Tech. (Regular).
4.
Promotion Rule:
A student shall be promoted from third year to fourth year only if he fulfils the
academic requirements of 37 credits from the examinations.
a. Two regular and one supplementary examinations of II year I semester. b. One
regular and one supplementary examinations of II year II semester. c. One regular
examination of III year I semester.
5.
Award of Class:
After a student has satisfied the requirements prescribed for the completion of the
program and is eligible for the award of B. Tech. Degree he shall be placed in one of
the following four classes:
First Class with Distinction
70% and above
From the aggregate marks
First Class
Below 70% but not less than 60%
secured for 150 Credits.
Second Class
Below 60% but not less than 50%
(i.e. II year to IV year)
Pass Class
Below 50% but not less than 40%
(The marks in internal evaluation and end examination shall be shown separately in
the marks memorandum)
6.
All other regulations as applicable for B. Tech. Four-year degree course (Regular) will
hold good for B. Tech. (Lateral Entry Scheme)
1. (a)
(b)
MALPRACTICES RULES
Nature of Malpractices/Improper
Punishment
conduct
If the candidate:
Possesses or keeps accessible in
Expulsion from the examination hall and
examination hall, any paper, note book,
cancellation of the performance in that subject
programmable calculators, Cell phones, only.
pager, palm computers or any other
form of material concerned with or
related to the subject of the examination
(theory or practical) in which he is
appearing but has not made use of
(material shall include any marks on the
body of the candidate which can be
used as an aid in the subject of the
examination)
Gives assistance or guidance or
Expulsion from the examination hall and
receives it from any other candidate
cancellation of the performance in that subject
orally or by any other body language
only of all the candidates involved.
In case of
2.
methods or communicates through cell
phones with any candidate or persons
in or outside the exam hall in respect of
any matter.
Has copied in the examination hall from
any paper, book, programmable
calculators, palm computers or any
other form of material relevant to the
subject of the examination (theory or
practical) in which the candidate is
appearing.
3.
Impersonates any other candidate in
connection with the examination.
4.
Smuggles in the Answer book or
additional sheet or takes out or
arranges to send out the question paper
during the examination or answer book
or additional sheet, during or after the
examination.
5.
6.
an outsider, he will be handed over to the
police and a case is registered against him.
Expulsion from the examination hall and
cancellation of the performance in that subject
and all other subjects the candidate has
already
appeared
including
practical
examinations and project work and shall not be
permitted to appear for the remaining
examinations of the subjects of that
Semester/year.
The Hall Ticket of the candidate is to be
cancelled and sent to the University.
The candidate who has impersonated shall be
expelled from examination hall. The candidate
is also debarred and forfeits the seat. The
performance of the original candidate who has
been impersonated, shall be cancelled in all
the subjects of the examination (including
practicals and project work) already appeared
and shall not be allowed to appear for
examinations of the remaining subjects of that
semester/year. The candidate is also debarred
for two consecutive semesters from class work
and all
University examinations.
The
continuation of the course by the candidate is
subject to the academic regulations in
connection with forfeiture of seat. If the
imposter is an outsider, he will be handed over
to the police and a case is registered against
him.
Expulsion from the examination hall and
cancellation of performance in that subject and
all the other subjects the candidate has already
appeared including practical examinations and
project work and shall not be permitted for the
remaining examinations of the subjects of that
semester/year. The candidate is also debarred
for two consecutive semesters from class work
and all
University examinations.
The
continuation of the course by the candidate
is
subject to the academic regulations in
connection with forfeiture of
seat.
Cancellation of the performance in that
or subject.
Uses objectionable, abusive
offensive language in the answer
paper
or in letters to the examiners or writes
to the examiner requesting him to
award pass marks.
Refuses to obey the orders of the
Chief
Superintendent/Assista
nt
–
Superintendent / any officer on duty
or
misbehaves or creates disturbance of
any kind in and around the
examination
hall or organizes a walk out or
In case of students of the college, they shall
be
expelled from examination halls and
cancellation of their performance in that
subject
and all other subjects the candidate(s) has
(have) already appeared and shall not
be
permitted to appear for the remaining
instigates others to walk out, or
threatens the officer-in charge or any
person on duty in or outside the
examination hall of any injury to his
7.
8.
9.
examinations of the subjects of that
semester/year. The candidates also are
debarred and forfeit their seats. In case of
outsiders, they will be handed over to the
police and a police case is registered
person or to any of his relations
against
whether by words, either spoken or them.
written or by signs or by visible
representation, assaults the officer-incharge, or any person on duty in or
outside the examination hall or any of
his relations, or indulges in any other
act of misconduct or mischief which
result in damage to or destruction of
property in the examination hall or
any
part of the College campus or
engages
in any other act which in the opinion
of
the officer on duty amounts to use of
unfair means or misconduct or has
the
tendency to disrupt the orderly
conduct
of the examination.
Leaves the exam hall taking away Expulsion from the examination hall and
cancellation of performance in that subject
answer script or intentionally tears of and
all the other subjects the candidate has
the script or any part thereof inside or already
appeared including practical examinations
outside the examination hall.
and
project work and shall not be permitted for
the
remaining examinations of the subjects of
that
semester/year. The candidate is also
debarred
for two consecutive semesters from class
work
and all
University examinations. The
continuation of the course by the candidate
is
subject to the academic regulations in
connection with forfeiture of
seat.
Possess any lethal weapon or firearm
in
Expulsion from the examination hall and
cancellation of the performance in that
the examination hall.
subject
and all other subjects the candidate has
already appeared including
practical
examinations and project work and shall not
be
permitted for the remaining examinations of
the
subjects of that semester/year. The
candidate
is also debarred and forfeits the seat.
If student of the college, who is not a Student of the colleges expulsion from the
candidate for the particular
examination
examination hall and cancellation of the
or any person not connected with the performance in that subject and all other
subjects the candidate has already
college indulges in any malpractice or appeared
improper conduct mentioned in
clause 6
including practical examinations and project
to 8.
work and shall not be permitted for the
remaining examinations of the subjects of
that
semester/year. The candidate is also
debarred
and forfeits the seat.
10.
Comes in a drunken condition to the
examination hall.
11.
Copying detected on the basis of
internal evidence, such as, during
valuation or during special scrutiny.
Person(s) who do not belong to the
College will be handed over to police and, a
police case will be registered against them.
Expulsion from the examination hall and
cancellation of the performance in that
subject
and all other subjects the candidate has
pr
a
ct
ic
already
appeared including al
examinations and project work and shall not
be
permitted for the remaining examinations of
the
subjects of that semester/year.
Cancellation of the performance in that
subject
and all other subjects the candidate has
appeared including practical examinations
and
semes
ter/ye
project
work
of that
ar
examinations.
12.
If any malpractice is detected which is
not covered in the above clauses 1 to
11 shall be reported to the University
for
further action to award suitable
punishment.
Malpractices identified by squad or special invigilators
1.
2.
Punishments to the candidates as per the above guidelines.
Punishment for institutions : (if the squad reports that the college is also involved in
encouraging malpractices)
(i)
A show cause notice shall be issued to the college.
(ii)
Impose a suitable fine on the college.
(iii)
Shifting the examination centre from the college to another college for a specific
period of not less than one year.
Academic Calendar by JNTU
DEPARTMENT EVENT PLANNER A.Y 2013-2014
A.Y 2013-2014 I SEM
S.No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
DATE AND MONTH
05/06/13 to 22/06/13
24/06/13 to 06/07/13
01/07/13
17/07/13 to 20/07/13
01/08/13 to 07/08/13
EVENT NAME
Mini Project Work for III Year II semester
CRT Program for III Year II semester
Commencement Of B.Tech Class Work
1st Workshop
IETE Student chapter Inauguration & 1st Staff Development
Program
19/08/13 to 24/08/13
1st Guest Lecture for II, III & IV Years
1st MID Exams for II & IV Years
26/08/13 to 28/08/13
1st MID Exams for III Year
29/08/13 to 31/08/13
04/09/13 to 07/09/13
Adjunct Course in Advanced Technology for III & IV Years
05/09/13
Teachers Day
15/09/13
Engineers Day
16/09/13 to 18/09/13
2nd Workshop
01/10/13 to 06/10/13
Sports Week
07/10/13 to 11/10/13
2nd Guest Lecture for II, III & IV Years
2nd MID Exams for II & IV Years
28/10/13 to 30/10/13
2nd MID Exams for III Year
31/10/13 to 02/11/13
31/10/13 to 08/11/13
Preparation & practical Exams for II & IV Years
04/11/13 to 09/11/13
Preparation & practical Exams for III Year
11/11/13 to 23/11/13
End Semester Examinations
1st week of December 2013
2nd Staff Development Program
A.Y 2013-2014 II SEM
09/12/13
Commencement Of B.Tech Class Work
03/12/13 to 15/12/13
Industrial Visit
06/01/14 to 10/01/14
3rd Workshop
20/01/14
Association Hour Program
01/02/14 to 06/02/14
3rd Guest Lecture for II, III, IV Years
1st MID Exams for II & IV Years
10/02/14 to 12/02/14
1st MID Exams for III Year
13/02/14 to 15/02/14
03/03/14 to 08/03/14
Adjunct Course in Advanced Technology for III & IV Years
17/03/14 to 21/03/14
4th Workshop
22/03/14 to 05/04/14
Avazya 2K14 & EXUBERANCE2K14
04/04/14 to 06/04/14
4th Guest Lecture for II & IV Years
07/04/14 to 08/04/14
4th Guest Lecture for III Years
2nd MID Exams for II & IV Years
07/04/14 to 09/04/14
2nd MID Exams for III Year
10/04/14 to 19/04/14
14/04/14 to 19/04/14
Preparation & practical Exams for II & IV Years
10/04/14 to 19/04/14
Preparation & practical Exams for III Year
21/04/14 to 03/05/14
End Semester Examinations
LIST OF SUBJECTS & LABS
S.No SUBJECT/LAB
CODE
CREDITS
1
Electronic Circuit Analysis
54020
4
2
Principles Of Electrical &
Electronics Engg
54019
3
3
Pulse And Digital Circuits
54021
4
4
Switching Theory & Logic Design
54010
4
5
Electromagnetic Theory &
Transmission Lines
54011
4
6
Electrical Engineering Lab
54606
2
7
Electronic Circuit Analysis Lab
54607
2
8
Pulse And Digital Circuits Lab
54608
2
SUBJECT: ELECTRONIC CIRCUIT
ANALYSIS
S.NO
CONTENT
(1)
-
Objectives and Relevance
(2)
-
Scope
(3)
-
Prerequisites
(4)
-
Syllabus
1.
JNTU
2.
GATE
3.
IES
(5)
-
Suggested Books
(6)
-
Websites
(7)
-
Expert Details
(8)
-
Journals
(9)
-
Subject (lesson) Plan
(10)
-
OOPS
(11)
-
Question Bank
1.
JNTU
2.
GATE
3.
IES
(12)
-
Assignment Question sets on each unit
(13)
-
List of topics for student’s seminars
(1)
OBJECTIVES AND RELEVANCE
Electronic Circuit Analysis is intended for undergraduate Electronics and communication
Engineering students. The purpose of this course is to provide a foundation for analyzing and
designing analog electronic circuits.
This course is designed to give an introductory idea of the fundamental aspects of single
stage and multistage amplifiers. This learning is enhanced by going through the hand analysis and
calculations. Design is the heart of engineering. Good design evolves out of considerable
experience with analysis. In this course various characteristics and properties of circuits are
planned out as we go through the analysis. The objective is to develop an intuition that can be
applied to the design process. Meeting an explicit set of design criteria is the first step in the
design process.
This course lays the foundation of Electronics and Communication Engineering. Every
topic here is therefore included as part of the syllabus for most of the competitive exams like the
IES, GATE etc.
(2)
SCOPE
The scope of this subject is to provide an insight into analysis and design of different
amplifiers like single stage and multistage amplifiers, feedback and non-feedback amplifiers,
small signal and large signal amplifiers, oscillators and tuned amplifiers. Amplifiers are the basic
blocks of communication system used for design of RF, IF and AF amplifiers.
(3)
PREREQUISITES
The prerequisites for understanding this course include knowledge of basic
semiconductor physics, concepts of BJT, FET transistors and exact h-parameter analysis of
different configurations of BJT, FET amplifiers.
(4.1)
SYLLABUS - JNTU
UNIT-I
OBJECTIVE
 Apply small signal h-parameter model for CE, CC and CB amplifiers.
 Describe signal h-parameter model for CE amplifier with emitter resistance.
 Apply small signal h-parameter model for Emitter follower.
 Understand and apply Millers theorem.
 Analyze single stage RC coupled BJT amplifier.
SYLLABUS
Single Stage Amplifiers Classification of Amplifiers, Distortion in amplifiers, Analysis of CE,
CC and CB configurations with simplified Hybrid Model, Analysis of CE amplifier with Emitter
resistance and Emitter follower, Miller’s Theorem and its dual, Design of single Stage RC
Coupled Amplifier using BJT.
UNIT - II
OBJECTIVE
 Analyze two stage RC coupled BJT amplifier.
 Analyze cascode amplifier.
 Characterize Darlington composite amplifier.
 Describe RC coupled amplifier.
 Describe transformer coupled amplifier.
 Describe direct coupled amplifier.
SYLLABUS
Multi Stage Amplifiers Analysis of Cascaded RC Coupled BJT amplifiers, Cascode Amplifier,
Darlington Pair, Different Coupling Schemes used in Amplifiers, RC Coupled Amplifier,
Transformer Coupled Amplifier, Direst Coupled Amplifier.
UNIT -III
OBJECTIVE
 Understand the concepts of Logarithms and Decibles.
 Characterize low, mid and high frequency responses.
 Bring out the effect of coupling and bypass capacitors.
 Understand Hybrid pi (П) model for BJT.
 Analyze CE short circuit current gain.
 Analyze emitter follower at high frequencies.
SYLLABUS
BJT Amplifiers- Frequency Response Logarithms, Decibles, General frequency considerations,
Frequency response of of BJT Amplifier, Analysis at Low and High frequencies, Effect of
coupling and bypass capacitors, The Hybrid pi (П), Common Emitter Transistor Model, CE Short
Circuit Current Gain, Current Gain with Resistive Load, Single Stage CE Transistor Amplifier
Response, Gain Bandwidth Product, Emitter follower at higher frequencies.
UNIT - IV
OBJECTIVE
 Understand small signal model for MOSFETS.
 Analyze CS amplifier with resistive load, diode connected load and current source load.
 Analyze Source follower and CG stage.
 Understand cascode and folded cascode amplifiers.
SYLLABUS
MOS Amplifiers Basic Concepts, MOS Small signal model, Common Source amplifier with
Resistive load, Diode connected Load and Current Source Load, Source follower, Common Gate
stage, Cascode and Folded Cascode Amplifier and their Frequency response.
UNIT - V
OBJECTIVE
 Describe block diagram of feedback amplifiers.
 Characterize negative feedback amplifiers.
 Understand the effect of feedback on amplifier characteristics.
 Describe the various topologies of feedback amplifiers.
SYLLABUS
Feedback Amplifiers Concepts of Feedback, Classification of Feedback Amplifiers, General
characteristics of Negative Feedback Amplifiers, Effect of Feedback on Amplifier Characteristics,
Voltage Series, Voltage Shunt, Current Series and Current Shunt Feedback Configurations,
Illustrative Problems.
UNIT - VI
OBJECTIVE
 Explain Barkhausen criterion.
 Explain different types of oscillators.
 Understand the working of RC phase shift oscillators.
 Understand the working of LC oscillators.
 Describe stability of oscillators.
SYLLABUS
Oscillators Classification of Oscillators, Conditions for Oscillations, RC Phase Shift Oscillator,
Generalized analysis of LC Oscillators, Hartley and Colpitts Oscillators, Wein Bridge and Crystal
Oscillators, Stability of Oscillators.
UNIT - VII
OBJECTIVE
 Get the knowledge about different types of large signal amplifiers.
 Analyze series fed and transformer coupled Class A power amplifier.
 Find the efficiency of Class B amplifiers.
 Understand the working of Class B Push-Pull and Complementary Symmetry amplifier.
 Describe second harmonic distortion.
 Understand thermal stability and heat sinks.
SYLLABUS
Large Signal Amplifiers Classification, Class A Large Signal Amplifiers, Transformer Coupled
Class A Audio Power Amplifier, Efficiency of Class A Amplifier, Class B Amplifier, Efficiency
of Class B Amplifier, Class B Push-Pull Amplifier, Complementary Symmetry Class B Push-Pull
Amplifier, Distortion in Power Amplifiers, Thermal Stability and Heat Sinks.
UNIT - VIII
OBJECTIVE
 Explain loaded and un-loaded Q.
 Analyze single and double tuned amplifiers.
 Understand the effect of cascading single and double tuned amplifiers on bandwidth.
 Explain stability of tuned amplifiers.
SYLLABUS
Tuned Amplifiers Introduction, Q-Factor, Small Signal Tuned Amplifiers, Effect of Cascoding
Single Tuned Amplifiers on Bandwidth, Effect of Cascoding Double Tuned Amplifiers on
Bandwidth, Stagger Tuned Amplifiers, Stability of Tuned Amplifiers.
(4.2)
SYLLABUS - GATE
UNIT I
Small signal Equivalent circuits of BJTs, Single stage amplifiers.
UNIT II
Multi stage amplifiers.
UNIT III
Frequency response of amplifiers.
UNIT IV
Small signal Equivalent circuits of MOSFET’s.
UNIT V
Feedback amplifiers.
UNIT VI
Sinusoidal oscillators, criterion for oscillation.
UNIT VII
Power amplifiers.
UNIT VIII
Not applicable
(4.3)
SYLLABUS - IES
UNIT I
Small signal analysis.
UNIT II
Not Applicable
UNIT III
Frequency response.
UNIT IV
Not Applicable
UNIT V
Feedback amplifiers.
UNIT VI
Oscillators
UNIT VII
Power amplifiers.
UNIT VIII
Tuned amplifiers.
(5)
SUGGESTED BOOKS
TEXTBOOKS :
1. Integrated Electronics – Jacob Millman and Christos C Halkies, 1991 Ed. 2008, TMH.
2. Electronic Devices and Circuits – S. Salivahanan, N. Suresh Kumar, A Vallavaraj, 2.Ed.,
2009, TMH
3. Design of Analog CMOS Integrated Cicuits – Behzad Razavi, 2008, TMH.
REFERENCES :
1.
2.
3.
4.
5.
(6)
Electronic Devices and Circuit Theory – Robet L. Boylestad, louis Nashelsky, 9.Ed., 2008
PE.
Introductory Electronic Devices and Circuits – Robert T. Paymer, 7.Ed., 2009, PEI.
Electronic Circuit Analysis – K. Lal Kishore, 2004, BSP.
Electronic Devices and Circuits, david A. Bell, 5.ed., Oxford University Press.
Microelectronics Circuits – Sedra and smith – 5.Ed., 2009, Oxford University.
WEBSITES
1.
2.
3.
4.
5.
6.
7.
8.
http://www.ni.com/multisim/what-is/
http://www.mhhe.com/engcs/electrical/neamen01/
http://www.unix.eng.ua.edu/~huddl/mystuff/ECE333/ISM--Electronic%20Circuit%20Analysis%20and%20Design.pdf
http://www.stanford.edu/class/ee122/Handouts/EE113_Course_Notes_Rev0.pdf
http://www.ee.hacettepe.edu.tr/~solen/Matlab/MatLab/Matlab%20%20Electronics%20and%20Circuit%20Analysis%20using%20Matlab.pdf
http://www.zen22142.zen.co.uk/Theory/tr_model.htm
http://en.wikipedia.org/wiki/Negative_feedback_amplifier
http://www.learnabout-electronics.org/Amplifiers/amplifiers10.php
9. http://www.electronics-tutorials.ws/oscillator/rc_oscillator.html
10. http://www.learnabout-electronics.org/Oscillators/osc10.php
(7)
EXPERT DETAILS
The Expert Details which have been mentioned below are only a few of the
eminent ones known Internationally, Nationally and Locally. T here are a few
others known as well.
INTERNATIONAL
1. Prof. Donald Neamen
Professor and Associate Chairman for the Department of Electrical and Computer
Engineering
The University of New Mexico.
e-mail: [email protected]
2.
Prof. Anantha P. Chandrakasan
Professor of Electrical Engineering and Computer Science
Massachusetts Institute of Technology.
e-mail: [email protected]
NATIONAL
1. Prof. Anindya Sundar Dhar
Professor Department of Electronics & Electrical Communication Engineering
IIT Kharagpur.
e-mail: [email protected]
2.
Prof. Indrajit Chakrabarti
Professor Department of Electronics & Electrical Communication Engineering
IIT Kharagpur.
e-mail: [email protected]
REGIONAL
1. Dr. Krishna Prasad K S R
Professor Department of Electronics & Communication Engineering
NIT Warangal.
e-mail: [email protected]
(8)
JOURNALS
INTERNATIONAL
1.
2.
3.
4.
5.
The Journal of Non-Linear Analysis and Application
International Journal of Electronics (Taylor & Francis Group)
International Journal of Modeling and Simulation (ACTA Press)
IEEE Transactions on Circuits and systems
IEEE Transactions on Electronic Devices.
NATIONAL
1.
2.
3.
4.
5.
(9)
Journal of the Institute of Engineers
Journal of the Indian Institute of Science
IETE Journal of Education
IETE Journal of Research
IETE Technical Review
SUBJECT (LESSON) PLAN
S.NO
Topic (JNTU
Syllabus)
Sub-Topic
No. of
Lectures
Required
Suggested
Books
UNIT - I
1
Classification of
Amplifiers
Different categories of
amplifiers
L1
T2, R2
2
Distortion in
Amplifiers
Amplitude, Frequency &
Phase distortions
L2
T2, R2
3
Analysis of CE
configuration with
simplified Hybrid
Model
h-parameter analysis of CE
amplifier with problems
L3, L4,
L5
T1, T2,R1
4
Analysis of CB
configurations with
simplified Hybrid
Model
h-parameter analysis of CB
amplifier with problems
L6
T1, T2,R1
5
Analysis of CC
configurations with
simplified Hybrid
Model
h-parameter analysis of CB
amplifier with problems
L7
T1, T2,R1
6
Analysis of CE
amplifier with
Emitter resistance
h-parameter analysis of CE
amplifier with Emitter
resistance
L8
T1, T2,R1
7
Analysis of Emitter
Follower
h-parameter analysis of
Emitter Follower
L9
T1, T2,R1
8
Miller’s Theorem
and its dual
Application of Miller’s
Theorem and its dual
L10, L11
T1, T2,R1
9
Design of single
Stage RC Coupled
Amplifier using
BJT
Design of single Stage RC
Coupled Amplifier using BJT
L12,L13
T1, T2,R1
L14, L15,
L16
T2, R2
UNIT – II
10
Analysis of
Cascaded RC
Coupled BJT
amplifiers
Need for cascading, Two
stage, n-stage cascaded
amplifier analysis with
problems
11
Cascode Amplifier
Analysis of Cascode
Amplifier
L17
T2, R2
12
Darlington Pair
Darlington Composite
Emitter follower
L18
T2, R2
Remar
ks
13
Different coupling
schemes
RC, Transformer, Direct
coupled amplifiers
L19
T2, R2
14
RC Coupled
Amplifier
Circuit & operation of RC
Coupled Amplifier
L20
T2, R4
15
Transformer
Coupled Amplifier
Circuit & operation of
Transformer Coupled
Amplifier
L21
T2, R4
16
Direct Coupled
Amplifier
Circuit & operation of Direct
Coupled Amplifier
L22
T2, R4
UNIT – III
17
Logarithms,
Decibels, General
frequency
considerations
Logarithms, Decibels,
frequency analysis
definitions
L23
T1, T2,R4
18
Frequency response
of BJT Amplifier
Low, Mid, High frequency
considerations
L24
T1, T2,R4
19
Analysis at Low
and High
frequencies
Low and high frequency
analysis
L25
T1, T2,R4
20
Effect of coupling
and bypass
capacitors
Effect of Ce, Cc, Co
capacitors
L26
T1, T2,R4
21
The Hybrid pi (П)
Transconductance model
L27, L28
T1, T2,R4
22
CE Short Circuit
Current Gain
Derivation for CE Short
Circuit Current Gain
L29
T1, T2,R4
23
Current Gain with
Resistive Load
Derivation for Current Gain
with Resistive Load
L30
T1, T2,R4
24
Gain Bandwidth
Product
Gain Bandwidth Product
L31
T1, T2,R4
25
Emitter Follower at
high frequencies
Analysis of Emitter Follower
at high frequencies
L32
T1, T2,R4
UNIT – IV
26
Basic Concepts
Non-linear system analysis
L33
T3, T2
27
MOS Small signal
model
gm, gd, gmb equations
L34
T3, T2
28
Common source
amplifier with
Resistive load,
Diode connected
Gain equations for CS
amplifier with Resistive load,
Diode connected Load
L35
T3, T2
Load
29
Current Source
Load, Source
follower
Gain equations for Current
Source Load, Source
follower
L36
T3, T2
30
Common Gate
Stage, Cascode
Amplifier
Gain equations for CG Stage,
Cascode Amplifier
L37
T3, T2
31
Folded Cascode
Amplifier
Analysis of Folded Cascode
Amplifier
L38
T3, T2
UNIT – V
32
Concepts of
Feedback,
Block diagram of feedback
amplifier, Positive &
Negative feedbacks
L39, L40
T2, R1, R4
33
Classification of
Feedback
Amplifiers
Voltage & Current series,
Voltage & Current shunt
feedback amplifiers
L41
T2, R1, R4
34
General
characteristics of
Negative Feedback
Amplifiers, Effect
of Feedback on
Amplifier
Characteristics
Gain , Bandwidth, Noise,
Distortion, Input & output
resistances
L42
T2, R1, R4
35
Voltage Series &
Current Series
Feedback
Configuration
Effect of feedback on input
and output resistances
L43
T2, R1, R4
36
Voltage Shunt &
Current Shunt
Feedback
Configuration
Effect of feedback on input
and output resistances
L44
T2, R1, R4
37
Illustrative
Problems
Problems
L45, L46
T2, R1, R4
L47
T1, T2, R1,
R4
L48, L49
T1, T2, R1,
R4
L50
T1, T2, R1,
R4
UNIT – VI
38
Classification of
Oscillators,
Conditions for
Oscillations
Different oscillators,
Barkhausen criterion
39
RC Phase Shift
Oscillator
BJT,FET RC Phase shift
oscillators operation
40
Wein Bridge
BJT,FET Wein Bridge
oscillators operation
Oscillators
41
Generalized
analysis of LC
Oscillators
Operation of tank circuit
L51
T1, T2, R1,
R4
42
Hartley and Colpitts
Oscillators
L52
T1, T2, R1,
R4
43
Crystal Oscillators
L53
44
Stability of
Oscillators
Operation and
oscillation frequency
equation
Operation of crystal
oscillators
Frequency stability of
oscillators
T1, T2, R1,
R4
T1, T2, R1,
R4
L54
UNIT – VII
45
Classification of
Large Signal
Amplifiers
Class A, B, C & AB large
signal amplifiers
L55, L56
T1, T2,R2
46
Class A Large
Signal Amplifiers
Efficiency of Series Fed
Class A Large Signal
Amplifiers
L57
T1, T2,R2
47
Transformer
Coupled Class A
Audio Power
Amplifier
Efficiency of Transformer
Coupled Class A Audio
Power Amplifier
L58, L59
T1, T2,R2
48
Distortion in Power
Amplifiers
Three point method second
harmonic distortion
L60
T1, T2,R2
49
Class B Push-Pull
Amplifier
Analysis of Class B PushPull Amplifier
L61
T1, T2,R2
50
Complementary
Symmetry Class B
Push-Pull Amplifier
Analysis of Complementary
Symmetry Class B Push-Pull
Amplifier
L62
T1, T2,R2
51
Thermal Stability
and Heat Sinks
Condition for Thermal
Stability and Heat Sinks
L63
T1, T2,R2
L64
T2, R4
L65, L66
T2, R4
L67
T2, R4
UNIT –VIII
52
Introduction, QFactor
Coil Losses, Loaded & UnLoaded Q
53
Small Signal Tuned
Amplifiers
Single & Double tuned
amplifiers
54
Effect of Cascoding
Single Tuned
Amplifiers on
Bandwidth
Bandwidth equation for
Single Tuned Amplifiers
55
Effect of Cascoding
Double Tuned
Amplifiers on
Bandwidth
Bandwidth equation for
Double Tuned Amplifiers
L68
T2, R4
56
Stagger Tuned
Amplifiers
Analysis of Stagger Tuned
Amplifiers
L69
T2, R4
57
Stability of Tuned
Amplifiers
Neutralization methods for
Stability of Tuned Amplifiers
L70
T2, R4
(10)
Lectu
re No.
OOPS
JNTUH Topic
Objective of each Topic
Learning Outcome
Practical
Inferences
Method of
Teaching
UNIT – 1 Single Stage Amplifiers
L1
Transistor – BJT,
FET
Review of Electronic
devices
Electrical
characteristics of
BJT,FET
Simple switch &
Amplifiers
M1
Classification of
Amplifiers,
Distortion in
Amplifiers
To study Classification
and Distortion in
amplifiers
Come to know
different types of
Amplifiers
Improve the
performance of
amplifiers
M1
To study simplified
Hybrid Model
Calculation of voltage
gain, current gain,
input impedance,
output impedance
Design of
Amplifiers
Calculation of voltage
gain, current gain,
input impedance,
output impedance
Used in
communication
M1
Circuit analysis
Replace the twoport represented
on the right to its
equivalent circuit
M1
L2
L3 L
4
L5
L6
L7
L8
L9
Analysis of CE,CC
and CB
Configurations with
simplified Hybrid
Model
Analysis of CE
Amplifier with
Emitter Resistance
To Study the impact of
RE in CE Amplifier
Emitter follower,
Miller’s Theorem and
its dual
To learn the Millers’
theorem
Design of Single
Stage RC Coupled
Amplifier using BJT
To learn the Single stage
Amplifier Analysis
Disadvantages of
single stage. Types of
inter stage coupling
and choice of
configuration
To understand the need
of multistage amplifiers
and to learn how to
analyze them.
Analysis of Cascaded
RC Coupled BJT
amplifiers
Learning to cascade
different transistor
configuration
Calculation of voltage
gain, current gain,
Used in low
input impedance,
frequencies
output impedance
UNIT – II Multistage Amplifiers
M1 & M5
M1
Need of multistage
amplifiers.
Used in
amplifying RF
communication
M4
Calculation of voltage
gain, current gain,
input impedance,
output impedance
Used in
amplifying RF
communication
M1 & M5
L10
Cascode Amplifier
Learning to cascade
different transistor
configuration
Operation of cascode
amplifier
Used in
Modulators,
differential OpAmp
L11
Darlington Pair
Learning to cascade
different transistor
configuration
Calculation of voltage
gain, current gain,
input impedance,
output impedance
A Darlington pair
is used to amplify
weak signal
L12
Different Coupling
Schemes used in
Amplifiers
To Study different types
of Coupling Amplifiers
What is coupling?
Importance of
coupling
multistage
amplifiers
L13
RC Coupled
Amplifier,
To Study different types
of Coupling Amplifiers
Knowledge about rc
coupled and
Transformer coupled
amplifiers
used to amplify
the low
frequencies of dc
signals
Basics of non linear
graphs and units of
frequency
Knowing the
calculation or how to
calculate the
frequency.
Frequency
response
measurement
Transformer Coupled
Amplifier and Direct
Coupled Amplifier
L14,L
15
Logarithms, Decibels
L16
Frequency response
of BJT Amplifier,
Analysis at Low and
High frequencies
M1 & M5
M4
M1
M1
M4
UNIT – III BJT Amplifiers Frequency Response
L17
Effect of coupling
and bypass capacitors
To study the frequency
response
To study effect of
capacitors in the
Amplifier
L18
The Hybrid 
Common Emitter
Transistor Model
To study Hybrid 
Model
L19
CE Short Circuit
Current Gain, Current
Gain with Resistive
Load
To study Short circuit
gain without and with
Resistive load
Single stage CE
To study frequency
response
L20
Transistor Amplifier
Response, GainBandwidth Product
Knowledge of the BJT
Amplifiers
Knowledge Effect of
Ce, Cc, Co capacitors
Calculation of voltage
gain, current gain,
input impedance,
output impedance
Used in low and
high frequencies
M4
Used in power
supplies to reduce
noise on the DC
Coupling
capacitors
M1
used to build
equations for
voltage gain,
current gain
M1
Calculation of voltage
gain, current gain,
input impedance,
output impedance
use as a current
buffer
M1
Calculation of voltage
gain, current gain,
input & output
impedance
Used in low
frequencies
M4
L21
Emitter follower at
higher frequencies
To study frequency
response at high
frequencies
Knowledge about the
emitter follower at
higher frequencies
Used in analysis
of frequency
response
M7
Unit – IV MOS Amplifiers
L23
MOSFET models
used by the circuit
designers and
circuit analysis
M1
Basic concepts, MOS
Small signal model
To study the
Characteristics of
Amplifiers
Common source
amplifier with
Resistive load
Study the analysis of CS
stage, I/P – O/P
characteristics, Small
signal model
Calculation of voltage
gain ,input resistance,
output resistance
Used in Audio
applications
L25
Diode connected
Load and Current
Source Load
To study the diode
connected NMOS &
PMOS devices & to find
Voltage gain
Calculation of voltage
gain ,input resistance,
output resistance
Used as a current
source load to an
NPN amplifier
stage.
M3
L26
Source follower
To study small signal
model and to find
Voltage gain
Calculation of voltage
gain ,input resistance,
output resistance
used as a voltage
buffer amplifier
M5
Calculation of voltage
gain ,input resistance,
output resistance
used in highfrequency
application
Calculation of voltage
gain ,input resistance,
output resistance
used in many
analog
applications
24
L27
Common Gate stage
To study small signal
model and to find
Voltage gain
L28
Cascode and folded
Cascode Amplifier
To derive the Voltage
gains
L29
Frequency response
Basic concepts of Poles
and Zeros in transfer
function of Voltage gain
and their impact on
Frequency response
Knowledge about
Small signal model
M1 & M4
M1
M1
M1
Knowledge about
frequency response
Used in measure
of the output
spectrum of a
system
Unit –V Feedback Amplifiers
L30
L31
L32
L33,L
34,L3
5
Concept of feedback
To study about feedback
amplifiers
Classification of
feedback amplifiers
Types of Feedback
amplifiers
What is feedback
amplifier? Concept &
Importance of it
Different types of
feedback Amplifiers
used in amplifiers
General characteristic
of negative feedback
amplifiers
Characteristics of
negative feedback
Knowing the gain of
the negative feedback
amplifier
Effect of feedback on
amplifier
characteristics
(Voltage Series,
Voltage Shunt,
Current Series and
Characteristics of
negative feedback
amplifiers
Calculation of input
and output resistance
Used in
Amplifiers
M4
For reducing the
Noise
M4
Used in Helping
to increase the
bandwidth,
decrease
distortion
M1 & M5
Used for analysis
of voltage gain,
bandwidth,
distortion
M1
Current Shunt)
Unit –VI Oscillators
L36 L37
Introduction to
oscillators, Condition
for oscillations – RC
phase shift oscillator
To study classification &
about oscillators
Knowledge on
oscillators.
Generation of AC
signal
M4
L38L39
Wien’s Bridge
Oscillators
Types of Oscillators
Knowledge of wien
bridge oscillators
Used to
generation of
M1
L40
General analysis of
LC oscillators,
Hartley oscillators,
Colpitts oscillators
To Study general form of
Oscillator and types
Knowledge and
analysis of oscillators
Used in
determining
oscillations.
M1 & M2
Frequency and
amplitude stability,
Crystal oscillators
To study about
frequency stability
Knowledge Frequency
and amplitude
stability, Crystal
oscillators
Used in checking
to the change in
frequency
L41
UNIT – VII Large Signal Amplifiers
L42,L
43
Classification, Class
A Large Signal
Amplifiers
Study of Large Signal
Amplifiers
L44L45
Transformer Coupled
Class A Audio Power
Amplifier, Efficiency
of Class A Amplifier
Study of Class A
Amplifier
L46L47
Class B Amplifier,
Efficiency of Class B
Amplifier, Class-B
Push-Pull Amplifier
Study of Class B
Amplifier
L48
Complementary
symmetry Class B
Push-Pull Amplifier,
Distortion in Power
Amplifiers, Thermal
Stability and Heat
Sinks.
L49
M1 & M5
Concept of power
amplifiers
Used in power
amplifiers
M1
Operation and analysis
of efficiency of the
amplifier
Used low power
linear amplifiers
Operation and analysis
of efficiency of the
amplifier
Used in radiofrequency
applications
Study of Class B
Amplifier
Operation and analysis
of efficiency of the
amplifier
Used in radiofrequency
applications
Study of Distortion,
Thermal stability and
Heat sinks
Knowledge of
different distortion in
power amplifiers and
their remedies
Used for reducing
noise in the
circuits
M1
M1 & M4
M4
UNIT:VIII Tuned Amplifiers
L50 L51
Introduction, QFactor
Introduction to Tuned
Amplifiers
Knowledge about
Tuned amplifier
L52 L 53
Small Signal Tuned
Amplifiers
Study of Small Signal
Tuned Amplifiers
Finding Resonance
and Quality factor
L54
Effect of Cascading
Single Tuned
Study of Bandwidth for
Single Tuned Amplifiers
Finding the bandwidth
of Single Tuned
used to amplify
signals in a
narrow frequency
band
used to amplify
signals in a
narrow frequency
band
M1
used to amplify
modulated RF
M1
M1
Amplifiers on
Bandwidth
L56
Stagger Tuned
Amplifiers
Study if stagger tuning
L57
Stability of Tuned
Amplifiers.
Study of Stability for
Tuned Amplifiers
Amplifiers
carrier and
Bandwidth
Knowing these
cascaded tuned
circuits are tuned to
different frequencies,
why.
Knowledge Stability
for Tuned Amplifiers
used to improve
the overall
frequency
response of tuned
Amplifiers
Used for stability
of the tuned
amplifier
(11.1) QUESTION BANK - JNTU
1.a)
For the CB amplifier circuit shown, compute R IN and ROUT if C1 is
i) Connected ii) Not connected
The h-parameters of the transistor in CE configuration are listed as: hie =
2.1KΩ, hfe = 81, hoe = 1.66 µMhos and hre is negligibly small.
3.
2.a)
b)
c)
Reason out the causes and results of Phase & Frequency distortions in transistor amplifiers.
Differentiate between direct and capacitive coupling of multiple stages of amplifiers.
With the help of a neat circuit diagram, describe the working of a cascode amplifier.
What are the merits and demerits of a cascade amplifier over a simple Common
Emitter amplifier?
3.a)
b)
c)
Derive the expressions for hybrid Π conductance, gce, and gbb’ of a transistor.
Explain how hybrid Π parameters, gm and gce vary with Ic, Vce and temperature.
Compute the overall lower cut-off frequency of an identical two stage cascade of
amplifiers with individual lower cut-off frequency given as 432 Hz.
4.a)
b)
Discuss the effect of different type of loads to a common source MOS amplifier.
Differentiate between cascode and folded cascode configurations.
If negative feedback with a feedback factor, β of 0.01 is introduced into an amplifier with a gain of
200 and bandwidth of 6 MHz, obtain the resulting bandwidth of the feedback amplifier.
b)
With the help of a suitable BJT based voltage series feedback amplifier diagram, explain the
feature and benefits of negative feedback amplifiers.
6.a) Substantiate the requirement of positive feedback in amplifier for oscillations. Relate the requirement
to Barkhausen Criterion.
5.
With the help of neat circuit diagram, explain how sustained oscillations are obtained in RC phase
5.a)
M1
M1
shift BJT based oscillator. Derive the expression for frequency of oscillations.
A single stage class A amplifier Vcc=20V, VCEQ =10V, ICQ =600mA, RL=16 Ω. The ac
output current varies by ± 300mA, with the ac input signal. Find
i) The power supplied by the dc source to the amplifier circuit.
ii) AC power consumed by the load resistor.
iii) AC power developed across the load resistor.
iv) DC power wasted in transistor collector.
v) Overall efficiency
vi) Collector efficiency.
List the advantages of complementary-symmetry configuration over push pull configuration.
7.a)
b).
6.
Describe the following briefly:
a) Stagger Tuned Amplifiers – Operation and comparison with synchronous tuning
b) Heat Sinks for tuned power amplifiers.
9. For the amplifier circuit shown with partially unbypassed emitter resistance, calculate the voltage gain
with R4 in place and with R4 shorted. Consider hie = 1.1KΩ, hfe = 100, hre & hoe are negligibly small.
Assume R1 and R2 to be 100KΩ and 22 KΩ respectively.
2
Analyse what the output voltage should be if the DC power supply given to a CE amplifier is
shorted to ground.
10..a)
With the help of circuit diagram and equivalent circuit of a Darlington amplifier generate the
expression for the overall input impedance of the pair.
Develop a generalized expression for overall current gain(A IS) when two transistor stages with
ROUT2 < RL, ROUT1 > RIN2, RIN1> RS and individual voltage gains are AV1, AV2.
A transistor amplifier in CE configuration is operated at high frequency with the following
specifications. fT=6MHz, gm=0.04,hfe =50, rbb’ =100 Ω, Rs =500 Ω , Cb’c =10pF, RL=100 Ω.
Compute the voltage gain, upper 3dB cut-off frequency, and gain bandwidth product (GBW).
Derive an expression for the overall higher cut-off frequency of a two stage amplifier
b)
11.a)
b)
with identical stages of individual higher cut-off frequency, fH.
12.a)
b)
Discuss the effect of different type of loads to a common source MOS amplifier.
Differentiate between cascode and folded cascode configurations.
13.a). If the non-linear distortion in a negative feedback amplifier with an open loop gain of 100 is reduced
from 40% to 10%with feedback, compute the feedback factor, β of the amplifier.
b)
Draw the circuit diagram of a current series feedback amplifier, Derive expressions to show the
effect of negative feedback on input & output impedances, bandwidth, distortion of the amplifier.
14.a)
b)
c)
Differentiate between RC and LC type oscillators.
Derive the expression for frequency of oscillation in a Hartley Oscillator.
State Barkhausen Critterion for Oscillations
15.a)
Derive the expression for maximum conversion efficiency for a simple series fed Class A power
amplifier.
What are the drawbacks of transformer coupled power amplifiers?
A push pull amplifier utilizes a transformer whose primary has a total of 160 turns and whose
secondary has 40 turns. It must be capable of delivering 40W to an 8 Ω load under maximum
power conditions. What is the minimum possible value of V cc?
b)
c)
16.a)
5.
List possible configurations of tuned amplifiers.
Derive an expression for bandwidth of a capacitive coupled tuned amplifier in CE
configuration. Make necessary assumptions and mention them.
17.a)
For the common emitter amplifier shown, draw the AC and DC load lines. Determine the peak -topeak output voltage for a sinusoidal input voltage of 30mV peak-to-peak. Assume C1, C2 and C3
are large enough to act as short circuit at the input frequency. Consider hie = 1.1KΩ, hfe = 100, hre
& hoe are negligibly small.
3.
State Miller’s theorem. Specify its relevance in the analysis of a BJT amplifier.
c)
Write expressions for AV and RIN of a Common Emitter amplifier.
18.a)
Derive expressions for overall voltage gain and overall current gain of a two-stage RC
coupled amplifier.
b)
19.a)
List out the special features of Darlington pair and cascode amplifiers.
Discuss the effect of emitter bypass capacitor and input & output coupling capacitors
on the lower cut-off frequency if number of amplifiers are cascaded.
b)
20.a)
b)
21.a)
b)
c)
Describe how an emitter follower behaves at high frequencies.
Discuss the effect of different types of loads to a common source MOS amplifier.
Differentiate between cascode and folded cascode configurations.
The β and the open loop gain of an amplifier are -10% and -80 respectively. By how
much % the closed loop gain changes if the open loop gain increases by 25%?
Compare the characteristics of feedback amplifiers in all the four configurations.
Reason out why 2 stages are required to implement current shunt feedback.
22. Starting from the description of a generalized oscillator, derive the expression for frequency of
oscillation in a colpitts oscillator.
23.a) With the help of a suitable circuit diagram, show that the maximum conversion efficiency of a
class B power amplifier is 78.5%.
b)
Explain how Total harmonic distortion can be reduced in a Class B push-pull
configured amplifier.
24.a)
b)
25.a)
b)
c)
26.a)
b)
Derive an expression for the bandwidth of a synchronous tuned circuit.
Discuss the necessity of stabilization circuits in tuned amplifiers.
Draw the circuit diagram of a common collector amplifier along with its equivalent circuit. Derive
expressions for AV and RI.
What is meant by small signal for analyzing a BJT based amplifier?
What is non-linear distortion? List the causes for this type of distortion in amplifiers.
Discuss various possibilities of inter-stage coupling of amplifiers.
For the two-stage RC coupled amplifier circuit shown, calculate the Individual stage voltage gains
and the overall voltage gain. Input impedance of individual stages is
given as 2.4 KΩ and β of individual transistors as 80.
27.a)
A transistor has fα = 8MHz, and β=80.when connected as an amplifier, it has stray capacitance of
100pF at the output terminal. Calculate its upper 3dB frequency when Rload is
b)
28.a)
b)
29.a)
b)
c)
i) 10KΩ
ii) 100KΩ.
Discuss the effect of coupling capacitors of a CE amplifier on the overall frequency response of
amplifier.
Discuss the effect of different type of loads to a common source MOS amplifier.
Differentiate between cascode and folded cascode configurations.
An amplifier has a gain of 50 with negative feedback. For a specified output voltage, if the input
required is 0.1V without feedback and 0.8V with feedback, Compute β and open loop gain.
Through the block schematics, show four types of negative feedback in amplifiers.
List the advantages of negative feedback in amplifiers.
30.a)
b)
List out the merits × demerits of oscillators.
With the help of suitable schematic and description, show that both positive and negative feedback
are used in a Wien Bridge oscillator. Establish the condition for oscillations.
31.a)
State the merits of using push pull configuration? Describe the operation of class B push pull
amplifier and show how even harmonics are eliminated.
A single ended class A amplifier has a transformer coupled load of 8 Ω. If the transformer turns
ration is 10, find the maximum power output delivered to the load.
b)
Take the zero signal collector current of 500mA.
32.a)
b)
Derive the expressions for Bandwidth and Q-factor of single tuned, capacitively
coupled amplifiers. List the assumptions made for the derivation.
What is stagger tuning? Suggest possible applications.
33.a) Draw the circuit diagram of Common Drain amplifier and derive an expression for
its Voltage gain.
b) The h-parameters of the transistor used in CE amplifier are h = 50, h =1.1KΩ, h =
fe
-4
2.5x10 , h
oe
ie
re
= 24μ A/V. Find out current gain and voltage gains with and without
source resistance, input and output impedances, given that R = 10K and R = 1 K.
L
S
34.a) Discuss about different types of distortions that occur in amplifier circuits.
b) Three identical non interacting amplifier stages in cascade have an overall gain of 1
dB down at 30 Hz compared to mid band. Calculate the lower cutoff frequency of
the individual stages.
35.a) Draw and explain the small signal equivalent circuit for an emitter follower stage
at high frequencies.
b) Consider a CE stage with a resistive load R . Using Miller’s theorem Find input
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capacitance at mid-band frequencies and high frequencies.
36. (a) For a single stage transistor amplifier, RS = 10K and RL= 10K. The h-parameter values are hfc =
51, hic =1.1K; hrc _ 1; hoc = 25 _A/V Find AI; AV; AV S, Ri, and Ro for the CC transistor configuration.
(b) For a single stage transistor amplifier, RS=1K; and RL= 10K the h-parameter values are hfe = 50, hie
=1.1K; hre = 2.5x10�4, hoe = 25 _ A/V. Find AI; AV; AV S, Ri, and Ro for the CE transistor
configuration.
37. (a) For the emitter follower circuit shown in _figure 1, calculate the quiescent voltage and current for
VCC = 20Volts, hfc =120, hic = 1.1K, hoc = 2.5 x 10�6 mhos and hrc is negligibly Small. Reactance of
capacitance need not be considered at the frequencies of interest.
If R1 = 27K, R2 = 5.6K, RL = RE =220, RS = 0, Find the maximum undistorted peak-to-peak output
voltage.
(b) Compare and contrast Common Emitter, Common Collector and Common Base amplifiers in all
aspects.
38. (a) Derive the expression for the bandwidth of multistage amplifier.
(b) What are the problems of Direct coupled amplifiers?
(c) Why RC coupling is popular?
(d) Why transformer coupling is not used in the initial stage of a multistage amplifier?
39. (a) Derive the expression for output conductance and diffusion capacitance of hybrid-_ CE amplifier.
(b) A single-stage CE ampli_er is to have a bandwidth fH of 5MHz with RL = 500. Assume hfe = 100,
gm= 100mA/V, rbb0 = 100, Cc= 1PF, and fT =400 MHz
i. Find the value of the source resistance that will give the required band-width.
ii. with the value of Rs, determined in part (i), _nd the mid band voltage gain Vo / VS.
40.a) Differentiate between direct and capacitive coupling of multiple stages of
amplifiers.
b) With the help of a neat circuit diagram, describe the working of a cascode amplifier.
c) What are the merits and demerits of a cascade amplifier over a simple Common Emitter amplifier?
41. For the amplifier circuit shown with partially unbypassed emitter resistance, calculate the voltage gain
with R in place and with R shorted. Consider h = 1.1KΩ, h = 100, h & h are negligibly small. Assume
4
4
R and R to be 100KΩ and 22 KΩ respectively.
1
2
ie
fe
re
oe
b) Analyse what the output voltage should be if the DC power supply given to a CE amplifier is shorted to
ground.
b) Reason out the causes and results of Phase & Frequency distortions in transistor amplifiers. [9+6] ha
b) State Miller’s theorem. Specify its relevance in the analysis of a BJT amplifier.
c) Write expressions for A and R of a Common Emitter amplifier.
V
IN
42. Derive expressions for overall voltage gain and overall current gain of a two-stage RC coupled
amplifier.
43.a) For the common emitter amplifier shown in Figure.1, Draw the AC and DC load
lines. Determine the peak-to-peak output voltage for a sinusoidal input voltage
of 30mV peak-to-peak. Assume C , C and C are large enough to act as short
1
2
circuit at the input frequency. Consider h
negligibly small.
3
ie
= 1.1KΩ, h = 100, h
fe
re
& h
oe
are
b) List the merits and demerits of a JFET over a BJT.
c) Write the expressions for A and R of a CE amplifier.
V
in
44 a) for the common emitter amplifier shown in Figure.1, Draw the AC and DC load lines. Determine the
peak-to-peak output voltage for a sinusoidal input voltage of 30mV peak-to-peak. Assume C , C and C are
1
2
3
large enough to act as short circuit at the input frequency. Consider h = 1.1KΩ, h = 100, h & h are
ie
negligibly small.
fe
re
oe
b) List the merits and demerits of a JFET over a BJT.
c) Write the expressions for A and R of a CE amplifier.
V
in
45.(a) Derive the expression for the high 3-dB frequency f _h of n-identical non inter-acting stages in terms
of fH for one stage.
(b) If four identical amplifiers are cascaded each having fH =100 KHz, determine the overall upper 3dB
frequency f _h. Assume non interacting stages.
(c) Write a short note on Bootstrapped Darlington circuit.
47. (a) Show that in Hybrid - model, the diffusion capacitance is proportional to the emitter bias current.
(b) What is the frequency range to consider Giacolletto model of a transistor at high frequencies? What is
the significance of fT in discussing the frequency range of a transistor at high frequencies?
48. For a given CE amplifier with _=100, Ic=5mA, Vce=10V, hie=800, ho e = 1 0�4 mhos hre= 10�4.
Take fT =50MHz and Cob=3pF. Compute all hybrid Q parameters.
49. (a) Compare the inter-stage coupling methods in RC coupled amplifier and Darlington pair.
(b) Generate a generalized expression for overall current gain (AIS) when two transistor stages with
ROUT2> RL, ROUT1 > RIN2 , RIN1> RS and individual voltage gains are AV 1 and AV 2 are cascaded.
50. (a) Draw the FET amplifier equivalent circuit looking into the drain and _nd its gain & o/p impedance?
(b) Starting with the definition of gm and rd, show that if two identical FETs are connected in parallel, gm
is doubled and rd is halved since µ = rd gm, then remains unchanged.
51. (a) What is square law distortion? What is its effect in FET amplifiers? Compare
important characteristics of CD, CS, CG FET amplifier.
(b) A self-biased CE amplifier circuit has R1 = 100K , R2 = 10K, Rc = 5K, RE= 1K, RS = 10K. Compute
AI , AV , AV S and Ri. The h-parameters of the transistor are hie = 1.1k, hfe = 50, hre = 2.5 x 10�4 , hoe =
25_A/V.
52. For the circuit shown, calculate the dc bias, voltage gain, input impedance and
output impedance for the cascade amplifier shown in Figure.
53.a) With the help of circuit diagram and equivalent circuit of a Darlington amplifier
generate the expression for the overall input impedance of the pair.
b) Develop a generalized expression for overall current gain(A ) when two transistor stages with
IS
R
OUT2
<R ,R
L
OUT1
>R
,R
IN2
> R and individual voltage gains are A , A .
IN1
S
V1
V2
54.a) A transistor amplifier in CE configuration is operated at high frequency with the
following specifications. f =6MHz, g =0.04,h =50, r =100 Ω, R =500 Ω , C
T
m
fe
bb’
s
b’c
=10pF, R =100 Ω. Compute the voltage gain, upper 3dB cut-off frequency, and
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gain bandwidth product (GBW).
b) Derive an expression for the overall higher cut-off frequency of a two stage amplifier with identical
stages of individual higher cut-off frequency, f .
H
55.a) Discuss the effect of different type of loads to a common source MOS amplifier.
b) Differentiate between cascode and folded cascode configurations.
b) List out the special features of Darlington pair and cascode amplifiers.
56.a) Discuss the effect of emitter bypass capacitor and input & output coupling
capacitors on the lower cut-off frequency if number of amplifiers are cascaded.
b) Describe how an emitter follower behaves at high frequencies.
57.a) Discuss the effect of different types of loads to a common source MOS amplifier.
b) Differentiate between cascode and folded cascode configurations.
58.a) With the help of circuit diagram and equivalent circuit of a Darlington amplifier,
generate the expression for the overall input impedance of the pair.
b) List out various types of distortions that occur in transistor amplifiers. Discuss the causes for each type
listed.
59.a) With the help of circuit diagram and equivalent circuit of a Darlington amplifier,
generate the expression for the overall input impedance of the pair.
b) List out various types of distortions that occur in transistor amplifiers. Discuss the causes for each type
listed.
60. (a) Draw the circuit of a voltage series feedback circuit and explain it.
(b) What are the possible amplifiers circuits in any feedback system? Discuss.
61. Obtain the expressions for the voltage gain in the low frequency, medium frequency and high frequency
ranges in the case of single stage amplifier.
62. (a) Give the two Barkhausen conditions required in order for sinusoidal oscillations to be sustained.
(b) Draw the circuit diagram of RC phase - shift oscillator and derive the expression for frequency of
Oscillations & condition for sustained Oscillations.
63.a) If negative feedback with a feedback factor, β of 0.01 is introduced into an
amplifier with a gain of 200 and bandwidth of 6 MHz, obtain the resulting
bandwidth of the feedback amplifier.
b) With the help of a suitable BJT based voltage series feedback amplifier diagram, explain the features and
benefits of negative feedback in amplifiers.
64.a). If the non-linear distortion in a negative feedback amplifier with an open loop gain
of 100 is reduced from 40% to 10%with feedback, compute the feedback factor,
β of the amplifier.
b) Draw the circuit diagram of a current series feedback amplifier, Derive expressions to show the effect of
negative feedback on input & output impedances, bandwidth, distortion of the amplifier.
65.a) The β and the open loop gain of an amplifier are -10% and -80 respectively. By
how much % the closed loop gain changes if the open loop gain increases by
25%?
b) Compare the characteristics of feedback amplifiers in all the four configurations.
c) Reason out why 2 stages are required to implement current shunt feedback.
66. Starting from the description of a generalized oscillator, derive the expression for frequency of
oscillation in a colpitts oscillator.
67.a) What is Harmonic distortion in transistor amplifier circuits? Discuss on second
harmonic distortion.
b) Draw and explain the operation of Class-AB power amplifier. How will it eliminate
cross over distortion?
68.a) Draw and explain the circuit diagram of a single tuned Capacitance coupled
amplifier. Also explain its operation.
b) Draw and explain the significance of Gain versus Frequency curve of tuned
amplifiers when they are used in radio receivers.
c) Draw the Ideal and actual frequency response curves of a single tuned amplifier.
69. Explain in detail the effect of cascading tuned amplifiers and hence derive the expression for bandwidth
of n-stage amplifier. Also draw the frequency response and explain what happens as the number of stages
increases?
70. (a) Draw the circuit of class -A series fed power amplifier and derive the expression for output
power Po. (b) Draw and discuss the operation of Class - C power amplifier.
71.(a) What is coefficient of coupling in a double tuned amplifier? Discuss its effect on the frequency
response.
(b) Derive the expression for bandwidth of a double tuned amplifier.
72. (a) A transistor supplies 0.85W to a 5K load, the zero signal dc collector current
is 30mA, and the dc collector current with signal is 36mA.Determine the percent harmonic distortion.
(b) Derive an expression for conversion efficiency of a class B power amplifier.
73. (a) Why two tuned circuits are used in double tuned amplifier?
(b) What are the advantages of stagger tuned amplifier?
(c) Why parallel resonance circuits are used in tuned amplifiers?
74. (a) A single ended class A power amplifier is coupled to an 8 load, using a transformer with a turn ratio
of 5:1 with a 50V supply the transistor is biased to have a quiescent collector current of 250mA. When a
sinusoidal signal is applied to the base, the collector voltage varies between a maximum of 5V and
maximum of 90V. Estimate the efficiency, power output & second – harmonic distortion of this stage.
(b) Discuss how rectification may takes place in a power amplifier?
75. (a) Explain the differences between the function of a transformer used in a power amplifier and that
used in a double tuned voltage amplifier.
(b) Explain the method of determination of total harmonic distortion in push pull power amplifiers using 5
- point analysis.
(c) Calculate the harmonic distortion components for an output signal, in push pull power amplifiers having
fundamental amplitude of 2.5 Volts, second harmonic amplitude of 0.25 Volts, third harmonic amplitude of
0.1 Volts, fourth harmonic amplitude of 0.05V. Also calculate the total harmonic distortion.
76. (a) Determine the input power, output power and efficiency for a class B power amplifier circuit with
Vcc=30 V , Im=1 Amp and RL=10 .
(b) Draw the circuit of transformer less pushpull amplifier circuit with loud speaker as the load resistance.
Justify the circuit behavior with \emitter follower" circuit operation.
77.a) Substantiate the requirement of positive feedback in amplifier for oscillations.
Relate the requirement to Barkhausen Criterion.
b) With the help of neat circuit diagram, explain how sustained oscillations are obtained in RC phase shift
BJT based oscillator. Derive the expression for frequency of oscillation.
78.a) A single stage class A amplifier V =20V, V
cc
CEQ
=10V, I
CQ
=600mA, R =16 Ω. The ac
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output current varies by 300mA, with the ac input signal. Find ±
i) The power supplied by the dc source to the amplifier circuit.
ii) AC power consumed by the load resistor.
iii) AC power developed across the load resistor.
iv) DC power wasted in transistor collector.
v) Overall efficiency
vi) Collector efficiency.
b). List the advantages of complementary-symmetry configuration over push pull configuration
79.. Describe the following briefly:
a) Stagger Tuned Amplifiers – Operation and comparison with synchronous tuning
b) Heat Sinks for tuned power amplifiers.
80.a) Differentiate between RC and LC type oscillators.
b) Derive the expression for frequency of oscillation in a Hartley Oscillator.
81.a) Derive the expression for maximum conversion efficiency for a simple series fed
Class A power amplifier.
b) What are the drawbacks of transformer coupled power amplifiers?
c) A push pull amplifier utilizes a transformer whose primary has a total of 160 turns
and whose secondary has 40 turns. It must be capable of delivering 40W to an 8
Ω load under maximum power conditions. What is the minimum possible value
of V ?
cc
82.a) List possible configurations of tuned amplifiers.
b) Derive an expression for bandwidth of a capacitive coupled tuned amplifier in CE configuration.
Make necessary assumptions and mention them.
83.a) With the help of a suitable circuit diagram, show that the maximum conversion
efficiency of a class B power amplifier is 78.5%.
b) Explain how Total harmonic distortion can be reduced in a Class B push-pull
configured amplifier.
84.a) Derive an expression for the bandwidth of a synchronous tuned circuit.
b) Discuss the necessity of stabilization circuits in tuned amplifiers.
85.a) Derive the expression for maximum conversion efficiency for a simple series fed
Class A power amplifier. What are the drawbacks of transformer coupled power
amplifiers?
b) A single stage class A amplifier V =20V, V
=10V, I =600mA, R =16 Ω. The ac
cc
CEQ
CQ
output current varies by ±300mA, with the ac input signal. Find
i) Power supplied by the dc source to the amplifier circuit.
ii) The AC power consumed by the load resistor.
iii) Conversion efficiency.
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86. a)Derive an expression for ‘bandwidth’ and ‘quality factor’ of a capacitive coupled
single tuned amplifier in CE configuration. Make necessary assumptions and
mention them.
b). Substantiate the necessity of the following in tuned amplifiers.
a) Heat Sinks
b) Stabilization circuits
87.a) Derive the expression for maximum conversion efficiency for a simple series fed
Class A power amplifier. What are the drawbacks of transformer coupled power
amplifiers?
b) A single stage class A amplifier V =20V, V
=10V, I =600mA, R =16 Ω. The ac
cc
CEQ
CQ
output current varies by ±300mA, with the ac input signal. Find
i) Power supplied by the dc source to the amplifier circuit.
ii) The AC power consumed by the load resistor.
iii) Conversion efficiency.
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(11.2) QUESTION BANK – GATE
1. In a voltage-voltage feedback as shown below, which one of the following statements is TRUE if the
gain k is increased?
GATE 2013
(A) The input impedance increases and output impedance decreases
(B) The input impedance increases and output impedance also increases
(C) The input impedance decreases and output impedance also decreases
(D) The input impedance decrases and output impedance increases
2. The ac schematic of an NMOS common-source stage is shown in the figure below, where part of the
biasing circuits has been omitted for simplicity. For the nchannel MOSFET M, the Transconductance m g
channel length modulation effect are to be neglected. The lower cutoff
frequency in Hz of the circuit is approximately at
GATE 2013
(A) 8
(B) 32
(C) 50
(D) 200
3. The current ib through the base of a silicon npn transistor is 1 + 0.1 cos (10000πt)mA At 300 K, the rπ in
the small signal model of the transistor is
GATE 2012
(A) 250 Ω
(C) 25 Ω
(B) 27.5 Ω
(D) 22.5 Ω
4. The voltage gain Av of the circuit shown below is
GATE 2012
(A) Av = 200
(C) Av = 20
(B) Av = 100
(D) Av = 10
5. In the circuit shown below, capacitors C1 and C2 are very large and are shorts at the input frequency. vi
is a small signal input. The gain magnitude Vo/Vi at 10 M rad/s is
GATE 2012
(A) maximum
(B) minimum
(C) unity
(D) zero
(11.3) QUESTION BANK – IES
1. In the circuit shown, the two transistors are matched. Find an expression for I1 in terms of IC1 and β.
Assume VBE = 0.6 V and β to be very large, calculate I1 and I2. Calculate IC1 , when β = 20.
2. It is desired to operate the JFET shown in fig. below at VGS = –1.0 V, VDS = 4.0 V and IDS = 1mA.
Determine the value RD and RS.
3. Determine the voltage gain for the amplifier circuit shown below. Vi is the input voltage between the
gate terminal and ground. Neglect all capacitances.
4. What is the class-D operation of power amplifier ? Draw the circuit diagram of transistorized class-D
amplifier and explain its working.
5. Draw the circuit diagram of a Colpitt’s oscillator using transistor. Derive an expression for its frequency
of oscillations. Deduce the starting condition for this oscillator.
6. In an R-C coupled amplifier, shown below, the BJT has hfe = 50. All bypass and coupling capacitors are
assumed to have zero reactance at the signal frequency. Find the quiescent conditions and draw the smallsignal equivalent circuit, neglecting hoe and hre.
7. For the amplifier circuit shown in Fig. 3, find the mid-band gain using small signal equivalent circuit.
Take early voltage of NPN transistor 95 V and that of PNP transistors as 76 V. Forward resistance of the
diode is negligible and thermal equivalent voltage, VT = 0.025 V, β is large.
(12)
ASSIGNMENT QUESTION SETS
Unit – I
SET 1:
1.
Reason out the causes and results of Phase & Frequency distortions in transistor amplifiers.
2.
Write expressions for AV and RIN of a Common Emitter amplifier.
3.
State Miller’s theorem. Specify its relevance in the analysis of a BJT amplifier.
4. Draw the circuit diagram of a common collector amplifier along with its equivalent circuit. Derive
expressions for AV and RI.
SET 2:
1.
What is meant by small signal for analyzing a BJT based amplifier?
2.
What is non-linear distortion? List the causes for this type of distortion in amplifiers.
3.
Draw the ciruit diagram of Emitter follower and derive the equation for voltage & current gains.
4.
Draw the simpli ed hybrid model for the CC circuit and derive expressions for input Resistance,
output resistance voltage gain and current gain.
SET 3:
1.
Draw the simpli ed hybrid model for the CC circuit and derive expressions for input Resistance,
output resistance voltage gain and current gain.
2.
Obtain CC `h' parameters interms of CE parameters.
3.
Draw the CE ampli er with un by passed emitter resistance and derive expression for its Ri & Av
4. How the need of high input impedance can be full lted using two CC configuration?
SET 4:
1.
What is meant by small signal for analyzing a BJT based amplifier?
2.
What is non-linear distortion? List the causes for this type of distortion in amplifiers.
3.
Draw the ciruit diagram of Emitter follower and derive the equation for voltage & current gains.
4.
Draw the simpli ed hybrid model for the CC circuit and derive expressions for input Resistance,
output resistance voltage gain and current gain.
Unit – II
SET 1:
1.
Obtain the expressions for the voltage gain in the low frequency, medium frequency and high
frequency ranges in case of single stage amplifier.
2. Explain the Principle of opeartion of direct coupled ampli er and mention its advantages.
3.
What is the use of transformer coupling in the output stage of multi stage amplier?
4.
Why RC coupling is mostly used for voltage amplier.
SET 2:
1.
Define unity gain frequency. Obtain the necessary relation using transistor frequency response.
2. Differentiate between direct and capacitive coupling of multiple stages of amplifiers.
3.
With the help of a neat circuit diagram, describe the working of a cascode amplifier.
4.
What are the merits and demerits of a cascade amplifier over a simple Common Emitter amplifier.
SET 3:
1. With the help of circuit diagram and equivalent circuit of a Darlington amplifier generate the
expression for the overall input impedance of the pair.
2.
Develop a generalized expression for overall current gain(A IS) when two transistor stages with
ROUT2 < RL, ROUT1 > RIN2, RIN1> RS and individual voltage gains are Av1, Av2
3.
Derive expressions for overall voltage gain and overall current gain of a two-stage RC coupled
amplifier.
4.
List out the special features of Darlington pair and cascode amplifiers.
SET 4:
1.
Discuss various possibilities of inter-stage coupling of amplifiers.
2.
Write the equation for overall gain of a n - stage cascaded Ampli er.
3.
How does the frequency response an ampli er change with cascading of ampli er stages?
4.
Explain the choice of con guration in a cascade of ampliers.
5.
Unit – III
SET 1:
1.
Obtain the expressions for the voltage gain in the low frequency, medium frequency and high
frequency ranges in the case of single stage amplifer.
2.
Derive the expression for the bandwidth of multistage amplier.
3.
Define unity gain frequency. Obtain the necessary relation using transistor frequency response.
4.
Derive the equation for the lower 3dB frequency of CE con guration.
SET 2:
1.
Draw the hybrid pi model of common emitter con guration and describe each component in the
model
2. Derive the expressions for hybrid Π conductance, gce, and gbb’ of a transistor.
3.
Explain how hybrid Π parameters, gm and gce vary with Ic, Vce and temperature.
4.
Compute the overall lower cut-off frequency of an identical two stage cascade of amplifiers with
individual lower cut off frequency given as 432 Hz.
SET 3:
1.
Define fβ and fT and also establish the relationship between fβ and fT .
2. Explain why the upper 3-dB frequency for current gain is not the same as fH for voltage gain.
3.
A Silicon PNP transistor has an fT = 400MHz. What is the base thickness?
4.
In terms of what parameters is the high frequency response of a CE stage obtained.
SET 4:
1. A transistor amplifier in CE configuration is operated at high frequency with the following
specifications. fT=6MHz, gm=0.04,hfe =50, rbb’ =100 Ω, Rs =500 Ω , Cb’c =10pF, RL=100 Ω.
Compute the voltage gain, upper 3dB cut-off frequency, and gain bandwidth product (GBW).
2.
Derive an expression for the overall higher cut-off frequency of a two stage amplifier
3.
Draw the ciruit diagram of Emitter follower and derive the equation for voltage & current gains.
4.
Define fβ and fT and also establish the relationship between fβ and fT .
Unit - IV
SET 1:
1. Draw the FET ampli er equivalent circuit looking into the drain and nd its gain & o/p impedance?
2.
Starting with the de nition of gm and rd, show that if two identical FETs are connected in
parallel, gm is doubled and rd is halved since = rdgm, then remains unchanged.
3.
Draw the small signal high frequency equivalent circuit for the source follower and its voltage
gain input and outputimpedances?
4.
Derive an expression for voltage gain of a common source FET amplier with and without source
resistance included in the circuit.
SET 2:
1.
Discuss the effect of different type of loads to a common source MOS amplifier.
2.
Differentiate between cascode and folded cascode configurations.
3.
Derive the equation for voltage gain of a Common Source FET ampli er.
4. Sketch the circuit of a CS amplier. Derive the expression for the voltage gain at low frequencies.
What is the maximum value of voltage gain?
SET 3:
1. Sketch the circuit of a CS amplier. Derive the expression for the voltage gain at low frequencies.
What is the maximum value of voltage gain?
2. Derive an expression for voltage gain of a common source FET amplier with and without
source resistance included in the circuit.
3.
Why a FET cannot be explained with h-parameters?
4.
Derive an expression for Trans - conductance using FET model.
SET 4:
1.
Draw the small signal high frequency equivalent circuit for the source follower and its voltage
gain input and outputimpedances?
2.
Derive an expression for voltage gain of a common source FET amplier with and without source
resistance included in the circuit.
3.
Discuss the effect of different type of loads to a common source MOS amplifier.
4.
Differentiate between cascode and folded cascode configurations.
Unit - V
SET 1:
1.
Draw the circuit of a voltage series feedback circuit and explain it.
2.
What are the possible ampli ers circuits in any feedback system? Discuss.
3.
Draw a feedback ampli er in block diagram form and explain each block giving its function.
4.
Distinguish between regenerative and degenerative feedback in ampliers.
SET 2:
1. Draw the equivalent circuit for a current ampli er and what are the values of R i & Ro for ideal
ampli er?
2.
The open loop gain of an ampli er is 100. What will be the overall gain when a negative feed back
of 0.5 is applied to the ampli er?
3.
What are the di erent mixing techniques used in any feed back system? Ex-plain.
4.
State the condition in terms of (1 + A ) which a feed back ampli er must satisfy in order to be
stable.
SET 3:
1. If negative feedback with a feedback factor, β of 0.01 is introduced into an amplifier with a gain of
200 and bandwidth of 6 MHz, obtain the resulting bandwidth of the feedback amplifier.
2.
With the help of a suitable BJT based voltage series feedback amplifier diagram,
explain the features and benefits of negative feedback in amplifiers.
3.
If the non-linear distortion in a negative feedback amplifier with an open loop gain of 100 is
reduced from 40% to 10%with feedback, compute the feedback factor, β of the amplifier.
4.
Draw the circuit diagram of a current series feedback amplifier, Derive expressions to show the
effect of negative feedback on input & output impedances, bandwidth, distortion of the amplifier.
SET 4:
1.
Through the block schematics, show four types of negative feedback in amplifiers.
2.
List the advantages of negative feedback in amplifiers.
3.
Derive an expression for the transfer gain of a feedback amplier.
4. Discuss about the types of negative feedback ampli ers giving the effect of each type of
feedback on the parameters of the amplier.
Unit - VI
SET 1:
1. Give the two Barkhausen conditions required in order for sinusoidal oscillations to be sustained.
2.
Draw the circuit diagram of RC phase - shift oscillator and derive the expression for frequency of
Oscillations & condition for sustained Oscillations.
3.
In a colpitts oscillator, C1 = 0.2 F and C2 = 0.04 F. If the frequency of oscillation is 10KHz, nd the
value if Inductor. Also, nd the required gain for oscillation.
4.
Determine the frequency of oscillations in a wien bridge oscillator.
SET 2:
1.
Draw the colpilts oscillator circuit and explain its working.
2.
Substantiate the requirement of positive feedback in amplifier for oscillations. Relate the
requirement to Barkhausen Criterion.
3.
With the help of neat circuit diagram, explain how sustained oscillations are obtained in RC phase
shift BJT based oscillator. Derive the expression for frequency of oscillation.
4. Differentiate between RC and LC type oscillators.
SET 3:
1.
Derive the expression for frequency of oscillation in a Hartley Oscillator.
2.
State Barkhausen Critterion for Oscillations
3.
Starting from the description of a generalized oscillator, derive the expression for
frequency of oscillation in a colpitts oscillator.
4. List out the merits & demerits of oscillators.
SET 4:
1. Draw the electrical model of a piezoelectric crystal.
2.
Over what portion of the reactance curve do we desire oscillations to take place when the
crystal is used as part of a sinusoidal oscillator? Explain.
3.
Sketch a circuit of a crystal - controlled oscillator and explain its function.
4.
Explain the frequency - stability criterion for a sinusoidal oscillator.
Unit –VII
SET 1:
1.
Show that the maximum conversion efficiency of the idealized class B push - pull circuit is 78.5%.
2.
Explain the origin of crossover distortion. Describe a method to minimize this distortion.
3.
What is class B amplifier? Why is it employed? Give its circuits, design equations, characteristics
& limitations.
4.
A transformer coupled Class A large signal amplifier has maximum and minimum values of
collector to emitter voltage of 25V and 2.5V. Determine its collector efficiency.
SET 2:
1. A single stage class A amplifier Vcc=20V, VCEQ =10V, ICQ =600mA, RL=16 Ω. The ac output
current varies by ± 300mA, with the ac input signal. Find
i) The power supplied by the dc source to the amplifier circuit.
ii) AC power consumed by the load resistor.
iii) AC power developed across the load resistor.
iv) DC power wasted in transistor collector.
v) Overall efficiency
vi) Collector efficiency.
2. List the advantages of complementary-symmetry configuration over push pull configuration.
3. Derive the expression for maximum conversion efficiency for a simple series fed Class A power
amplifier.
4.
What are the drawbacks of transformer coupled power amplifiers?
SET 3:
1. With the help of a suitable circuit diagram, show that the maximum conversion efficiency of a
class B power amplifier is 78.5%.
2.
Explain how Total harmonic distortion can be reduced in a Class B push-pull amplifier.
3. State the merits of using push pull configuration? Describe the operation of class B push pull
amplifier and show how even harmonics are eliminated.
4.
A single ended class A amplifier has a transformer coupled load of 8 Ω. If the transformer turns
ration is 10, find the maximum power output delivered to the load. Take zero signal collector
current of 500mA.
SET 4:
1. What is push-pull configuration and how does this circuit reduce the harmonic distortion?
2.
Derive an expression for the output power of a class A large - signal amplifier in terms of
Vmax, Vmin Imax & Imin.
3.
What is a class B amplifier? Where is it employed? Give its circuits, design equations,
characteristics & limitations.
4.
A transistor supplies 0.8W to a 5K load. The zero signal dc collector current is 30mA, and the dc
collector current with signal is 36mA. Determine the percent second - harmonic distortion.
Unit –VIII
SET 1:
1. Why two tuned circuits are used in double tuned amplifier?
2.
What the advantages are of stagger tuned amplifier?
3. Compare neutralization and unilaterlization methods of tuned amplifiers
4.
What the limitations are of stagger tuned amplifiers?
SET 2:
1.
What happen when no. of stages is increased in single tuned cascaded amplifiers
2.
How the frequency response of doubled tuned amplifier depends on degree of coupling between
two tank circuits?
3. Draw the equivalent circuit of double tuned amplifier and derive the expression
for gain at resonance.
4.
Derive the expression for effective bandwidth of cascaded tuned amplifier.
SET 3:
1.
Describe briefly Stagger Tuned Amplifiers – Operation and comparison with synchronous tuning
2. List possible configurations of tuned amplifiers.
3.
Derive an expression for bandwidth of a capacitive coupled tuned amplifier in CE configuration.
4. What is stagger tuning? Suggest possible applications.
SET 4:
1.
What the limitations are of stagger tuned amplifiers?
2. List possible configurations of tuned amplifiers.
3.
Derive the expression for effective bandwidth of cascaded tuned amplifier.
4. Why two tuned circuits are used in double tuned amplifier?
(13)
TOPICS FOR STUDENT’S SEMINARS
1.
Magnetic Amplifiers
2.
Oven Controlled Crystal Oscillators
3. Crystal Oscillators for Industrial Applications
4.
Stereo audio amplifier with digital volume control
5.
Adjustable High/Low Frequency Sine wave generator
6.
Nostalgic Crystal Radio
7. MSF Radio Time Clock
8.
CB receiver
9. Band-Pass and Notch Filters
10. CB transmitter
SUBJECT: ELECTROMAGNETIC WAVES &TRANSMISSION LINES
S.NO
CONTENT
(1)
-
Objectives
(2)
-
Scope
(3)
-
Prerequisites
(4)
-
Syllabus
and
Relevance
1.
JNTU
2.
GATE
3.
IES
(5)
-
Suggested Books
(6)
-
Websites
(7)
-
Expert Details
(8)
-
Journals
(9)
-
Subject (lesson) Plan
(10)
-
Question Bank
(11)
-
(12)
-
1.
JNTU
2.
GATE
Tutorial Question sets on each unit
List of topics for student’s seminars
(1)
OBJECTIVES AND RELEVANCE
This course introduces the basic concepts of electric and magnetic properties which are the
foundation for Microwave and Radar Engineering subjects. The emphasis of this course is laid on
the basic analysis electric and magnetic fields and the effects of these fields in communication
systems. Transmission lines introduces about the path between sender and receiver.
(2)
SCOPE
The scope of This subject is useful in mobile communications and satellite Communications . The
generation of the Electric and Magnetic fields the directions of these fields in different mediums
gives the idea about the disturbances and applications of Electromagneti fields. The applicants of
Maxwell’s Equations are more useful for this subject
(3)
PREREQUISITES
This recommends continues practice of analysis of how the fields are generated. It needs the
knowledge about the mathematical fundamentals and applications of calculus like Integrations ,
differentiations and concepts of vectors.
(4.1)
SYLLABUS - JNTU
UNIT-I
OBJECTIVE
 Coloumbs law,basic law for electro static fields
 This concept derives the maxwell’s two equations
 Electric field intensiy,flux density calculations in these fields.
 Observation of the behaviour of the charge in Electro static field & electro dynamic field
 Types of the arrangments of Capacitors and the Electric field intensity in these
arrangments.
SYLLABUS
ELECTROSTATICS: Coulomb’s Law, Electric Field Intensity – Fields due to Different Charge
Distributions, Electric Flux Density, Gauss Law and Applications, Electric Potential, Relations
Between E and V, Maxwell’s Two Equations for Electrostatic Fields, Energy Density, Related
Problems. Convection and Conduction Currents, Dielectric Constant, Isotropic and Homogeneous
Dielectrics, Continuity Equation, Relaxation Time, Poisson’s and Laplace’s Equations;
Capacitance – Parallel Plate, Coaxial, Spherical Capacitors, Related Problems
UNIT-II
OBJECTIVE
 Convection and Conduction Currents
 Dielectric Constant, Isotropic and Homogeneous Dielectrics Observation of the
behaviour of the charge in Electro static field & electro dynamic field
 Continuity Equation, Relaxation Time, Poisson’s and Laplace’s Equations.
 Capacitance – Parallel Plate, Coaxial, Spherical Capacitors
SYLLABUS
ELECTROSTATICS-II: Convection and Conduction Currents, Dielectric Constant, Isotropic and
Homogeneous Dielectrics, Continuity Equation, Relaxation Time, Poisson’s and Laplace’s
Equations; Capacitance – Parallel Plate, Coaxial, Spherical Capacitors, Related Problems
UNIT - III
OBJECTIVE
 Bio savarts Law, basic law for Magetic fields
 This concept derives theMaxwell’s two equations

Magnetic field intensity,flux density calculations in these fields
SYLLABUS
Magneto Statics : Biot-Savart Law, Ampere’s Circuital Law and Applications, Magnetic Flux
Density, Maxwell’s Two Equations for Magnetostatic Fields, Magnetic Scalar and Vector
Potentials, Forces due to Magnetic Fields, Ampere’s Force Law, Inductances and Magnetic
Energy. Related Problems.
UNIT -IV
OBJECTIVE
 The earlier chapters gives the Maxwells equations in static fieldsonly Here
we find the Maxwell’s equations for time varying fields.
 Max well’s equations in different forms
 Displacement and conventional current density calculations
 The conditions of the charges at bounderies of the arrangements of differet
types of meterials
SYLLABUS
Maxwell’s Equations (Time Varying Fields): Faraday’s Law and Transformer emf,
Inconsistency of Ampere’s Law and Displacement Current Density, Maxwell’s Equations in
Different Final Forms and Word Statements. Conditions at a Boundary Surface : DielectricDielectric and Dielectric-Conductor Interfaces. Related Problems .
UNIT - V
OBJECTIVE
 Derivation of the wave equations in both fields.
 The wave propagation through dielectric media
 The wave propagation through conducters.
 Observing the losses that occured duri ng the transmission of the wave
through the different types the mediums
 Polarization the two or more fields are posisioned in near.
SYLLABUS
EM Wave Characteristics - I: Wave Equations for Conducting and Perfect Dielectric Media,
Uniform Plane Waves – Definition, All Relations Between E & H. Sinusoidal Variations. Wave
Propagtion in Lossless and Conducting Media. Conductors & Dielectrics – Characterization,
Wave Propagation in Good Conductors and Good Dielectrics. Polarization. Related Problems.
UNIT - VI
OBJECTIVE
 The change of the path of the wave when it is incident in the surface of the
types of mediums
 Calculations of the reflection and refraction coefficients
 Derivation of the Poynting theorem
 Calculation of the amount of the loss in plane conductor
SYLLABUS
EM Wave Characteristics – II: Reflection and Refraction of Plane Waves – Normal and Oblique
Incidences, for both Perfect Conductor and Perfect Dielectrics, Brewster Angle, Critical Angle and
Total Internal Reflection, Surface Impedance. Poynting Vector and Poynting Theorem –
Applications, Power Loss in a Plane Conductor. Related Problems.
UNIT - VII
OBJECTIVE
 This introduces the various types of Transmission Lines
 According to the dependency of parameters the Transmission Line
equations are derived
 The properties of the waves in TL like velocity, wavelength,wave
impedances are derived
SYLLABUS
Transmission Lines - I : Types, Parameters, Transmission Line Equations, Primary & Secondary
Constants, Expressions for Characteristic Impedance, Propagation Constant, Phase and Group
Velocities, Infinite Line Concepts, Losslessness/Low Loss Characterization, Distortion –
Condition for Distortionlessness and Minimum Attenuation, Loading - Types of Loading. Related
Problems.
UNIT - VIII
OBJECTIVE
 To know the different configurations of Transmission Lines like SC & OC
lines
 To obtain the reflection coefficient,VSWR,UHF Lines
 Smith chart & applications like single and double matchimg
SYLLABUS
Transmission Lines – II : Input Impedance Relations, SC and OC Lines, Reflection Coefficient,
– Impedance Transformations.
Smith Chart – Configuration and Applications, Single and Double Stub Matching. Related
Problems.
(4.2)
SYLLABUS - GATE
UNIT I&II
Elements of vector calculus: divergence and curl; Gauss' and Stokes' theorems
UNIT III
Maxwell's equations: differential and integral forms.
UNIT IV
Wave equation
UNIT V
Poynting vector. Plane waves: propagation through various media; reflection and refraction; phase
and group velocity; skin depth.
UNIT VI
Waveguides: modes in rectangular waveguides; boundary conditions; cut-off frequencies;
dispersion relations. Basics of propagation in dielectric waveguide
UNIT VII
Transmission lines: characteristic impedance; impedance transformation.
UNIT VIII
Smith chart; impedance matching; S parameters, pulse excitation.
(4.3)
SYLLABUS - IES
UNIT I &II
Analysis of electrostatic and magnetostatic fields; Laplace's and Piossons's equations; Boundary
value problems and their solutions
UNIT III
Maxwell's equations; application to wave propagation in bounded and unbounded media
UNIT IV &V
Not applicable
UNIT VI
Basics of wave guides and resonators
UNIT VII &VIII
Transmission lines: basic theory, standing waves, matching applications, misconstrue lines
(5)
SUGGESTED BOOKS
TEXT BOOKS :
1. Elements of Electromagnetic – Matthew N.O. Sadiku, Oxford Univ. Press, 3rd ed., 2001.
2. Electromagnetic Waves and Radiating Systems – E.C. Jordan and K.G. Balmain, PHI, 2nd
Edition, 2000.
REFERENCES :
1. Engineering Electromagnetics – Nathan Ida, Springer (India) Pvt. Ltd., New Delhi, 2nd ed.,
2005.
2. Engineering Electromagnetics – William H. Hayt Jr. and John A. Buck, TMH, 7th ed., 2006.
3. Networks, Lines and Fields – John D. Ryder, PHI, 2nd ed.,1999.
4. Transmission Lines and Networks – Umesh Sinha, Satya Prakashan (Tech. India
Publications), New Delhi, 2001.
5.. Electromagnetic Field Theory and Transmission Lines – G.S.N. Raju, Pearson Edn. Pte.
Ltd., 2005.
(6)
WEBSITES
Do not confine yourself to the list of websites mentioned here alone. Be cognizant and keep
yourself abreast of the others too. The given list is not exhaustive.
1.
www.mit.edu
2.
www.soe.stanford.edu
3.
www.grad.gatech.edu
4.
www.gsas.har ward.edu
5.
www.eng.ufl.edu
6.
www.iitk.ac.in
7.
www.iitd.ernet.in
8.
www.iitb.ac.in
9.
www.iitm.ac.in
10. www.iitr.ac.in
11. www.iitg.ernet.in
12. www.bits-pilani.ac.in
13. www.bitmesra.ac.in
14. www.psgtech.edu
15. www.iisc.ernet.in
16. www.circuit-magic.com
17. www.ieee.org
(7) EXPERT DETAILS
INTERNATIONAL
1. R. R. A. Shamonina, E. Kalinin, V. Solymar, L. Optical and Semiconductor Devices
Group, Electricaland Electronic Engineering (EEE) Department, Imperial College,
Exhibition Road, London SW7 2BT, United Kingdom
NATIONAL
1. Dr. D.Ganesh Rao - Prof. & Head, Deptt. of Telecommunication Engg., M.S. Ramayya Instt. of
Tech., Bangalore
REGIONAL
1. Dr Somashekar Dept of ECE JNTU,HYderabad.
(8)
JOURNALS
INTERNATIONAL
1.
IEEE transactions on electro magnetic fields
2.
IEEE proceedings circuits, devices and systems
3. International journal of field theory and applications
(9)
Lecture
No.
SUBJECT (LESSON) PLAN AND 10)OOPS
Topics as per JNTU
syllabus
Topics to be covered
Unit I
L1,
What is Vector & Scalar?
Suggested
Book
Page No
Teaching
Methods
L2,
L3,
L4
Review of Coordinate
Systems,
Vector Calculus :
Vector Product, Dot product,
Rectangular Coordinate Systems, Spherical
Coordinate System, Cylindrical Coordinate
Systems Relation between them.
T1
P4 -P35
BB
Coulomb’s Law, Electric Field
Intensity – Fields due to
Different Charge Distributions,
Coulomb’s Law, Electric Field Intensity –
Fields due to Different Charge Distributions
T1
L6
Electric Flux Density
Electric Flux Density Problems
T1
P124
BB
L7
Gauss Law and Applications,
Gauss Law and Applications
T1
P126,P128
BB
Electric Potential,
Relations Between E and V,
Maxwell’s Two Equations for
Electrostatic Fields,
Energy Density, Related
Problems
Electric Potential,
Relations Between E and V,
Maxwell’s Two Equations for Electrostatic
Fields,
T1
P135, P141
T1
P141
T1
P148
Related Problems
Related Problems
L5
L8
L9
L10
L11
Energy Density, Related Problems
P106, P113
BB
BB
BB
BB
BB
Unit II
L12
L13,
L14
L15
L16
L17
Convection and Conduction
Currents,
Dielectric Constant, Isotropic
and Homogeneous Dielectrics,
Continuity Equation, Relaxation
Time, Poisson’s and Laplace’s
Equations;
Capacitance – Parallel Plate,
Coaxial, Spherical Capacitors,
T1
P170
Dielectric Constant, Isotropic and
Homogeneous Dielectrics,
T1
P179, P183
Continuity Equation, Relaxation Time,
Poisson’s and Laplace’s Equations;
Capacitance – Parallel Plate, Coaxial,
Spherical Capacitors,
T1
P188, P209
Convection and Conduction Currents,
Related Problems
BB
BB
BB
T1
P43-45
T1
P43-45
BB
T1
P274
BB
T1
P285
T1
P293
BB
Unit III
L 18
L 19
L 20,
L21,
L22
L 23
L24,
L25
L 26
Biot-Savart Law
Ampere’s Circuital Law and
Applications
Magnetic Flux Density,
Maxwell’s Two Equations for
Magnetostatic Fields
Magnetic Scalar and Vector
Potentials
Forces due to Magnetic Fields,
Ampere’s Force Law
Inductances and Magnetic
Energy
Biot-Savart Law
Ampere’s Circuital Law and Applications
Magnetic Flux Density, Maxwell’s Two
Equations for Magnetostatic Fields
Magnetic Scalar and Vector Potentials
Forces due to Magnetic Fields, Ampere’s
Force Law
Inductances
Magnetic Energy
BB
BB
T1
P296
T1
P319
T1
P353
BB
BB
BB
L27
BB
Related Problems
Unit IV
Faraday’s Law
and
L 28
Transformer emf
Inconsistency of
Ampere’s
L 29 Law and Displacement
Current
Density
Maxwell’s Equations
in
L30, L Different Final
Forms
31 and Word
Statements
Conditions at a
Boundary
L32, L Surface: Dielectric-Dielectric
and Dielectric33 Conductor
Interfaces.
L 34
Faraday' s Laws, Transformer
electromagnetic force
T1
P386,388
InconsistencyofAmpere’sLawand
T1
P397
BB
Displacement Current Density
Maxwell’s Equations in Different Forms
&
BB
T1
P400
BB
Statements
Conditions at a Boundary Surface:
T1,R5
P264
Dielectric-Dielectric and
Dielectric-Conductor Interfaces.
BB
BB
Related Problems
Unit V
L 35
Wave Equations for
Wave Equations for Conducting and
Conducting
Perfect
and Perfect Dielectric Media, Dielectric Media,
Uniform Plane Waves
–
Definition, All
L36,L37 Relations
between E & H. Sinusoidal
Variations.
Wave Propagtion in Lossless
and Conducting
L 38, Media.
L39 Conductors & Dielectrics –
L42
Characterization,
Wave Propagation in
Good
Conductors and
Good
Dielectrics.
Polarization. Related
Problems.
L43
Related Problems.
L40,
L41
T1
BB
Uniform Plane Waves – Definition, All
Relations between E & H. Sinusoidal
Variations.
T1
BB
Wave Propagtion in Lossless and
Conducting
Media.
Conductors & Dielectrics –
Characterization,
T1
P441
BB
Wave Propagation in Good Conductors
and
T1
Good Dielectrics.
P444
BB
Polarization. Related Problems.
T1
P179
T1
BB
BB
Unit VI
L44,
L45,
L46
L 47
L 48
L 49
Reflection
and
Refraction of
Plane
–
Waves
Normal
and
Obliq
Reflection and Refraction of Plane Waves
ue
Incidences, for both –
Perfect Conductor and
Normal and Oblique Incidences, for
Perfect
both
Dielectrics
Perfect Conductor and Perfect Dielectrics
Brewster Angle, Critical
Brewster Angle, Critical Angle and
Angle
Total
and Total Internal Reflection Internal Reflection
Surfa
ce
Impedance. Poynting Surface Impedance.
Vecto
r
Poynting Vector
Poynt
Theorem
–
P459,
T1
469
BB
R5
P333
T1, R5
P454
R5
P341
BB
BB
L 50
L 51
ing
Applications
,
Powe
r
Loss in
Condctor.
BB
Poynting Theorem – Applications,
a
Plane
Power Loss in a Plane Conductor.
R2
P413
BB
BB
Related Problems.
Unit VII
L 52
L 53,
L 54
L 55,
L 56
L 57
Types,
Parameters,
Transmission Line Equations
Primary &
Secondary
Constants,
Expressions for
Characteristic
Impedance
Propagation
Constant,
Phase and Group Velocities,
Infinite Line Concepts, Loss
less ness/Low Loss
Characterization,
Distortion
Condition for Distortion less
L 58,
and Minimum Attenuation,
L 59
L 60
Loading - Types of Loading.
Related Problems.
Types, Parameters, Transmission Line
Equations
T1
Primary & Secondary Constants (α, β, γ ),
T1,
P 418,
Expressions for Characteristic Impedance
R5
P425
P502, P505,
BB
BB
Propagation Constant,
Phase and Group Velocities,
Infinite Line Concepts, Loss less
ness/Low
Loss Characterization,
Distortion
Condition for Distortion less and
Minimum
Attenuation,
T1
R5
BB
P426
BB
T1
BB
Loading - Types of Loading.
Related Problems.
T1
BB
Unit VIII
L 61
L 62
Input Impedance Relations,
SC
Input Impedance Relations, SC and OC
and OC Lines
Lines
Reflection Coefficient
Reflection Coefficient
VSWR. UHF Lines as Circuit
L 63,
Elements; λ/4, λ /2, λ /8 Lines –
L 64 Impedance Transformations
L 65, Smith Chart – Configuration
L66 and Applications
L 67, Single and Double Stub
L 68 Matching.
L 69 Related Problems.
VSWR. UHF Lines as Circuit Elements; λ/4,
R4
R5
P433
BB
BB
T1, R5
P512,
P434,435
BB
λ /2, λ /8 Lines – Impedance Transformations
Smith Chart – Configuration and
Applications
R5
P450
Single and Double Stub Matching.
R5
P453,460
BB
BB
R2, R5
BB
Lectu
re No.
JNTUH Topic
Objective of each Topic
Met
hod
of
Teac
hing
Practical
Inferences
Learning Outcome
UNIT – 1 Electrostatics-I
L1,
L2
L3,
L4
Review of
Coordinate.
Systems,
Vector Calculus :
Explanation
of
coordinate system
L5
Coulomb’s Law,
Electric Field
Intensity – Fields due to
Different Charge
Distributions,
L6
L7
L8
L9
Electric Flux Density
Gauss Law and
Applications,
Electric Potential,
Relations Between E
and V,
Maxwell’s Two
Equations for
Electrostatic Fields
L10
Energy Density
L11
Related Problems
A convenient language for expressing
certain
fundamental
ideas
in
electromagnetic.
Useful
determining
calculus
Explanation of coulomb’s
law and different charge
distributions
It deals with the force a point charge
exerts on another point charge.
Electrical power
transmission, Xray machines.
M1
Explanation of Electric flux
density
Knowledge of the flux due to electric
field
Military
applications
M1
Explanation of Gauss law
Determination of the electric field
Point charge,
infinite line
charge
M1
Explanation
Potential
Relationship between E and V
Equipotential
Surface
M1
Waveguides
M1
Military
applications
M1
of
the
Electric
Explanation
of
Maxwell’s Equations
Explanation
density
of
two
Energy
Knowledge
Equations
of
two
Maxwell’s
Knowledge of Energy density
in
M1
M1
UNIT – 2 Electrostatics-II
L15
Convection and
Conduction
Currents,
Dielectric Constant,
Isotropic and
Homogeneous
Dielectrics
Continuity Equation,
Relaxation
Time, Poisson’s and
Laplace’s
Equations;
L16
Capacitance – Parallel
Plate,
Coaxial, Spherical
Capacitors,
Related Problems
L12
L13,
L14
Lectu
re No.
Explanation of Convection
and Conduction
Currents
of Dielectric
Constant,
Isotropic
and
Homogeneous Dielectrics
Explanation
Explanation of Continuity
Equation
Explanation of Capacitors.
Objective of each Topic
JNTUH Topic
Should get knowledge of the
relationship between Convection and
Curent
M1
Materials
M1
Determination of
Mathematics
M1
Conduction Currents
of
Isotropic
Homogeneous Dielectrics.
Knowledge
and
Knowledge of charge conservation
Knowledge of resistance of
conductor of uniform cross section
Learning Outcome
a
Parallel
plate
capacitors
Practical
Inferences
M1
Met
hod
of
Teac
hing
UNIT – 3 Magnetostatics
L18
L19
L20
L21
L22
L23
L24,
L25
L26
Biot-Savart Law
Explanation
savart’s law
Ampere’s Circuital Law
and
Applications
Magnetic Flux Density,
Maxwell’s Two
Equations for
Magneto static Fields
Explanation of Ampere’s
Magnetic Scalar and
Vector
Potentials
Explanation of Magnetic
Scalar
and
Vector
Potentials
Explanation of Forces due to
Forces due to Magnetic
Fields,
Ampere’s Force Law
Inductances and
Magnetic
Energy, Related
Problems
of
Biot
Circuital Law and
Applications
Explanation of Magnetic
Flux Density, Two Maxwell’s
equations
Knowledge of infinite line current
Power flow
Determination of the magnetic field
For a solenoid.
Knowledge of another two magnetic
Maxwell’s equations and
Waveguides
Knowledge on Magnetic Scalar and
Vector Potentials
Rectangular
waveguides
M1
M1
Knowledge of Forces due to Magnetic
Magnetic Fields,
Ampere’s Force Law
Fields,
Ampere’s Force Law .
Military
applications
Explanation of Inductances
Knowledge of Inductances and Magnetic
Military
applications
and Magnetic Energy
Energy
M1
M1
M1
UNIT – 4 Maxwell’s Equations in Time Varying Fields
Explanation of Faraday’s
L27
L28
L29,
L30
L31,
L32
L33
Faraday’s Law and
Transformer emf
Inconsistency of
Ampere’s
Law and Displacement
Current Density
Maxwell’s Equations in
Different Final Forms
and Word Statements
Conditions at a
Boundary
Surface: DielectricDielectric
and DielectricConductor
Interfaces.
Law and
Transformer emf
Knowledge of induced emf
Explanation of Inconsistency
Knowledge of Inconsistency of Ampere’s
of Ampere’s Law and
Displacement
Current Density
Explanation of Maxwell’s
Equations in Different Final
Forms
and Word Statements
electrolysis
M1
Law and Displacement
Current Density
Light and radio
waves
M1
Knowledge of Maxwell’s Equations in
Wave guides
Different Final Forms
and Word Statements
M1
M1
Overview of boundary conditions
DielectricDielectric
Explanation of Boundary
Conditions
M1
Related Problems
UNIT – 5 EM Wave Characteristics-I
L34
L35,
L36
L37,
L38,
Wave Equations for
Conducting
and Perfect Dielectric
Media
Uniform Plane Waves –
Definition, All
Relations between E &
H. Sinusoidal
Variations
Wave Propagtion in
Lossless
and Conducting Media.
Conductors &
Dielectrics –
Explanation of Wave
Knowledge of Wave Equations for
Equations for Conducting
and Perfect Dielectric Media
Conducting
and Perfect Dielectric Media
Wave Equations
M1
Knowledge on Uniform Plane Waves –
Definition,.
Uniform
Waves
M1
&
M6
Explanation of Uniform
Plane Waves – Definition, All
Relations between E & H.
Sinusoidal Variations
Explanation of Wave
Propagtion in Lossless and
Conducting Media.
.
Should able to understand Wave
Propagtion in Lossless and Conducting
Media).
Wave
Plane
Propagtion
application.
M1
&
M4
Characterization,
L39,
L40
Wave Propagation in
Good
Conductors and
Good
Dielectrics.
L41
Polarization. Related
Problems.
Explanation of Wave
Propagation in Good
Conductors and Good
Dielectrics.
Knowledge of Wave Propagation in Good
Conductors and Good Dielectrics..
Wave Propagation
in
Good
Conductors
and
Good Dielectrics.
M1
&
M4
M1
&
M4
Explanation of Polarization
UNIT – 6 EM Wave Characteristics-II
Reflection and
Refraction of
L42,
L43,
L44
Plane waves-Normal
and Oblique
Incidences for both
Perfect conductors
and Perfect
dielectrics
L45
Brewster Angle,
Critical
Angle
and Total Internal
Reflection
L46
Surface Impedance.
Poynting
Vector
Explanation of Oblique
Incidences
Knowledge on Reflection and Refraction
Mirrors.
M1
&
M4
Explanation of Brewster
Knowledge on relation between Brewster Angle,
Angle, Critical Angle
Critical Angle
Angle
modulat
ion.
M1
&
M4
Explanation of Surface
Knowledge on Surface Impedance. Poynting
Poynting
Vector.
M1
&
M4
Used for
wide
range of
speed
calculati
ons and
speed
control.
M1
&
M4
Impedance. Pointing
Vector
L47
Should be able to understand Poynting
theorem.
Poyntig Theorem
Applications,
L48
Vector
Power Loss in a plane
Condctor.
Explanation of Pointing
Theorem
Explanation of Power Loss in
M1
&
M4
a plane
Overview of power loss
UNIT – 7 TRANSMISSION LINES-I
L49
L50,
L51
L52,
L53
L54,
L55
Types, Parameters,
Transmission Line
Equations
Primary & Secondary
Constants, Expressions
For
Characteristic
Impedance
Propagation Constant,
Phase and Group
Velocities,
Infinite Line Concepts,
Loss
less ness/Low Loss
Characterization,
Distortion
Explanation of Types,
Parameters,
Explanation of Primary &
Secondary Constants.
Explanation of Propagation
Constant, Phase and Group
Velocities
Explanation of Infinite Line
Concepts
Knowledge on types and parameters.
Knowledge of that describes the characteristics of
conductive transmission lines.
Knowledge of change undergone by the amplitude
of the wave as it propagates in a given direction
Knowledge of Infinite line concepts
Power
distribut
ion.
M1
Copper
wires
M1
telecom
municat
ion
M1
Transmi
ssion
lines
M1
L56
Condition for Distortion
less
and Minimum
Attenuation,
L57,
L58
Loading - Types of
Loading.
Related Problems.
Explanation of Condition for
Distortion less and Minimum
Attenuation
Explanation of Loadings.
Knowledge of band of fequencies
Transmi
ssion
lines
M1
Knowledge of flow of loadings.
High
transmis
sion
lines.
M1
UNIT – 8 TRANSMISSION LINES-II
L59
Input Impedance
Relations, SC
and OC Lines
Working of single phase
IM.
Knowledge on working of SC and OC
lines
Reflection Coefficient
Explanation of Reflection
Coefficient
Knowledge on reflection coefficient
L60
VSWR. UHF Lines as
Circuit
Explanation of VSWR
L61,
L62
Elements; λ/4, λ /2, λ /8
Lines –
L63,
L64
Impedance
Transformations
Smith Chart –
Configuration
and Applications
L65,
L66
Single and Double Stub
Matching.
Smith Chart – Configuration
Working of Single and
Double Stub Matching
Knowledge on graphical measures.
Knowledge on working and relation
between single and double stub
matching.
M6 : Tutorial
M2 : Demo
M7 : Assignment
M3 : Guest Lecture
M8 : Industry Visit
M4 : Presentation
M9 : Project Based
M5 : Lab/Practical
M10 : OHP
GATE-2010
M1
VSWR.
M1
Waveguides.
M1
Microwave
Engineering.
M1
micristrips.
M1
Knowledge on working and relation
between VSWR.
M1 : Lecture
METHODS OF TEACHING:
Generators.
1. A transmission line has a characteristic impedance of 50 Ω and a resistance of 0.1 Ω /m. if the line is
distortion less, the attenuation constant (in Np/m) is
(A) 500 (B) 5 (C) 0.014 (D) 0.002
2. The electric field component of a time harmonic plane EM wave traveling in a nonmagnetic lossless
dielectric medium has an amplitude of 1 V/m. If the relative permittivity of the medium is 4, the magnitude
of the time-average power density vector (in W/m2) is
(A)1/30π
(B)1/60π
(C)1/120π
(D)1/240π
3.
(A) 0
(B) 2√3
(C) 1
(D) 2√ 3
4. A transmission line has a characteristic impedance of 50 Ω and a resistance of 0.1 Ω /m. if the line is
distortion less, the attenuation constant (in Np/m) is
(A) 500 (B) 5 (C) 0.014 (D) 0.002
5. The electric field component of a time harmonic plane EM wave traveling in a nonmagnetic lossless
dielectric medium has an amplitude of 1 V/m. If the relative permittivity of the medium is 4, the magnitude
of the time-average power density vector (in W/m2) is
(A) 1∕30π
(B) 1∕60π
(C) 1∕120π
(D) 1∕240π
5. In the circuit shown, all the transmission line sections are lossless. The Voltage Standing Wave Ration
(VSWR) on the 60W line is
(A) 1.00 (B) 1.64 (C) 2.50 (D) 3.00
GATE-2008
6. For static electric and magnetic fields in an in homogeneous source free medium, which of the following
represents the correct form of two of Maxwell’s equations?
7.A Rectangular wave guide of internal dimensions (a=4cm and b=3cm) is to be operated in TE11 mode.
The minimum operating frequency is
a)6.25 GHz
b) 6.0 GHz
c) 5.0 GHz
d) 3.75GHz
8. One end of a loss-less transmission line having the characteristic impedance of 75Ω and length of a cm is
short-circuited. At 3 GHz, The input impedance at the other end of the transmission line is
a)0
b)Resistive
c)Capacitive
d) Inductive
9.A uniform plane wave in the free space is normally incident on an infinitely thick dielectric
slab(dielectric constant ε=9). The magnitude of the reflection coefficient is
a)0
b)0.3
c)0.5
d)0.8
GATE 2007
10. A plane wave of wavelength λ is travelling in a direction making an angle 30 degrees with positive xaxis and 90 d with positive y-axis. The E field of the plane wave can be represented as (Eo is a constant)
11.If C is a closd curve enclosing a surface S, then the magnetic field intensity H, The current density j and
the electric flux density D are related by
12.The E field in a rectangular wave guide of inner dimensions a͞ x b is given by
Where Ho is a constant, and a and b are the dimentions along the x-axis and they-axis respectively. The
mode of propagation in the wave guide is
a)TE20
b)TM11
c)TM20
d)TE10
13. A load of 50 Ω is connected in shunt in a 2-wire transmission line of Zo=50Ω as shown in the figure.
The 2-port scattering parameter matrix(S-matrix) of the shunt element is.
14. The parallel branches of a two wire transmission line are terminated in 100 Ω and 200 Ω resistors as
shown in the figure. The characteristic impedance of the line is Zo =50 Ω and each section has a length of
λo /2 . The voltage reflection coefficient γ at the input is
(10)QUESTION BANK
UNIT-I
1.
Derive the expression for Curl of a Vector in Cartesian, Cylindrical and Spherical
Co-Ordinate system.
2.
(a) Define the “poisson's" and “Laplace's" equation.
(b) Obtain expression for the capacitance of
i. a parallel plate capacitor and
ii. a coaxial capacitor.
3. State Coulomb’s law of force between any two point charges,
and indicate the units of the quantities
in the force equation
b) Point charger 6 nc and – 3 nc are located at (3,2,-1) and (-1,-1,4) respectively
i) Determine the force on a 1nc point charge located at (0,3,1)
ii) Find the electric field intensity at that point
4. a) Define Gauss’ law. Apply Gauss law to derive the boundary
Conditions at a conductor-dielectric interface
b) Derive an expression for the capacitance of a parallel plate
Capacitors containing two dielectrics with the dielectric interface parallel to the
conducting
plates.
5.
6.
7.
a) What are the different types of charge distributions and give
an example for each one?
at (2,2,0)
What is the limitation of Coulomb’s law?
State and prove the Uniqueness theorem
8. Define electric potential and obtain expression for electric potential due to npoint charges.
b) Find electric flux density at (0, 4, 3) when a point charge of
30nC is located at the origin and plane y=3 carries charge 10nc/m2.
9.
a) Define electric field intensity at a point. Derive the expression for E of a line
charge.
b) An infinitely long uniform line charge is located at y=3, z=5 of
PL=30nc/m. Find ‘E’ at the origin.
10. a) Derive Possion’s and Laplace’s equations from fundamentals.
b) An infinitely long uniform line charge is located at y = 3, z = 5. If PL = 30 n
c/m, find field intensity at E
i) origion ii) P (5, 6, 1).
11. a) Define electric potential and obtain expression for electric potential due to npoint charges.
b) Find electric flux density at (0,4,3) when a point charge of 30nC is located at
the origin and plane y=3 carries charge 10nc/m2.
12. a) Define electric field intensity at a point. Derive the expression for E of a line
charge.
b) An infinitely long uniform line charge is located at y=3, z=5 of
PL=30nc/m. Find ‘E’ at the origin.
13. Derive Possion’s and Laplace’s equations from fundamentals.
UNIT-II
1. a) Derive magnetic field equation due to infinitely long current element.
b) What is the current density which produces a magnetic field of H = 28 sin ay
c) State and explain Lorentz’s force equation.
2. a) State and explain Amphere’s circuital law.
3. Define the magnetic vector potential and show that
4. a) State Biot-Savart’s law. Find H at the centre of a square current loop of side
‘L’.
b) Derive the expression for the energy stored in a magnetic field.
5. Obtain the boundary conditions at the boundary of two dielectric materials
6. Give the classification of magnetic materials and their characteristics
7. State and prove Boundary Conditions for electric Field between a conductor and a dielectric.
UNIT-III
1. a) State Maxwell’s equations in differential form and write down their word statements
b) If the electric field strength, E of an electromagnetic wave in free space is given by
E = 8 sin (wt- z) a y v /m . Find the magnetic field H
2.
a) What is polarization of an EM wave? Explain different types of polarizations
3. a) State and prove poynting theorem
b) Define depth of penetration and show that depth of penetration = 1/attenuation constant
4. Express Maxwell’s equations in phasor form
5. Discuss about inconsistency of Ampere’s law and displacement current density
6. Express Maxwell’s equations in dielectric medium in integral forms along with
word statements.
7. Derive the expression for continuity of current equation.
8. Explain magnetic boundary conditions.
9.Explain the action of transformer and capacitor in terms of static and time varying
FIelds. Give examples.
10. Show that the displacement current in the dielectric of parallel-plate capacitor
is equal to the conduction
current in its leads
11. Define depth of penetration.
12. Show that poynting vector P = E x H represents power flow for unit area.
UNIT-IV
1. Prove that under the condition of no reflection at an interface, the sum of the Brewster angle and the
angle of refraction is
/2 for parallel polarization for the case of reflection by a perfect conductor under
oblique incident, with neat sketches.
2.
3. Prove that uniform plane wave does not have field components in the direction of the propagation.
4. Determine the intrinsic impedance of free space. (Set No. 2 Apr/May 2008 Supply)
5. What is polarization of an EM wave? Distinguish between different types of polarizations? Prove that the
polarization is circular when the two components of electric field are equal and are 90 apart.
6. A plane EM wave is normally incident on the boundary between two di- electrics. What must be the ratio
of refractive indices of the two media in order that the reflected and transmitted waves may have average
Power of equal magnitude? (Set No. 3 Apr/May 2008 Supply)
7. Derive the expression for attenuation and phase constants of uniform plane wave.
8. If _r = 9, μ = μ0 for the medium in which a wave with frequency f = 0.3 GHz is propagating, determine
propagation constant and intrinsic impedance of the medium when
i. _ = 0 and
ii. _ = 10 mho/m. (Set No. 4 Apr/May 2008 Supply)
9. For good dielectrics derive the expressions for , _, and _.
10. Find , _, and _. for Ferrite at 10GHz ∈ r = 9, μr = 4, _ = 10ms/m.
11. For a conducting medium derive expressions for and_. (Set No. 1 Apr/May 2008 Reg)
12. Determine the phase velocity of propagation, attenuation constant, phase con- stant and intrinsic
impedance for a
forward travelling wave in a large block of copper at 1 MHz (_ = 5.8 × 107, ∈ r = μr = 1) determine the
distance that the wave must travel to be attenuated by a factor of 100 (40 dB)
13. A plane sinusoidal electromagnetic wave travelling in space has Emax = 1500μv/m i. Find the
accompanying Hmax
ii. The average power transmitted
14. The electric field intensity associated with a plane wave travelling in a perfect dielectric medium is
given by Ex (z, t)
= 10 cos (2
t - 0.1
x 10 7
z)v/m
i. What is the velocity of propagation
ii. Write down an expression for the magnetic field intesity associated with the wave if μ = μ0
15. A large copper conductor (_ = 5.8 × 10 7
s/m, _r = μr = 1)support a uniform plane wave at 60 Hz. Determine the ratio of conduction current to
displace- ment current compute the attenuation constant. Propagation constant, in- trinsic impedance, wave
length and phase velocity of propagation.
16. A 3 GHz uniform plane wave propagates through rexolite in the positive Z-direction the E-field at Z = 0
is 100 6 00v/m
17. Calculate the RMS value and phase of E at Z=4 cm (Set No. 1 Apr/May 2008 Reg)
18. Calculate the total attenuation in dB over a distance of 6 wave lengths. For rexolite 2r=2.54 and tan
_=0.0005
UNIT-V
1. Define uniform plane wave. (Set No. 1 Apr/May 2008 Supply)
2. Define and distinguish between the terms perpendicular polarization, parallel polarization, for the case of
reflection by a perfect conductor under oblique incidence.
3. A plane wave of frequency 2MHz is incident upon a copper conductor normally. The wave has an
electric field amplitude of E= 2mV/m. The copper has _r = 1, μr = 1 and _ = 5.8 × 107 mho/m. Find out
average power density absorbed by the copper. (Set No. 1 Aug/Sep 2008 Supply)
4. A plane wave traveling in a medium of _r = 1, μr = 1 has an electric field intensity of 100×p
.
Determine the energy density in the magnetic field and also the total energy density. (Set No. 3 Aug/Sep
2008 Supply)
5. A uniform plane wave is normally incident from air on a perfect conductor. Determine the resulting E
and H fields. Sketch their variations. (Set No. 4 Aug/Sep 2008 Supply)
6. A plane EM wave is normally incident on the boundary between two dielectrics. What must be the ratio
of the refractive indices of the two media in order that the reflected and transmitted waves may have equal
magnitudes of average power (Set No. 4 Aug/Sep 2008 Supply)
7. Explain wave propagation in a conducting medium. (Set No. 1 Apr/May 2008 Reg)
UNIT-VI
1. Define and differentiate between the terms: Instantaneous average and complex poynting vectors, giving
their mathematical expressions. ( Set No. 1 Apr/May 2008 Supply)
2. State and Prove Poynting Theorem. ( Set No. 2, 3 Apr/May 2008 Supply)
3. Derive expression for Reflection and Transmission coefficients of an EM wave when it is incident
normally on a dielectric. ( Set No. 4 Apr/May 2008 Supply)
4. For an incident wave under oblique incident from medium of _1 to medium of _2with parallel
polarization ( Set No. 4 Apr/May 2008 Supply)
5. Explain the significances of Poynting theorem and Poynting vector. (Set No. 2 Aug/Sep 2008 )
6. A Plane wave traveling in a free space has an average poynting vector of 5 watts/m2. Find the average
energy density. ( Set No. 2, 3 Apr/May 2008 Supply)
7. Plot _C and _Br versus the ratio of _1/_2
8. Write short notes on the following
(a) Surface Impedance (b) Brewster angle (c) Total Internal Reflection
9. Explain the difference between the Intrinsic Impedance and the Surface Impedance of a conductor. Show
that for a good conductor, the surface impedance is equal to the intrinsic impedance.
10. Define surface impedance and explain how it exists. (Set No. 4 Apr/May 2008 Supply)
11. Define and establish the relations for the critical angle _C and Brewster angle _Br for non-magnetic
media with neat sketches.
12. Define Complex Poynting vector and explain how to obtain an average power. (Set No. 1 Aug/Sep 13.
Prove that under the condition of no reflection at an interface, the sum of the Brewster angle and the angle
of refraction is 90 degrees for parallel polarization for the case of reflection by a perfect conductor under
oblique incidence, with neat sketches. (Set No. 2 Aug/Sep 2008 Supply)
UNIT-VII
1. Derive a relation between reflection coefficient and characteristic impedance. (Set No. 1 Apr/May 2. 2.
Determine the reflection coefficients when (Set No. 1 Apr/May 2008 Supply)
i. ZL = Z0
ii. ZL = short circuit
iii. ZL = open circuit.
iv. Also find out the magnitude of reflection coefficient when ZL is purely reactive.
3. List out types of transmission lines and draw their schematic diagrams. (Set No. 2 Apr/May 2008 4. 4.
Draw the directions of electric and magnetic fields in parallel plate and coaxial lines.
5. A transmission line in which no distortion is present has the following parameters Z0= 50_, = 20mNP/m,
_= 0.6_0. Determine R, L, G, C and wavelength at 0.1 GHz. (Set No. 2 Apr/May 2008 6. List out types of
transmission lines and draw their schematic diagrams. (Set No. 3 Apr/May 2008 7. Draw the directions of
electric and magnetic fields in parallel plate and coaxial lines.
8. A transmission line in which no distortion is present has the following parameters Z0= 50_, = 20mNP/m,
_= 0.6_0. Determine R, L, G, C and wavelength at 0.1 GHz. (Set No. 3 Apr/May
9. What are the salient aspects of primary constants of a two wire transmission line
10. A lossless transmission line used in a TV receiver has a capacitance of 50 PF/m and an inductance of
200 nH/m. Find out the characteristic impedance for 10 meter long section of the line and 500 meter
section.
11. Explain the different types of transmission lines. What are limitations to the maximum power that they
can handle
12. A coaxial limes with an outer diameter of 8 mm has 50 ohm characteristic impedance. If the dielectric
constant of the insulation is 1.60, calculate the inner diameter.
13. Describe the losses in transmission lines (Set No. 1 Apr/May 2008 Reg.) (Set No. 1 Aug/Sep 2008 14.
Definite following terms and explain their physical significance.
i. Attenuation function
ii. Characteristic impedance
iii. Phase function, and
iv. Phase velocity as applied to a transmission line. (Set No. 2 Apr/May 2008 Reg.)
15. At 8 MHz the characteristic impedance of transmission line is (40-j2) _ and the propagation constant is
(0.01+j0.18 ) per meter. Find the primary constants. (Set No. 2 Apr/May 2008 Reg.)
16. Define the following
i. Infinite line
ii. Insertion loss
iii. Lossy and loss less lines
iv. Phase and group velocities (Set No. 3 Apr/May 2008 Reg.)
17. Derive the characteristic impedance of a transmission line in terms of its line constants
18. Explain the meaning of the terms characteristic impedance and propagation constant of a uniform
transmission line and obtain the expressions for them in terms of Parameters of line?
19. A telephone wire 20 km long has the following constants per loop km resistance 90 _, capacitance
0.062 μF , inductance 0.001H and leakage = 1.5 x 10 −6 mhos. The line is terminated in its characteristic
impedance and a potential difference of 2.1 V having a frequency of 1000 Hz is applied at the sending end.
Calculate :
i . The characteristic impedance
ii. Wavelength
iii. The velocity of propagation (Set No. 4 Apr/May 2008 Reg.)
19. Sketch the voltage and current distribution along matched, open and short circuited transmission lines.
20. A line 10 km long has the following line constants: Z0= 600 |0 0 = 0.1neper/km _= 0.05radians/km
Find the received current and voltage when 200 mA are sent down into one end, and the receiving end is
shorted.
21. Define the i/p impedance of a transmission line and derive the expression for it.
22. The characteristic impedance of a certain line is 710 |140 and _ = 0.007 + j0.028 per km. The line is
terminated in a 300Ohm resistor. Calculate the i/p impedance of the line if its length is 100 km.
23. Show that for any uniform transmission line the following relations are valid. Z0 = (Zoc.Zsc)1/2
TanhP1 = (Zsc/Zoc)1/2 What will be their modifications for loss less lines? (Set No. 3 Aug/Sep 2008
Supply)
24. Short-circuited and open ?circuited measurements at frequency of 5000 Hz on a line length 100 km
yields the following results:
Zoc = 570? − 480
Zsc = 720, 340
25. Find the characteristic impedance and propagation constant of the line. (Set No. 3 Aug/Sep 2008 2. 26.
List out types of transmission lines and draw their schematic diagrams. (Set No. 4 Aug/Sep 2008 26. Draw
the directions of electric and magnetic fields in parallel plate and coaxial lines.
27. A transmission lines in which no distortion is present has the following parameters Z0 = 50 , = 20
mNP/m = 0.60. Determine R, L, G, C and wavelength at 0.2 GHz (Set No. 4 Aug/Sep 2008 Supply)
UNIT VIII
1. An EM wave of 3 W/m
2 . Power density is incident normally from air on a perfect dielectric boundary. If the resulting
VSWR is 2.2, find the reflected and transmitted powers. ( Set No. 1 Apr/May 2008 Supply)
2. Explain how UHF lines can be treated as circuit elements, giving the necessary equivalent circuits.
3. A loss less line of 100 _ is terminated by a load which produces SWR = 3. The first Maxima is found to
be occurring at 320 cm. If f = 300 MHz, determine load impedance. (Set No. 1Apr/May 2008 Supply)
Draw the equivalent circuits of a transmission lines when
i. length of the transmission line, 1 <_/4, with shorted load
ii. when 1 <_/4, with open end
iii. 1 =_/4.
4. Find out VSWR if
i. Z0 = 100 _, RL = 80 _
ii. when Z0 = 80 _, RL = 100_ (Set No. 2, 3 Apr/May 2008 Supply)
5. Draw the equivalent circuits of a transmission lines when
i. length of the transmission line, 1 <_/4, with shorted load
ii. when 1 <_/4, with open end
iii. 1 =_/4. (Set No. 3 Apr/May 2008 Supply)
6. Explain the principle of Impedance matching with Quarter wave Transformer?
7. A 100 _ loss less line connects a signal of 100 KHz to a load of 140 _. The load power is 100mW .
Calculate i. Voltage Reflection coefficient, ii. VSWR, iii. Position of VMax , IM ax VMin and IMin
8. Define the reflection coefficient and derive the expression for i/p impedance in terms of reflection
coefficient.
9. Explain how the i/p impedance varies with the frequency with sketches.
10. Explain the significance and Utility of _/8, _/4, and _/2 Line. (Set No. 2 Apr/May 2008 Reg.)
11. A low transmission line of 100 _ characteristic impedance is connected to a load of 400 _. Calculate the
reflection coefficient and standing wave ratio. Derive the Relationships used.
12. Explain the significance of Vmax andVmin positions along the transmission line, for a complex load
ZR Hence calculate the impedances at these positions. (Set No. 3 Apr/May 2008 Reg.)
13. An aerial of (200-j300) _ is to be matched with 500 _ lines. The matching is to be done by means of
low loss 600_ stub line. Find the position and length of the stub line used if the operating wave length is 20
meters.
14. Describe all the characteristics of UHF Lines? (Set No. 4 Apr/May 2008 Reg.)
15. Explain the significance and design of single stub impedance Matching .Discuss the factors on which
stub length depends.
16. Point out salient features of r and x-circles in a Smith chart. (Set No. 3 Aug/Sep 2007 Supply)
17. Find out the input impedance of a 75 lossless transmission line of length (0.1_) if it is terminated in
open circuit.
18. Explain clearly why the short circuited stubs are preferred over to a open circuited stubs?
19. Derive the expression for the input impedance of a loss-less line Hence evaluate Zsc and Zoc and
sketch their variation with line length (Set No. 4 Aug/Sep 2007 Supply)
20. Describe the formation of smith chart. Explain clearly how the Smith charts are useful to calculate
transmission line parameters. (Set No. 2 Aug/Sep 2007 Supply)
21. The reflection coefficient at load is 0.5 |30 0 . The characteristic impedance is 100 . At 200MHz,
calculate
i. The position of Vmin nearest to the load.
ii. The ratio of voltage to current at the load.
iii. The value of the load, and VSWR. (Set No. 2 Aug/Sep 2007 Supply)
22. Give a neat sketch for a smith chart and explain clearly, step by step how would you use this chart to
i. Calculate the complex reflection coefficient.
ii. Transfer impedance from one point to other along the line.
iii. Determine the length and location of a short circuited stub line (Set No. 1 Aug/Sep 2007 Supply)
23. Discuss the merits and demerits of stub matching techniques. (Set No. 1 Aug/Sep 2007 Supply)
24. Explain the method of determining the input impedance of line using Smith chart, for a loss less Line of
length L , at any frequency f, for a complex load of ZR. (Set No. 4 Aug/Sep 2008 Supply)
25. A loss less Line of 300 is terminated by a load of ZR. If the VSWR at 200MHz is 4.48, and the first
Vmin is located at 6 cm from the load. Calculate the reflection coefficient and ZR. (Set No. 4 Aug/Sep 26.
Explain clearly why the short circuited stubs are preferred over to a open circuited stubs?
27. Derive the expression for the input impedance of a loss-less line. Hence evaluate ZSC and ZOC and
sketch their variation with line length (Set No. 3 Aug/Sep 2008 Supply)
28. Explain what is meant by voltage reflection coefficient in a transmission line The voltage reflection
coefficient due to load connected to a lossless transmission line of characteristic impedance 100 and
working at 3 GHz is 0.5, 450. Assuming the load voltage to be 10 V, calculate the r.m.s voltage and current
at intervals of one fourth wave length from the load up to a distance 5 cm.
29. A 75 line is terminated by a load of 120 + j80. Find the maximum and minimum impedances on the
line.
(11) TUTORIAL QUESTIONS
UNIT-I
SET-1
1. State the Coulomb’s law in SI units and indicate the parameters used in the equations with the aid of a
diagram.
2. Point charges Q1 and Q2 are respectively located at (4, 0, -3) and (2, 0, 1). If Q2 = 4 nC, find Q1 such
that.
i. The E at (5, 0, 6) has no Z-component.
ii. The force on a test charge at (5, 0, 6) has no X-component.
3. A charge Q1 is at point (0,-1,0)m. Another charge Q2 is at the point (0,2,0)m. Find the ratio Q2=Q1
resulting in zero force
on a test charge at the origin. Q1;Q2 and the test charge are all of the same sign. (RR May 2010)
4. State Gauss’s law. Using divergence theorem and Gauss’s law, relate the displacement density D to the
volume charge density __. (Set No. 2 Apr/May 2008 Supply)
5. A sphere of radius “a” is filled with a uniform charge density of ‘_v ’ c/m
SET-II
6. Derive the boundary conditions for the tangential and normal components of Electrostatic fields at the
boundary between two perfect dielectrics. (Set No. 3 Apr/May 2008 Supply)
7. x-z-plane is a boundary between two dielectrics. Region y < 0 contains dielectric material _r1 = 2.5
while region y > 0 has dielectric with _r2 = 4.0. If E = −30ax +50ay +70az v/m, find normal and tangential
components of the E field on both sides of the boundary. (Set No. 3 Apr/May 2008 Supply)
8. Explain the following terms:
i. Homogeneous and isotropic medium and
ii. Line, surface and volume charge distributions. (Set No. 4 Apr/May 2008 Supply)
9. A circular ring of radius ‘a’ carries uniform charge _L C/m and is in xy-plane. Find the Electric Field at
Point (0, 0, 2) along its axis. (Set No. 4 Apr/May 2008 Supply)
10. State and Prove Gauss’s law. List the limitations of Gauss’s law. (Set No. 3 Aug/Sep 2008 Supply)
11. Derive an expression for the electric field strength due to a circular ring of radius ‘a’ and uniform
charge density, _L C/m, using Gauss’s law. Obtain the value of height ‘h’ along z-axis at which the net
electric field becomes zero.
Assume the ring to be placed in x-y plane. (Set No. 1 Apr/May 2008
12. Define Electric potential. (Set No. 3 Aug/Sep 2008 Supply)
SET-III
13. State and prove Gauss’s law. Express Gauss’s law in both integral and differential forms.
14. Discuss the salient features and limitations of Gauss’s law. (Set No. 2 Apr/May 2008 Reg.)
15. Define conductivity of a material. (Set No. 3 Apr/May 2008
16. Apply Gauss’s law to derive the boundary conditions at a conductor-dielectric interface. (Set No. 3 17.
In a cylindrical conductor of radius 2mm, the current density varies with distance from the axis according
to J = 103e−400r A/m2. Find the total current I. (Set No. 3 Apr/May 2008
18. Using Gauss’s law derive expressions for electric field intensity and electric flux density due to an
infinite sheet of conductor of charge density _ C/cm (Set No. 4 Apr/May 2008
SET-IV
19. A parallel plate capacitance has 500mm side plates of square shape separated by 10mm distance. A
sulphur slab of 6mm thickness with ∈ r = 4 is kept on the lower plate find the capacitance of the setup. If a
voltage of 100 volts is applied across the capacitor, calculate the voltages at both the regions of the
capacitor between the plates.
20. In a cylindrical conductor of radius 2mm, the current density varies with distance from the axis
according to J =103e−400rA/m2. Find the total current I. (Set No. 1 Aug / Sep 2 0 0 8 Supply)
21. Apply Gauss’s law to derive the boundary conditions at a conductor-dielectric interface. (Set No. 4 22.
In a cylindrical conductor of radius 2mm, the current density varies
UNIT-II
SET-1
1. Derive Poisson’s and Laplace’s equations starting from Gauss’s law
2. An infinitely long straight conducting rod of radius ‘a’ carries a current of I in +Z direction. Using
Ampere’s Circuital Law, find H in all regions and sketch the variation of H as a function of radial distance.
If I = 3 mA. and a = 2 cm., find H and _ at ( 0, 1cm., 0) and (0, 4cm., 0). (Set No. 1 Apr/May 3. Define
Ampere’s Force Law and establish the associated relations. (Set No. 2 Apr/May 2008 4. A long coaxial
cable has an inner conductor carrying a current of 1 mA. Along Z direction , its axis coinciding with Zaxis.
Its inner conductor diameter is 6 mm. If its outer conductor has an inside diameter of 12 mm. and a
thicknessof 2 mm., determine H at (0, 0, 0), (0, 1.5 mm, 0), (0, 4.5 mm, 0) and (0, 1cm, 0). (No derivations)
5. Find the field at the centre of a circular loop of radius ‘a’, carrying a current I along _ in z = 0 plane.
SET-II
6. Determine the magnetic flux , for the surface described by
i. _ = 1m., 0 _ _ _ ._/2, 0 _ z _ 2m.,
ii. a sphere of radius 2 m., if the magnetic field is of the form
7. A conducting plane at y = 1 carries a surface current of 10 Z b mA/m. Find H and B at (0, 0, 0) and at (2,
2, 2).
8. State Maxwell’s equations for magneto static fields. (Set No. 1 Apr/May 2008
9. Show that the magnetic field due to a finite current element along Z axis at a point P, ‘r’ distance away
along yaxis is given by H = (I /4
r)(sin 1 − sin 2).b a_ where I is the current through the conductor , 1
and 2 are the angles made by the tips of the conductor element at P?. (Set No. 1 Apr/May 10. State
Ampere’s circuital law. Specify the conditions to be met for determining magnetic field strength, H, based
on Ampere’s circuital law (Set No. 2 Apr/May 2008 Reg)
11. A long straight conductor with radius ‘a’ has a magnetic field strength H = (I r/2
) aˆ_ within the conductor(r < a) and H = (I /2
a2
r) aˆ_ outside the conductor (r > a) Find the current
density J in both the regions (r< a and r > a (Set No. 2 Apr/May 2008 Reg)
12. Define Magnetic flux density and vector magnetic potential. (Set No. 2 Apr/May 2008 Reg)
13. Derive equation of continuity for static magnetic fields.(Set No. 3 Apr/May 2008 Reg)
SET-III
14. Derive an expression for magnetic field strength, H, due to a current carrying conductor of finite length
placed along
the y- axis, at a point P in x-z plane and ‘r’ distant from the origin. Hence deduce expressions for H due to
semiinfinite length of the conductor. (Set No. 2 Apr/May 2008 Reg)
15. A long straight conductor with radius ‘a’ has a magnetic field strength H = (Ir/2
conductor (r < a) and H = (I/2
a2) ˆa_ within the
r) ˆa_ outside the conductor (r > a) Find the current density J in both the
regions (r < and r > a)
SET-IV
16. State Ampere’s circuital law. Specify the conditions to be met for determining magnetic field strength,
H, based on Ampere’s circuital law (Set No. 1 Aug/Sep 2007 Supply)
17. State Biot- Savart law (Set No. 4 Aug/Sep 2007 Supply)
18. Derive an expression for magnetic field strength, H, due to a finite filamentary conductor carrying a
curent I and placed along Z- axis at a point ‘P’ on y- axis. Hence deduce the magnetic field strength for the
length of the conductor extending from - 1 to + 1. (Set No. 4 Aug/Sep 2007 Supply)
19. Obtain an expression for differential magnetic field strength dH due to differential current element I dl
at the origin in the positive Z- direction. (Set No. 2, 3 Aug/Sep 2007 Supply)
20. Find the magnetic field strength, H at the centre of a square conducting loop of side ‘2a’ in Z=0 plane if
the loop is carrying a current, I, in anti clock wise direction. (Set No. 2, 3 Aug/Sep 2007
UNIT-III
SET-1
1. In free space D = Dm Sin (wt +_ z)ax. Determine B and displacement current density.
2. Region 1, for which μr1 = 3 is defined by X < 0 and region 2, X < 0 has μr2 = 5 given H1 = 4 ax + 3ay 6
az (A/m). Determine H2 for X > 0 and the angles that H1 and H2 make with the interface.
3. In a perfect dielectric medium, the EM wave has maximum value for E of 10 V/m with μr = 1 and _r = 4.
Find the velocity of the wave, peak poynting vector, average poynting vector, impedance of the medium
and peak value of the magnetic field (Set No. 2 Apr/May 2008 Supply)
4. What is the inconsistency in Ampere’s Law? How it is rectified by Maxwell?
5. Show that the total displacement current between the condenser plates con- nected to an alternating
voltage sources is exactly the same as the value of charging current (conduction current).
SET-II
6. In a perfect dielectric medium, the EM wave has maximum value for E of 10V/m with μr = 1 and _r = 4.
Find the velocity of the wave, peak poynting vector, average poynting vector, impedance of the medium
and peak value of the magnetic field. (Set No. 3 Apr/May 2008 Supply)
7. What is the inconsistency in Ampere’s Law? How it is rectified by Maxwell?
8. Show that the total displacement current between the condenser plates connected to an alternating
voltage sources is exactly the same as the value of charging current (conduction current). (Set No. 4
9. Derive Maxwell’s equations in integral form and differential form for time varying fields.
10. Explain how the concept of Displacement current was introduced by Maxwell to account for the
production of Magnetic fields in the empty space. (Set No. 4 Apr/May 2008 Supply)
SET-III
11. The electric field intensity in the region 0 < x < 5, 0 < y < /12, 0 < z < 0.06m in free space is given by
E=c sin12y sin az cos2 × 10 t ax v/m. Beginning with the ∇xE relationship, use Maxwell’s equations to find
a numerical value for a , if it is known that a is greater than’0’. ( Set No. 1 Apr/May
12. Write down the Maxwell’s equations for Harmonically varying fields.(b) A certain material has _ =
0and ∈R = 1if H = 4sin(106t − 0.01z)ay A/m. make use of Maxwell’s equations to find μr
13. In figure 3 let B=0-2cos 120 t T, and assume that the conductor joining the two ends of the resistor is
perfect. It may be assumed that the magnetic field produced by I(t) is negligible find
(a) Vab (t)
(b) I(t) ( Set No. 2 Apr/May 2008 Regular)
14. What is the inconsistency of Amperes law?
SET-IV
15. A circular loop conductor of radius 0.1m lies in the z=0plane and has a resistance of 5_ given B=0.20
sin 10 3taz T. Determine the current ( Set No. 3 Apr/May 2008 Regular)
16. Derive the equation of continuity for time varying fields ( Set No. 3 Apr/May 2008 Regular)
17. A Parallel plate capacitor with a plate area of 5cm2 and plate separation of 3mm has a voltage 50 Sin
103t V applied to its plates. Calculate the displacement current assuming 2= 2 20
UNIT-IV
SET-1
1. Prove that under the condition of no reflection at an interface, the sum of the Brewster angle and the
angle of refraction is
/2 for parallel polarization for the case of reflection by a perfect conductor under
oblique incident, with neat sketches.
2.
3. Prove that uniform plane wave does not have field components in the direction of the propagation.
4. Determine the intrinsic impedance of free space. (Set No. 2 Apr/May 2008 Supply)
5. What is polarization of an EM wave? Distinguish between different types of polarizations? Prove that the
polarization is circular when the two components of electric field are equal and are 90 apart.
6. A plane EM wave is normally incident on the boundary between two di- electrics. What must be the ratio
of refractive indices of the two media in order that the reflected and transmitted waves may have average
Power of equal magnitude? (Set No. 3 Apr/May 2008 Supply)
7. Derive the expression for attenuation and phase constants of uniform plane wave.
8. If _r = 9, μ = μ0 for the medium in which a wave with frequency f = 0.3 GHz is propagating, determine
propagation constant and intrinsic impedance of the medium when
i. _ = 0 and
ii. _ = 10 mho/m. (Set No. 4 Apr/May 2008 Supply)
9. For good dielectrics derive the expressions for , _, and _.
10. Find , _, and _. for Ferrite at 10GHz ∈ r = 9, μr = 4, _ = 10ms/m.
11. For a conducting medium derive expressions for and_. (Set No. 1 Apr/May 2008 Reg)
SET-II
12. Determine the phase velocity of propagation, attenuation constant, phase con- stant and intrinsic
impedance for a
forward travelling wave in a large block of copper at 1 MHz (_ = 5.8 × 107, ∈ r = μr = 1) determine the
distance that the wave must travel to be attenuated by a factor of 100 (40 dB)
13. A plane sinusoidal electromagnetic wave travelling in space has Emax = 1500μv/m i. Find the
accompanying Hmax
ii. The average power transmitted
14. The electric field intensity associated with a plane wave travelling in a perfect dielectric medium is
given by Ex (z, t)
= 10 cos (2
t - 0.1
x 10 7
z)v/m
i. What is the velocity of propagation
ii. Write down an expression for the magnetic field intesity associated with the wave if μ = μ0
15. A large copper conductor (_ = 5.8 × 10 7
s/m, _r = μr = 1)support a uniform plane wave at 60 Hz. Determine the ratio of conduction current to
displace- ment current compute the attenuation constant. Propagation constant, in- trinsic impedance, wave
length and phase velocity of propagation.
16. A 3 GHz uniform plane wave propagates through rexolite in the positive Z-direction the E-field at Z = 0
is 100 6 00v/m
17. Calculate the RMS value and phase of E at Z=4 cm (Set No. 1 Apr/May 2008 Reg)
18. Calculate the total attenuation in dB over a distance of 6 wave lengths. For rexolite 2r=2.54 and tan
_=0.0005
UNIT-V
SET-1
1. Define uniform plane wave. (Set No. 1 Apr/May 2008 Supply)
2. Define and distinguish between the terms perpendicular polarization, parallel polarization, for the case of
reflection by a perfect conductor under oblique incidence.
3. A plane wave of frequency 2MHz is incident upon a copper conductor normally. The wave has an
electric field amplitude of E= 2mV/m. The copper has _r = 1, μr = 1 and _ = 5.8 × 107 mho/m. Find out
average power density absorbed by the copper. (Set No. 1 Aug/Sep 2008 Supply)
4. A plane wave traveling in a medium of _r = 1, μr = 1 has an electric field intensity of 100×p
.
Determine the energy density in the magnetic field and also the total energy density.
SET-II
5. A uniform plane wave is normally incident from air on a perfect conductor. Determine the resulting E
and H fields. Sketch their variations. (Set No. 4 Aug/Sep 2008 Supply)
6. A plane EM wave is normally incident on the boundary between two dielectrics. What must be the ratio
of the refractive indices of the two media in order that the reflected and transmitted waves may have equal
magnitudes of average power (Set No. 4 Aug/Sep 2008 Supply)
7. Explain wave propagation in a conducting medium. (Set No. 1 Apr/May 2008 Reg)
UNIT-VI
SET-1
1. Define and differentiate between the terms: Instantaneous average and complex poynting vectors, giving
their mathematical expressions. ( Set No. 1 Apr/May 2008 Supply)
2. State and Prove Poynting Theorem. ( Set No. 2, 3 Apr/May 2008 Supply)
3. Derive expression for Reflection and Transmission coefficients of an EM wave when it is incident
normally on a dielectric. ( Set No. 4 Apr/May 2008 Supply)
SET-II
4. For an incident wave under oblique incident from medium of _1 to medium of _2with parallel
polarization ( Set No. 4 Apr/May 2008 Supply)
5. Explain the significances of Poynting theorem and Poynting vector. (Set No. 2 Aug/Sep 2008 )
6. A Plane wave traveling in a free space has an average poynting vector of 5 watts/m2. Find the average
energy density. ( Set No. 2, 3 Apr/May 2008 Supply)
SET-III
7. Plot _C and _Br versus the ratio of _1/_2
8. Write short notes on the following
(a) Surface Impedance (b) Brewster angle (c) Total Internal Reflection
9. Explain the difference between the Intrinsic Impedance and the Surface Impedance of a conductor. Show
that for a good conductor, the surface impedance is equal to the intrinsic impedance.
10. Define surface impedance and explain how it exists. (Set No. 4 Apr/May 2008 Supply)
SET-IV
11. Define and establish the relations for the critical angle _C and Brewster angle _Br for non-magnetic
media with neat sketches.
12. Define Complex Poynting vector and explain how to obtain an average power. (Set No. 1 Aug/Sep 13.
Prove that under the condition of no reflection at an interface, the sum of the Brewster angle and the angle
of refraction is 90 degrees for parallel polarization for the case of reflection by a perfect conductor under
oblique incidence, with neat sketches. (Set No. 2 Aug/Sep 2008 Supply)
UNIT-VII
SET-1
1. Derive a relation between reflection coefficient and characteristic impedance. (Set No. 1 Apr/May 2. 2.
Determine the reflection coefficients when (Set No. 1 Apr/May 2008 Supply)
i. ZL = Z0
ii. ZL = short circuit
iii. ZL = open circuit.
iv. Also find out the magnitude of reflection coefficient when ZL is purely reactive.
3. List out types of transmission lines and draw their schematic diagrams. (Set No. 2 Apr/May 2008 4. 4.
Draw the directions of electric and magnetic fields in parallel plate and coaxial lines.
5. A transmission line in which no distortion is present has the following parameters Z0= 50_, = 20mNP/m,
_= 0.6_0. Determine R, L, G, C and wavelength at 0.1 GHz. (Set No. 2 Apr/May 2008 6. List out types of
transmission lines and draw their schematic diagrams. (Set No. 3 Apr/May 2008 7. Draw the directions of
electric and magnetic fields in parallel plate and coaxial lines.
8. A transmission line in which no distortion is present has the following parameters Z0= 50_, = 20mNP/m,
_= 0.6_0. Determine R, L, G, C and wavelength at 0.1 GHz. (Set No. 3 Apr/May
9. What are the salient aspects of primary constants of a two wire transmission line
SET-II
10. A lossless transmission line used in a TV receiver has a capacitance of 50 PF/m and an inductance of
200 nH/m. Find out the characteristic impedance for 10 meter long section of the line and 500 meter
section.
11. Explain the different types of transmission lines. What are limitations to the maximum power that they
can handle
12. A coaxial limes with an outer diameter of 8 mm has 50 ohm characteristic impedance. If the dielectric
constant of the insulation is 1.60, calculate the inner diameter.
13. Describe the losses in transmission lines (Set No. 1 Apr/May 2008 Reg.) (Set No. 1 Aug/Sep 2008 14.
Definite following terms and explain their physical significance.
i. Attenuation function
ii. Characteristic impedance
iii. Phase function, and
iv. Phase velocity as applied to a transmission line. (Set No. 2 Apr/May 2008 Reg.)
SET-III
15. At 8 MHz the characteristic impedance of transmission line is (40-j2) _ and the propagation constant is
(0.01+j0.18 ) per meter. Find the primary constants. (Set No. 2 Apr/May 2008 Reg.)
16. Define the following
i. Infinite line
ii. Insertion loss
iii. Lossy and loss less lines
iv. Phase and group velocities (Set No. 3 Apr/May 2008 Reg.)
17. Derive the characteristic impedance of a transmission line in terms of its line constants
18. Explain the meaning of the terms characteristic impedance and propagation constant of a uniform
transmission line and obtain the expressions for them in terms of Parameters of line?
19. A telephone wire 20 km long has the following constants per loop km resistance 90 _, capacitance
0.062 μF , inductance 0.001H and leakage = 1.5 x 10 −6 mhos. The line is terminated in its characteristic
impedance and a potential difference of 2.1 V having a frequency of 1000 Hz is applied at the sending end.
Calculate :
i . The characteristic impedance
ii. Wavelength
iii. The velocity of propagation (Set No. 4 Apr/May 2008 Reg.)
19. Sketch the voltage and current distribution along matched, open and short circuited transmission lines.
SET-IV
20. A line 10 km long has the following line constants: Z0= 600 |0 0 = 0.1neper/km _= 0.05radians/km
Find the received current and voltage when 200 mA are sent down into one end, and the receiving end is
shorted.
21. Define the i/p impedance of a transmission line and derive the expression for it.
22. The characteristic impedance of a certain line is 710 |140 and _ = 0.007 + j0.028 per km. The line is
terminated in a 300Ohm resistor. Calculate the i/p impedance of the line if its length is 100 km.
23. Show that for any uniform transmission line the following relations are valid. Z0 = (Zoc.Zsc)1/2
TanhP1 = (Zsc/Zoc)1/2 What will be their modifications for loss less lines? (Set No. 3 Aug/Sep 2008 24.
Short-circuited and open ?circuited measurements at frequency of 5000 Hz on a line length 100 km yields
the following results:
Zoc = 570? − 480
Zsc = 720, 340
25. Find the characteristic impedance and propagation constant of the line. (Set No. 3 Aug/Sep 2008 2. 26.
List out types of transmission lines and draw their schematic diagrams. (Set No. 4 Aug/Sep 2008 26. Draw
the directions of electric and magnetic fields in parallel plate and coaxial lines.
27. A transmission lines in which no distortion is present has the following parameters Z0 = 50 , = 20
mNP/m = 0.60. Determine R, L, G, C and wavelength at 0.2 GHz (Set No. 4 Aug/Sep 2008 Supply
(12)List of topics for student’s seminars
1. Vector calculus
2. Vector algebra
3. Coordinate system
4. Electrostatic fields
5. Time varying fields
6. Transmission lines
7. Smith Chart
8. VSWR
PULSE AND DIGITAL CIRCUITS
S.NO
CONTENT
(1)
-
(2)
Objectives and Relevance
-
Scope
(3)
-
Prerequisites
(4)
-
Syllabus
1.
JNTU
2.
GATE
3.
IES
(5)
-
Websites
(6)
-
Expert Details
(7)
-
Subject (lesson) Plan
(8)
-
Suggested Books
(9)
-
(10)
-
Objective & Outcome Based Plan for Subject (OOPS)
Course/Subject Objectives
(11)
(12)
-
(13)
-
Prog ram education Outcomes
Action & Assess ment Plan
(12.1) Assignment Q uestions
(12.2) Slip Test questions
Assessment plan for Action
13.1) Assessment plan for
13.2) Assessment plan for Slip Test
Assignments
(14)
-
Program Outcome Matrix
(15)
-
Course/Laboratory Schedule
(16)
-
Experts details
(17)
-
Mid and Final Examination question
(18)
-
List of topics for student’s
Seminarspapers
1) COURSE OBJECTIVE & RELEVANCE:
The purpose of this course is to introduce students to the basics of biasing transistor
circuits, wave shaping circuit using transistor & analyzing different electronic
circuits.(large signal amplifiers,), Multi vibrators, voltage & current Time Base generators
with pulse signals.
This course introduces methods of generation of pulse waveforms making use of
semiconductor devices like diodes, transistors and UJT’s. Pulse waveforms play a
significant role in electronics to refer to non-sinusoidal waveforms. These waveforms
play a vital role in electronics and communications. The basic objective of this subject is
to help students analyze circuits for different non-sinusoidal signals which help them
immensely to use them in pulse communication, television engineering, radar and
telemetry.
First Year – 4 credits
Topics:
1. Linear Wave Shaping
2. Non-Linear Wave Shaping
3. Switching Characteristics of Devices
4. Multi vibrators
5. Time Base Generators
6. Sampling Gates
7. Synchronization and Frequency Division
8. Realization of Logic Gates Using Diodes & Transistors
2) SCOPE:
This subject helps in understanding the generation and processing of non sinusoidal
waveforms. The switching mode of operation can also be analyzed. This subject gives us an
idea or overview to transmit the signal from one location to another, to amplify it, to select
a portion of it in voltage, to choose a section of it in time, to combine it with other signal in
order to perform a logic operation, to use it to synchronize a system and so orth.

The study of pulse and digital circuits emphasizes the application of basic
scientific principles to the design of equipment, which includes electronic and
electro-mechanical systems, for use in measurements, communications, and
digital electronics.
At the end of this course the students will learn and apply



Basic working & design of wave shaping circuits
Time response of various signals like ramp, pulse
Behaviour of time base, current base signal generators
3) PREREQUISITES:
The student is expected to be familiar with the fundamentals of linear circuit analysis
and small signal models of electronic devices, like semiconductor diodes and transistors
and knowledge of different theorems, analyzing circuits, mesh analysis for getting
output and input relations.
4) SYLLABUS:
I) JNTU
Sub: Pulse and Digital Circuits
II Year B.Tech (Regulation: R09)
(ECE/ EEE)
L/ T/P/D C
3/
/3/ 4
Unit-I
Linear Wave Shaping: High pass and low pass RC circuits and their response for Sinusoidal, Step,
Pulse, Square & Ramp inputs, High pass RC network as Differentiator, Low pass RC circuit as an
Integrator, Attenuators and its application as a CRO Probe, RL and RLC Circuits and their
response for step Input, Ringing Circuit.
Unit-II
Non-Linear Wave Shaping: Diode clippers, Transistor Clippers, Clipping at two independent
levels, Comparators, Applications of Voltage comparators. Clamping Operation, Clamping circuit
taking Source and Diode resistances into account, Clamping Circuit Theorem, Practical Clamping
Circuits, Effect of Diode Characteristics on Clamping Voltage, Synchronized Clamping.
Unit-III
Switching Characteristics of Devices: Diode as Switch, Piecewise Linear Diode Characteristics,
Diode Switching times, Transistor as a Switch, Breakdown voltages, Transistor in Saturation,
Temperature variation of Saturation Parameters, Transistor-switching times, Silicon-controlled –
switch circuits.
Unit-IV
Multivibrators:
Analysis and Design of Bi-stable, Mono-stable, Astable Multivibrators and Schmitt trigger using
Transistors.
Unit-V
Time Base Generators:
General features of a Time base signal, Methods of Generating Time Base Waveform, Miller and
Bootstrap Time Base Generators-Basic Principles, Transistor Miller Time Base generator,
Transistor Bootstrap Time base Generator, Transistor Current Time Base Generators, and
Methods of Linearity improvement.
Unit-VI
Sampling Gates:
Basic operating principles of Sampling Gates, Unidirectional and Bi-directional sampling Gates,
Four Diode Sampling Gate, Reduction of pedestal in gate Circuits, Six Diode Gate, Application of
Sampling Gates>
Unit-VII
Synchronization and Frequency Division:
Pulse Synchronization of Relaxation Devices , Frequency division in Sweep Circuit, Stability of
Relaxation Devices, Astable Relaxation Circuits, Mônostable Relaxation Circuits, Synchronization
of a Sweep Circuit with Symmetrical Signals, Sine wave frequency division with a Sweep Circuit,
A Sinusoidal Divider using Regeneration and Modulation.
Unit-VIII
Realization of Logic Gates Using Diodes & Transistors:
AND, OR and NOT Gates using Diodes and Transistors, DCTL, RTL, DTL, TTL and CML Logic
Families and its comparison.
TEXT BOOKS
1. J. Millman and H. Taub, “Pulse & Digital and Switching Waveforms” 2nd ed., Tata McGrawHill, 2008.
2. A. Anand Kumar, “Pulse and Digital Circuits”, 2nd ed., PHI, 2009.
REFERENCE BOOKS
1. David A. Bell, “Solid State Pulse circuits”, 4th ed., PHI, 2009.
2. R.P. Jain, Modern Digital Electronics, 1st ed., Tata McGraw-Hill, 2010
II) GATE
UNIT 1
1. Time constant RC
2. RC circuits-low pass, high pass, attenuators
UNIT II
1. Clipping circuits
2. Clamping circuit theorem
UNIT III
1. Transistor-switch
UNIT IV
1. Multivibrators
2. Schmitt trigger
UNIT V
1. Errors in time base generators
UNIT VIII
1. Concept of logic gates
III) IES
UNIT 1
1. RC low pass circuit
2. RC high pass circuit
UNIT III
1. Transistor-switch
3. Switching times
4.
UNIT IV
1. Multivibrators
2. Schmitt trigger
UNIT VIII
1. Concept of logic gates
(5) WEBSITES:
1)
2)
3)
4)
5)
6)
7)
8)
9)
10)
http://www.electronics-tutorials.ws/waveforms/monostable.html
http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/logfam.html
www.stanford.edu/class/ee122/Handouts/0%20Intro.pdf
http://openbookproject.net/electricCircuits/
http://www.elexp.com/links.htm
http://simple.wikipedia.org/wiki/Category:Electronic_components
nptel.iitm.ac.in/courses/Web course-contents/IIT.../main1.html
www.iisc.ernet.in
www.e-booksdictionary.com
http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=6576263
(6) SUJECT EXPERTS DETAILS:
INTERNATIONAL:
1) Professor Luke J. Mawst ,University of Madisson
Ph: (608) 263-1705
Fax: (608) 262-1267
[email protected]
2) Professor Zhenqiang (Jack) Ma, university of Madisson
Ph: (608) 261-1095
Fax: (608) 261-1095
[email protected]
3) Professor Peter Y.K. Cheung, Imperial College of science, technology and medicine,
London, Department of Electrical and Electronic Engineering
[email protected]
NATIONAL:
1) T.S Natarajn, Professor, IIT madras
Tele Phone Number: +91 - 44 - 2257 4860 (OFF.)
Mobile Number: +91 – 8056000958
Email_Id: [email protected]
2) Dr. Dhrubes Biswas, Professor, Electronics & Electrical Communication
Engineering,
IIT kharagpur,
Phone (office): +91 - 3222 – 283528
Phone (residence): +91 - 3222 - 283529 (IIT Phone)
Email_Id:dbiswas @ ece.iitkgp.ernet.in
3) Chitralekha mahanty, Professor,
Office Address: Room No. #106, EEE Department, IIT Guwahati, Guwahati781039, INDIA.
Phone: +91-361-258-2507 (O)
Fax: +91-361-2582542, 2690762
Email: [email protected]
4) Professor Pramod Agarwal,IIT, Roorkee,
Email_Id:[email protected]
REGIONAL
1) Suryaprakash Mothiki, professor and head of the Deparment, Vishakapatnam, AP
Works at Sri Vasavi Engineering College, Tadepalligudem
Attended JNTU College of Engineering, Kakinada
Lives in Tadepalligudem
2) Sri V Aravind ,Professor, Gokaraju Rangaraju Institute of Engineering and
Technology
E-mail: [email protected]
3) Dr. A.Vani, Assoc. Prof, Dept of ECE, Chaitanya Bharathi Institute of Technology
Email_Id:[email protected]
7) LESSON PLAN
Subject code
Name of the subject
Year/Branch
Name of the Faculty
54021
Pulse And Digital Circuits
II B.Tech II Sem ECE
G.DIVYA&
P.BHAGYALAKSHMI
Name of the
Topic
UNIT-I
Subtopics
High pass RC circuit response for
Sinusoidal, Step input
No.
of
class
es
Text
book
s
Methodolo
gy
L1
T1,
R1
M1
Remark
s
LINEAR WAVE
SHAPING
High pass RC circuit response for
Pulse, Square input
L2
High pass RC circuit response for
ramp &exponential input
L3
Low pass RC circuit as integrator
Low pass RC circuit response for
Sinusoidal, Step input
L4
Low pass RC circuit response for
Pulse, Square input
L5
T1,
R1
M1
T1,
R1
M1
T1,
R1
M1
T1,
R1
M1
T1,
R1
M1
T1,
R1
M1
T1,
R1
M1
T1,
R1
M1
T1,
R1
M1
T1,
R1
M1
L6
Low pass RC circuit response
for ramp &exponential input
High pass RC network as
Differentiator
L7
Low pass RC network as Integrator
L8
Attenuators and its application as a
CRO Probe
L9
RL Circuits and their response for
step Input
L10
RLC Circuit and their response for
step Input, Ringing Circuit.
L11
TOTAL NO OF CLASSES 11
UNIT-II
NON-LINEAR
WAVE SHAPING
Diode clippers
L1
T1,
R1
M1
Transistor Clippers
Clipping at two independent
levels
L2
L3
T1,
T1,
R1
R1
M1
M1
T1,
R1
M1
T1,
R1
M1
L4
Comparators, Applications of
Voltage comparators.
L5
Clamping Operation
L6
Clamping circuit taking Source
and Diode resistances into
account
T1,
R1
M1
L7
Clamping Circuit Theorem,
Practical Clamping Circuits
Effect of Diode Characteristics
on Clamping Voltage
T1,
R1
L8
T1,
R1
M1
M1
L9
Synchronized Clamping
T1,
R1
M1
TOTAL NO OF CLASSES 09
UNIT III
SWITCHING
CHARACTERISTICS
OF DEVICES
Diode as Switch, Piecewise Linear
Diode Characteristics
L1
Diode Switching times
L2
Transistor as a Switch, Breakdown
voltages, Transistor in Saturation
L3
Diode as Switch, Piecewise Linear
Diode Characteristics
L4
Diode Switching times
L5
Transistor as a Switch, Breakdown
voltages, Transistor in Saturation
L6
T1,
R1
M1
T1,
R1
M1
T1,
R1
M1
T1,
R1
M1
T1,
R1
M1
T1,
R1
M1
Temperature variation of
Saturation Parameters, Transistorswitching times
L7
Silicon-controlled –switch circuits
L8
T1,
R1
M1
T1,
R1
M1
TOTAL NO OF
CLASSES 08
Analysis of Bi-stable Multi
vibrators.
L1
Design of Bi-stable Multi vibrators
Analysis
of Mono-stable Multi
using Transistors
vibrators
L2
L3
Design of Mono-stable Multi
vibrators on astable,monostable
Problems
and bistable multivibrators
L4
L5
Analysis of As table Multi
vibrators
L6
Design of As table Multi vibrators
using Transistors
L7
Analysis of Schmitt trigger
L8
UNIT IV
MULTI
VIBRATORS
Design of Schmitt trigger using
Transistors
L9
Problems
L10
T1,
R1
M1, M2
T1,
T1,
R1
R1
M1, M2
M1, M2
T1,
T1,
R1
R1
M1, M2
M1, M2
T1,
R1
M1, M2
T1,
R1
M1, M2
T1,
R1
M1, M2
T1,
R1
M1, M2
T1,
R1
M1, M2
TOTAL NO OF CLASSES 10
UNIT V
TIME BASE
GENERATORS
General features of a Time base
Methods
signal, of Generating Time Base
Waveform
L1
L2
Miller Time Base Generators-Basic
Principle
L3
T1,
T1,
R1
R1
M1
M1
T1,
M1
R1
Transistor Miller Time Base
generator
L4
Transistor Bootstrap Time base
Generator
L5
Bootstrap Time Base GeneratorsBasic Principle
L6
Transistor Current Time Base
Generators
L7
Problems, Methods of Linearity
improvement
L8
T1,
R1
M1
T1,
R1
M1
T1,
R1
M1
T1,
R1
M1
T1,
R1
M1
TOTAL NO OF CLASSES 08
Basic operating principles of
Unidirectional
Sampling Gatessampling Gates
L1
L2
Bi-directional sampling Gates
L3
Four Diode Sampling Gate
Reduction of pedestal in gate
Circuits
L5
Six Diode Gate
L6
Application of Sampling Gates
M1
M1
T1,
R1
M1
T1,
R1
M1
T1,
R1
M1
T1,
R1
M1
T1,
R1
M1
L4
UNIT VI
SAMPLING GATES
T1,
T1,
R1
R1
L7
TOTAL NO OF CLASSES 08
UNIT VII
SYNCHRONIZATIO
N AND
Pulse Synchronization of Relaxation
Frequency
Devices, division in Sweep Circuit
L1
L2
T1, R1
T1, R1
M1,
M2M1,
M2
FREQUENCY
DIVISION
Stability of Relaxation Devices
A stable Relaxation Circuits
L3
T1, R1
M1,
M2
T1, R1
M1,
M2
T1, R1
M1,
M2
T1, R1
M1,
M2
T1, R1
M1,
M2
T1, R1
M1,
M2
L4
Mono stable Relaxation Circuits
L5
Synchronization of a Sweep Circuit
with Symmetrical Signals
L6
Sine wave frequency division with a
Sweep Circuit
L7
A Sinusoidal Divider using
Regeneration and modulation
L8
TOTAL NO OF CLASSES 08
UNIT VIII
REALIZATION OF
LOGIC GATES
USING DIODES &
TRANSISTORS
Realization of AND Gate using Diodes
and transistors
L1
Realization of OR and NOT Gates
using Diodes and Transistors
L2
DCTL Logic Family
L3
RTL Logic Family
T1, R1
M1
T1, R1
M1
T1, R1
M1
T1, R1
M1
T1, R1
M1
T1, R1
M1
T1, R1
M1
L4
DTL Logic Family
L5
TTL Logic Family
L6
CML Logic Family
L7
TOTAL NO OF CLASSES 07
TOTAL NO OF CLASSES
69
Lect
ure
No.
JNTUH Topic
Objective of each Topic
Learning Outcome
Practical
Inferences
Met
hod
of
Teac
hing
M1
&
M5
UNIT – 1 LINEAR WAVE SHAPING
L1,
L2
L3
L4,
L5
L6,
L7
L8,
L9
L10,
L11
High pass RC circuit and
their response for
Sinusoidal, Step, High pass
RC circuit and their
response for Pulse, Square
& Ramp inputs,
Explanation of Transients
for
different
combinations of circuit
parameters.
Differentiating
between
transients and steady state
responses of RL, RC, RLC circuits
and plotting the response.
Useful
in
determining the
relationship
between time
constant
and
performance of
the circuit.
High pass RC network as
Differentiator
Explanation of how high
pass RC circuit acts as an
differentiator
Knowledge about the response of
the system before and after
occurring of the transient’s w.r.t
mathematical equations.
Useful
to
convert
triangular wave
in to a square
wave
Low pass RC circuit and
their response for
Sinusoidal, Step, Low pass
RC circuit and their
response for Pulse, Square
& Ramp inputs,
Explanation to calculate
complete solution of the
transient circuit.
Differentiating
between
transients and steady state
responses of low pass RC circuit
for
step,pulse,ramp
and
sinusoidal wave forms and
plotting the response
Useful
in
determining the
relationship
between time
constant
and
performance of
the circuit.
Low pass RC circuit as an
Integrator
Explanation of how low
pass RC circuit acts as an
integrator
Knowledge about the response of
low pass RC circuit as integrator
and calculation of time constant
Useful
to
convert square
wave in to a
triangular wave
Explanation
attenuator
applications
Knowledge
about
attenuator operation
practical applications
Useful to reduce
the amplitude of
the signal and
CRO
probe
applications
Attenuators and its
application as a CRO
Probe
RL and RLC Circuits and
their response for step
Input, Ringing Circuit
and
of
its
Explanation of RL,RLC
circuits
and
ringing
circuit
the
and
Knowledge about the response of
RL,RLC and ringining circuits
Useful
in
generation
of
pulses
and
timing
applications
M1
&
M5
M1
&
M5
M1
&
M5
M1
&
M7
M1
&
M6
UNIT – 2 NON LINEAR WAVE SHAPING
L12,L
13
Diode clippers
Explanation
clippers
of
diode
Should get knowledge of the
diode series and shunt clippers
Useful to remove
unwanted portion of
the signal and to find
the
transfer
characteristics
M1
&
M5
Transistor
Clippers,
Clipping
at
two
independent levels
Explanation
of
transistor clipper and
clipping
at
two
independent levels
Knowledge of clipping at two
independent levels
L15
Comparators,
Applications of Voltage
comparators
Explanation
of
comparator circuit and
its operation
Knowledge
about the
comparator circuit and how
the
comparison operation
performed
L16
Clamping Operation,
Clamping circuit taking
Source and Diode
resistances into account
Explanation of clamping
circuit and its operation
Knowledge
about
the
clamping circuit when diode
resistance included in the
circuit
L14
L17,L
18
L19
Clamping Circuit
Theorem,PracticalClampi
ng Circuits
Explanation of clamping
circuit theorem and
practical applications
Effect of Diode
Characteristics on
Clamping Voltage
Explanation of diode
characteristics on
clamping voltage
Synchronized Clamping
Explanation
of
Synchronized Clamping
L20
Used
as double
ended clipper and to
find the transfer
characteristics
Useful in comparison
applications, analog
to digital converters
Used to insert the dc
level by fixing the
positive or negative
extremity of that
waveform to some
reference level
M1
&
M5
M1
&
M5
M1
M1
&
M4
Knowledge
about
the
clamping circuit theorem and
practical clamping circuits
Useful to calculate
steady
state
conditions
of
clamping circuits
Knowledge about the effect of
diode
characteristics
on
clamping voltage
Useful to calculate
the effect of diode
characteristics
by
applying
clamping
voltage
Knowledge
about
the
Synchronized Clamping and its
applications
Useful to provide dc
restoration
when
positive & negative
excursions of the
signal fluctuate from
cycle to cycle
M1
&
M7
Knowledge about diode acts
as
switch
&knowledge
about piece wise linear
diode characteristics
Useful in switching
applications
M1
Should get the knowledge
about the switching times of
diode
Useful to calculate
diode
switching
times
such
as
storage
time,transition
time,reverse
recovery times etc
MI&
M6
UNIT –3 SWITCHING CHARACTERISTICS OF DEVICES
L21
Diode as Switch, Piecewise
Linear Diode Characteristics
Explanation
of
piecewise linear diode
characteristics
Diode Switching times
L22
Explanation
about
different
switching
times of diode
M1
& M6
L23
Transistor as a Switch,
Breakdown voltages,
Transistor in Saturation
Design of Transistor Switch
L24
L25
L26
Explanation
of
transistor acts as switch
and transistor action in
saturation region
Knowledge of
transistor
acts as switch and working
principle of transistor is in
saturation region
Transistor acts as
closed switch in
saturation region.
Explanation
Design of
Switch
Knowledge
of
design
specifications of transistor
switch
Used to calculate
different
parameters
of
transistor
about
Transistor
M1&
M5
M1
&
M4
Temperature variation of
Saturation Parameters
Explanation
about
Temperature variation
of
Saturation
Parameters
Knowledge on Temperature
variation
of
Saturation
Parameters
Used to calculate
sensitive
parameters
of
transistor
M1
Silicon-controlled –switch
circuits
Explanation
about
silicon
controlled
switch.
Knowledge about working
principle
of
Siliconcontrolled switch circuits
Used in switching
applications
M4
UNIT – 4 MULTIVIBRATORS
L27
Analysis of Bi-stable Multi
vibrators.
Explanation of
Knowledge
of
Bistable
multivibrator and analysis
Bistable Multivibrator
Design of Bi-stable Multi
vibrators using Transistors
L28
L29
L30
L31
L32
Analysis of Mono-stable
Multi vibrators
Design of Mono-stable Multi
vibrators
Problems on Monostable
and Bistable Multivibrators
Analysis of Astable Multi
vibrators
Explanation about the
design of bistable multi
vibrator
using
transistors
Knowledge of Bi-stable
Multi vibrator design using
transistor and its working
principle
Explanation
Monostable
multivibrator
Knowledge of Monostable
multivibrator and analysis
of
Used as the basic
memory
element,
also called as flipflop
Useful
in
many
digital
operations
such as counting and
storing of binary
data and generation
of
pulse
type
waveforms
Used in pulse circuits
M1
&
M4
M1
&
M5
M1
&
M4
Explanation about the
design of Monostable
multivibrator
using
transistors
Knowledge of Monostable
Multi vibrator design using
transistor and its working
principle
Mostly Used as a
Gating circuit or
Delay Circuit.
Explanation about the
Monostable bistable
multivibtrators design
specifications
knowledge on Monostable
and Bistable multivibtrators
design specifications
Used to calculate the
pulse width and time
constants
Explanation of Astable
Multivibrator
Knowledge of
Astable
Multivibrator and analysis
Used
as
Free
Running Oscillator
and
Relaxation
M1
&
M5
M6
&
M7
M1
&
Oscillator
Design of As table Multi
vibrators using Transistors
L33
L34
L35,L
36
Design of Schmitt trigger
using Transistors
problems
Explanation on about
the
Astable
multivibtrators design
using transistors
Explanation
Schmitt
trigger using Transistors
Explanation about the
problems
on
Multivibrators
Knowledge of Astable Multi
vibrator
design
using
transistor and its working
principle
M4
Used as master
oscillator
to
generate
square
waveforms
also
called as square
wave generator.
M1
&
M5
Knowledge about design of
Schmitt
trigger
using
transistors
Important
application
of
Schmitt Trigger is as
a Squaring Circuit.
M1
&
Knowledge
about
the
problems on Multivibrators
Used to determine
pulse width and time
constant
M1
&
M6
Useful applications
are CROs, TeleVision
and RADAR Displays.
M1
M1
M5
UNIT – 5 TIME BASE GENERATORS
L37
L38
L39
L40
L41
L42,L
43
L44
General features of a Time
base signal
Explanation of
General features of a
Time base signal
Knowledge of time base
signal and calculation of
errors.
Methods of Generating Time
Base Waveform
Explanation of methods
of generating time base
wave form
Knowledge on different
methods of generating time
base wave form
Used in
circuits
Explanation miller time
base generator and its
working principle
Knowledge on miller time
base generator and working
principle
Used to
convert
input step voltage
into
a
ramp
waveform
M1
Explanation transistor
miller
time
base
generator
Knowledge on transistor
miller time base generator
and working principle
A Miller time base
generator produces
a negative
going
sweep
M1
Explanation
of
Transistor
Bootstrap
Time base Generator
Knowledge on Transistor
Bootstrap
Time
base
Generator and its working
Used to produce a
positive
going
sweep.
M1
&
M5
Knowledge on transistor
current
time
base
generators
Used in transistor
current
sweep
circuits
such
as
magnetic deflection
applications
Miller Time Base
Generators-Basic Principle
Transistor Miller Time Base
generator
Transistor Bootstrap Time
base Generator
Transistor Current Time
Base Generators
Problems, Methods of
Linearity improvement
Explanation
of
Transistor Current Time
Base Generators
Explanation of methods
of
linearity
improvements
Knowledge on improving
methods of linearity
sweep
Used
in sweep
circuit applications
M1
&
M4
M1
&
M6
UNIT – 6 SAMPLING GATES
Basic operating principles of
Sampling Gates
L45
Unidirectional sampling
Gates
Explanation of Basic
operating principles of
Sampling Gates
Explanation
of
Unidirectional sampling
Gates
L46
Knowledge about Basic
operating
principles
of
Sampling Gates
Knowledge of Unidirectional
sampling Gates
Used
as Selection
Circuits, which the
output
is
exact
reproduction
of
input.
Useful to transmit
only one polarity of
signal either positive
or negative signals
M1
&
M4
M1
&
M6
.
L47
Bi-directional sampling
Gates
Explanation
directional
Gates
Four Diode Sampling Gate
L48
L49
Reduction of pedestal in
gate Circuits
of
Bisampling
Working Principle Of
Four Diode Sampling
Gate
Knowledge on Working
Principle Of Four Diode
Sampling Gate
Used in Digital to
Analog Converters
Working of Reduction
of pedestal in gate
Circuits
Knowledge on working of
Reduction of pedestal in
gate Circuits
Used
Superimpose
input signal
output signal
Working Principle Of Six
Diode Sampling Gate
Knowledge on Working
Principle Of Six Diode
Sampling Gate
Six Diode Gate
L50
L51
Application of Sampling
Gates
Useful to transmit
Knowledge on the Biboth
positive
and
directional sampling Gates
negative signals.
Explanation
about
Application of Sampling
Gates
Knowledge on Application
of Sampling Gates
M1
&
M7
M1
&
M4
to
the
on
Used
in
Multiplexers, Sample
and Hold Circuits
Used
in
Multiplexers, Sample
and Hold Circuits,
Sampling Scopes
M1
&
M4
M1
&
M4
M6
UNIT – 7 SYNCHRONIZATION AND FREQUENCY DIVISION
Pulse Synchronization of
Relaxation Devices
Explanation about Pulse
Synchronization
of
Relaxation Devices
Knowledge on working
principle
of
Pulse
Synchronization
of
Relaxation Devices
Frequency division in Sweep
Explanation
of
Frequency division in
Knowledge about Frequency
L52
L53
Used
as
Multivibrators,Time
base
Genarators,Blocking
Oscillators etc.
Used
in
Counting
M1
&
M4
M1
&
Circuit
Sweep Circuit
division in Sweep Circuit
Stability of Relaxation
Devices
Working principle of
stability of Relaxation
Devices
Knowledge on stability of
Relaxation Devices
Astable Relaxation Circuits
Explanation of Astable
Relaxation Circuits
Knowledge on Working of
Astable Relaxation Circuits
Monostable Relaxation
Circuits
Explanation
of
Monostable Relaxation
Circuits
Knowledge on Working of
Monostable
Relaxation
Circuits
Synchronization of a Sweep
Circuit with Symmetrical
Signals
Explanation
about
Synchronization of a
Sweep Circuit with
Symmetrical Signals
Knowledge
about
Synchronization of a Sweep
Circuit with Symmetrical
Signals
Sine wave frequency
division with a Sweep Circuit
Explanation of
Sine
wave frequency division
with a Sweep Circuit
Knowledge about Sine wave
frequency division with a
Sweep Circuit
A Sinusoidal Divider using
Regeneration and
Working of a Sinusoidal
Divider using
Regeneration and
Knowledge on a Sinusoidal
Divider using Regeneration
and
modulation
modulation
L54
L55
L56
L57
L58
L59
modulation
Circuits
Used in constant
Sweep Generators
Used as Frequency
Divider
Used
in
the
application
of
Frequency Division
Used in
Pulse
Synchronization
applications
Used in Counting
Applications
Used in Frequency
Dividers
and
Modulation circuits
M4
M1
&
M4
M1
&
M4
M1
&
M4
M1
&
M4
M1
&
M4
M1
&
M4
UNIT – 8 REALIZATION OF LOGIC GATES USING DIODES & TRANSISTORS
L60
Realization of AND Gate
using Diodes and transistors
Implementation of AND
Gate using diodes and
transistors
Knowledge to realize basic
AND gate using diodes and
transistors
Implementation of basic
gates OR & NOT Gate
using
diodes
and
transistors
Knowledge to realize basic
OR &NOT gates using diodes
and transistors
Transistors
L61
Realization of OR and NOT
Gates using Diodes and
Transistors
Useful to implement
digital circuits and
VLSI circuits
M1
&
M5
Useful to implement
digital circuits and
VLSI circuits
M1
&
M5
DCTL Logic Family
L62
RTL Logic Family
L63
DTL Logic Family
L64
TTL Logic Family
L65
CML Logic Family
L66
Explanation of direct
coupled transistor logic
family
Knowledge about the direct
coupled
transistor logic
family
Useful to implement
digital circuits and
VLSI circuits
M1
Explanation of resistor
transistor logic family
Knowledge
about
the
resistor
transistor logic
family
Useful to implement
digital circuits and
VLSI circuits
M1
Explanation of diode
transistor logic family
Knowledge about the diode
transistor logic family
Useful to implement
digital circuits and
VLSI circuits
M1
Explanation
transistor
logic family
Knowledge
about
the
transistor transistor logic
family
Useful to implement
bipolar digital IC
family and VLSI
Circuits
M1
&
Useful in super fast
computers and high
speed
special
purpose applications
M1
&
of
transistor
Explanation of current
mode logic family
Knowledge
about
the
current mode logic family or
emitter coupled logic family
8) SUGGESTED BOOKS:
TEXT BOOKS:
1. Principles Millman’s Pulse, Digital and Switching Waveforms – J.Millman, H.Taub and
Mothiki
S. Prakash Rao, 2 ed., 2008, TMH.
2. Solid State Pulse circuits – David A. Bell, 4 ed., 2002 PHI.
REFERENCE BOOKS:
1.
2.
3.
4.
Pulse and Digital Circuits – A. Anand Kumar, 2005, PHI.
Fundamentals of Pulse and Digital Circuits – Ronald J Tocci, 3 ed., 2008
Pulse and Digital Circuits – Motheki S. Prakash Rao, 2006, TMH.
Wave Generation and Shapping- L .Strauss
9) OBJECTIVE & OUTCOME BASED PLAN FOR SUBJECT (OOPS)
FACULTY: P.BHAGYALAKSHMI &G.DIVYA
SUBJECT: PULSE AND DIGITAL CIRCUITS
DEPT: ECE
M9
M9
M1 : Lecture
M6 : Tutorial
M2 : Demo
M7 : Assignment
M3 : Guest Lecture
M8 : Industry Visit
M4 : Presentation
M9 : Project Based
M5 : Lab/Practical
M10 : OHP
(10) COURSE / SUBJECT OBJECTIVES:
1. To identify the basic types of waves which are used in signal processing such as square,
sine, pulse, ramp etc.
2. Be able to understand the basic principles involved in the generation and processing of
pulse waveforms which are used in different types of applications such as Television,
Radar and Pulse generation and modulation.
3. To gain fundamental understanding of how pulse type signals are transmitted, shaped
or amplified by linear circuits and non linear circuits
4. Understand the concept of Clippers with Diodes and Transistors which are used to
modify by removing its upper or lower portion, Comparators, Applications of Voltage
comparators.
5. Describe the operations performed on the signal such as Clamping Operation (The dc
level of the waveform has to be shifted to a higher level or to a lower level), Clamping
Circuit Theorem, Practical Clamping Circuits, Effect of Diode Characteristics on Clamping
Voltage, Synchronized Clamping.
6. Introduce operation and Switching Characteristics of Devices such as Diode as Switch,
Diode Switching times, Transistor as a Switch, Breakdown voltages, Transistor in
Saturation, Transistor-switching times.
7. To analyse and design of Bi-stable, Mono-stable, Astable Multivibrators and Schmitt
trigger using Transistors.
8. Demonstrate general features of a Time base signal, Methods of Generating Time Base
Waveform, and different types of Time Base Generators such as Miller and Bootstrap
9. Provide basic operating principles of Sampling Gates, Unidirectional and Bi-directional
sampling Gates, Four Diode Sampling Gate, Reduction of pedestal in gate Circuits, Six
Diode Gate, Application of Sampling Gates
10. To provide the understanding of Synchronization and Frequency Division by using
Astable Relaxation Circuits, Mônostable Relaxation Circuits and Sinusoidal Divider using
Regeneration and Modulation.
11. To realize the Logic Gates Using Diodes & Transistors and different logic families such as
DCTL, RTL, DTL, TTL and CML.
11) PROGRAM EDUCATION OUTCOMES
a. Graduates will demonstrate knowledge about the response of the system before and
after occurring
of the transient’s with respect to mathematical equations.
b. Graduates will demonstrate an ability to identify, formulate and solve electronic
problems.
c. Graduate will demonstrate an ability to design and conduct experiments, analyze and
interpret data.
d. Graduates will demonstrate an ability to design a system which is used to change the
voltage levels,
and to cut the some portion of input.
e. Graduates will demonstrate an ability to visualize and work on laboratory and
multidisciplinary
tasks.
f. Graduates will demonstrate knowledge of professional and ethical responsibilities.
h. Graduate will be able to design the transistor with specifications.
i. Graduate will show the understanding of impact of practical solutions on the society and
also will
be aware of contemporary issues.
j. Graduate will develop confidence for self education and ability for life-long learning.
k. Graduate who can participate and succeed in competitive examinations.
12) ACTION & ASSESSMENT PLAN (to improve the course plan to meet the objectives)
Students have to attend the daily lecture classes and maintain the lecture notes for
every topic. There are other requirements the student have to meet in order to acquire
adequate knowledge.
Actions:
12.1: Assignments:
Instructions: All the assignments should be in either printed MS Word or Written documents
with the following requirements.
1) Cover page with name, roll number, course name and course section.
2) A page with assignments tasks.
3) Solutions/Explanations.
Three assignments are given to the students during the course.
Assignment1 :( From I unit)
1.(a) Explain RC double differentiator circuit.
(b) Draw the series RLC circuit and derive expression for its transfer function.
2. A ramp input, shown in Figure.1 is applied to a high-pass RC circuit. Draw to scale the output
waveform
for the following cases:
i) T = 0.2 RC ii) T = 10 RC
Figure.1
3. What is an attenuator? Draw the circuit of compensated attenuator. While sketching the
response of
compensated attenuator for perfect compensation, over compensation and under
compensation, show that
the condition for perfect compensation is R C = R C .
1
1
2
2
4. (a)Draw the output waveform of an RC High pass circuit with a square wave input
under different time
constants. Explain the same.
(b)Prove that for any square wave input waveform the average level of the steady state output
signal from
The RC high pass circuit is always Zero.
5. A symmetrical square wave whose peak-to-peak amplitude is 2V and whose average
value is zero as
applied to on RC integrating circuit. The time constant is equals to half -period of the
square wave. Find
the peak to peak value of the output amplitude. Also sketch the output waveform.
6. (a) Derive the expression for percentage tilt for a square wave output of RC high pass circuit.
(b)Draw the circuit of compensated attenuator. Obtain the condition for perfect
compensation?
7. (a) Explain the response of a low pass circuit to an exponential input is applied.
(b) Explain the response of RL circuit when a rectangular pulse is applied
8. (a) i. Three low pass RC circuits are in cascaded and isolated from one another by ideal buffer
amplifiers.Find the expression for the out put voltage as a function of time if the input is
a step
voltage.
ii. Find the rise time of the out put in terms of the product RC.
iii. What is the ratio of the rise time of the three sections in cascade to the rise time of a
single
section?
(b) Write short notes on High pass RC circuit as a differentiator.
9. (a) Write a short notes on RC low pass circuit in detail.
(b) Draw the output response of RC low pass circuit for a step input signal and explain in
detailed.
10. (a) A symmetrical square wave whose peak-to-peak amptitude is 2V and whose average
value is zero is
applied to an RC integrating circuit. The time constant is equal to half -period of the
square wave.
Find the peak to peak value of the output amplitude.
(b) Describe the relationship between rise time and RC time constant of a low pass RC circuit.
11. (a) Prove that an RC circuit behaves as a reasonably good integrator if RC > 15T, Where T is
the period of an input ‘E sin ωt′.
m
(b) What is the ratio of the rise time of the three sections in cascade to the rise-time of Single
section of
low pass RC circuit?
Assignment2 :( From II unit)
1. (a)State and prove clamping circuit theorem.
(b) What in meant by a d.c restoration circuit and explain?
2. (a) Draw the basic circuit diagram of a DC restorer circuit and explain its operation.
(b) For the circuit shown in Figure.1, a sine wave input of 100V peak is applied. Sketch the
output voltage
Vo to the same time scale & transfer characteristic. Assume ideal diodes.
Figure.1
3. (a)Draw the diode differentiator comparator circuit and explain its operation when a ramp
input signal is
applied.
(b)Write a short note on voltage comparators
4. A square wave input as shown in figure.2 is applied to a negative clamper circuit. Sketch the
steady-state
output waveform and derive the necessary expressions.
Figure.2
5. (a) Draw the basic circuit diagram of negative peak clamper and explain its operation
(b) Explain negative peak clipper with and without reference voltage
6. (a) Classify different types of clipper circuits. Give their circuits and explain their
operation with the aid
of transfer characteristics.
(b) Design a diode clamper circuit to clamp the positive peaks of the input signal at zero level.
The
frequency of the input signal is 500 Hz
7. (a) Draw the basic circuit diagram of negative peak clamper circuit and explain its operation.
(b) What is meant by comparator and explain diode differentiator comparator operation with
the help of
ramp input signal is applied.
8. (a) Compare series diode clipper and shunt diode clipper.
(b)Explain positive peak clipping without reference voltage?
9. Draw the circuit diagram of an Emitter-Coupled clipping circuit. Explain its operation with its
transfer
characteristic and necessary expressions
Assignment3 :( From III unit)
1 Explain the phenomenon of “latching” in a transistor switch.
2. Explain how transistor can be used as a switch in the circuit, under what condition a transistor
is said to be
‘OFF’ and ‘ON’ respectively.
3. a) With neat sketches and necessary equations, explain in detail about transistor switching
times.
b) Explain Zener & Avalanche breakdown mechanisms in diodes.
4. a) Explain the transistor switch in saturation region.
b) Explain the diode switching characteristics.
5.(a) Give a brief note on piece-wise linear diode characteristics.
(b) Describe the switching times of BJT by considering the charge distribution across the base
region.
Explain this for cut off, active and saturation regions
6. (a) Explain the terms pertaining to transistor switching characteristics.
i. Rise time.
ii. Delay time.
iii. Turn-on time.
iv. Storage time.
v. Fall time.
vi. Turn-off time.
(b) Give the expression for rise time and fall time in terms of transistor parameters and
operating currents.
7. Calculate the maximum operating frequency of a diode with storage time of 1ns and
transition time of 8ns
Assignment4 :( From IV unit)
1. With reference to multivibrators, explain: i) stable-state ii) loop-gain iii) quasi stable-state
2. Describe multivibrators from the viewpoints of construction, principle of working,
classification
based on the output states, applications and specifications. Mention one specific application
of each.
3. Draw and explain the circuit of Astable Multivibrator with necessary waveforms and also
derive the
expression for its frequency of oscillations.
4. Explain the operation of emitter-coupled bistable multivibrator. Also discuss different
methods of
triggering a bistable multivibrator.
5. What is dead-band in a Schmitt trigger? Draw the hysteresis loop and
explain how hysteresis can be
eliminated in a Schmitt trigger.
6. (a) Explain the reason for the occurrence of overshoot at the base of normally ON transistor
of one shot.
Derive an expression for overshoot.
(b) Discuss a few applications of a monostable multivibrator. Explain how it differs with that of
a binary.
7. (a) Draw the equivalent circuit diagram for differential amplifier used as an astable multi
vibrator.
(b) Draw the various waveforms at base and collector of transistors of the astable
multivibrator
8. (a)What are transpose capacitors? Explain how the commutating capacitors will increase the
speed of a
fixed bias binary.
(b)What do you mean by collector catching diodes? Explain the need of these diodes in a
bistable
Multivibrator.
9. What is a monostable multivibrator? Explain with the help of a neat circuit diagram the
principle of
operation of a monostable multi, and derive an expression for pulse width. Draw the wave
forms at
collector and Bases of both transistors
10. Explain the
multivibrator.
operation
of
an
emitter
coupled
monostable
Assignment5 :( From V unit)
1. Draw a bootstrap sweep circuit using Darlington pair. Explain its operation with neat
waveforms also
mention its merits and limitations?
2. Briefly describe various methods to achieve sweep linearity in time-base circuits.
3. Draw the circuit of a constant current sweep circuit, explain its operation and derive the
expression for sweep voltage.
4. Explain the principle of working of Miller sweep circuit. Derive the expression for sweep
speed
by taking Miller integrator circuit.
5. (a) What is meant by triggered sweep? What are the merits and
demerits of triggered sweep circuits?
(b) What is relaxation oscillator? Name some negative resistance devices used in relaxation
oscillators and
give its applications.
6. (a) Compare the principle of operation of Miller sweep circuit and Bootstrap sweep circuit.
(b) Explain how linearity is obtained by adjusting the driving waveform of current sweep
circuit.
7. (a) What is a linear time base generator?
(b) Write the applications of time base generators.
(c) Define the sweep speed error, displacement error and transmission error of voltage time
base
Waveform
8. (a) Draw the circuit of a Boot strap sweep generator and explain its operation. Derive an
expression for its
sweep time.
(b) Explain with a circuit the working of a UJT sweep circuit and obtain the expressions for the
intrinsic
standoff ratio (η).
9. (a)Define the three errors that occur in a sweep circuit and obtain an expression for
these errors for an
exponential sweep circuit
(b)What are the essential requirements of TV horizontal sweep circuit? How do you achieve
them using a
current sweep?
10. With neat sketches and necessary expressions, explain the transistor Miller time-base
generator
Assignment6 :( From VI unit)
1. Draw the circuit of two-diode bi-directional sampling gate. Explain its operation & derive
expressions for
gain and minimum control voltage in the circuit.
2. Illustrate the principle of sampling gates with series and parallel switches and compare them.
3. For the four-diode sampling gate shown in figure.3, Vs = 25V, R = 50Ω, R = Rc =100KΩ and R2
f
L
=
2KΩ. Find (Vc) , A, V
min
min
and (Vn)
min
for V = V ?
min
Figure.3
4. The four-diode sampling gate (with a divider resistance, R) shown in
Figure.3, V =25V, Rf = 20Ω, RL =
s
Rc = 200KΩ and R = 100Ω. Find (Vc)min, and (Vn)min?
Figure.3
5. (a) Explain the operation of unidirectional diode sampling gate with neat sketch of
waveforms.Illustrate
the effect of different levels of control voltage on gate output.
(b) State the effects of circuit capacitances?
6. (a) sampling gate? Explain how it differs from Logic gates?
(b) What is pedestal ? How it effect the output of sampling gates?
(c) What are the drawbacks of two diode sampling gate?
7. (a) Explain the basic principle of sampling gates using series switch and also give the
applications of
sampling gates.
(b) Explain the effect of control voltage on gate output of unidirectional sampling gate using
diode with
Some example.
8. (a) Explain the operation of a six - diode gate.
(b) Briefly describe the chopper amplifier and sampling scope.
9. (a) Distinguish between sampling gates and logic gates?
(b) Distinguish between unidirectional and bidirectional gates.
10. (a)With the help of a neat diagram, explain the working of two-diode sampling gate.
(b)Explain with circuit diagram the operation of a two input sampling gate which does not
have any
loading effect on control signal.
11. Derive expressions for gain and minimum control voltages of a bi-directional two- diode
sampling gate
12. (a)Draw the circuit of an emitter-coupled bidirectional sampling gate and explain.
(b) Draw the circuit of FOUR-DIODE sampling gate. Derive expressions for its gain(A) and
V .
min
Assignment7 :( From VII unit)
1. Define sweep speed error, transmission error and displacement error pertaining to sweep
circuits. Also
derive the expressions for the same with respect to an exponential sweep circuit.
2. (a) With a neat sketch, explain the frequency division by a factor of 2 in sweep generators.
(b)Explain the principle of “synchronization” and ‘synchronization with frequency division’
4. Describe frequency division employing a transistor monostable multivibrator with necessary
waveforms.
5. Explain with the help of block diagram and waveforms for achieving frequency division of
relaxation devices without phase jitter.
6. With the help of a circuit diagram and waveforms, explain frequency division of an astable
multivibrator
with pulse signals.
7. (a)With a neat circuit and waveforms explain the frequency division in blocking
oscillator.
(b). Describe the sine wave frequency division with a sweep circuit?
8. (a) Draw a simple single stage transistor Miller integration circuit and explain how it
behaves as a timebase circuit.
(b) Explain the method of pulse synchronization of relaxation devices, with examples.
9. (a) What do you mean by a relaxation circuit? Give few examples of relaxation circuits.
(b) With the help of neat waveforms, explain sine wave frequency division with a sweep
circuit.
10. (a) Describe the method involved in the synchronization of voltage sweep wave-form with a
sinusoidal
synchronization signal with neat waveforms.
(b) Describe the pulse synchronization of a stable relaxation circuit with neat sketches of
waveforms
11. With neat waveforms explain sine wave synchronization and compare it with pulse
synchronization.
12. (a) Explain how monostable multivibrator is used as frequency divider?
(b) Write short notes on
i) Phase delay
ii) Phase jitters.
Assignment8 :( From VIII unit)
1. (a) Give some applications of logic gates.
(b) Define positive and negative logic systems
2. (a) With reference to logic families, define:
i) Positive & negative logic system ii) Fan-in & fan-out
(b) Draw and explain the circuit diagram of a diode OR gate for positive logic.
3. (a) Realize two-input AND & OR gates using diodes and explain their operation with the help
of truthtables.
(b) Realize a three-input NOR gate using Resistor Transistor Logic and explain its operation
with the help
of truth-table.
4. (a) Draw and explain the circuit diagram of integrated positive DTL NAND gate
(b) Consider a two input positive logic diode OR and AND gates. Sketch the output waveform
for inputs
shown in figure 1.
Figure 1
5. (a)What are the basic logic gates which perform almost all the operations in digital
communication
systems.
(b)Draw a pulse train representing a 11010111 in a synchronous positive logic digital system
6. (a) Draw the circuit diagram of diode - resistor logic OR gate and explain its operation?
(b)Define level logic system and pulse logic system?
7. a) What is logical noise in a diode AND gate? Explain how it can be reduced by connecting a
clamping
diode in the circuit?
b) Realize NAND & NOR gates using CMOS Logic and explain their operation with the help
of truthtables.
8. a) Realize a two-input NAND gate using Diode Transistor Logic and explain its operation with
the help of
truth-table.
b) Explain the terms:
i) Wired- AND connection ii) Current Source – Sink logic iii) Tri-state logic
9. a) Realize a three-input NAND GATE using Transistor Transistor Logic. Explain its operation
with
Totem-pole load.
b) With reference to logic gates, explain the terms:
i) Fan-out ii) Noise- Margin iii) Propagation Delay iv) Figure of Merit
12.2: SLIP TESTS:
Slip tests are conducted in the class rooms.
8 slip tests are conducted per course.
3 questions are given for each slip test.
Instructions:
Slip test should be in written documents with the following requirements.
1) Cover page with name, roll number, course name and course section.
2) A page with questions.
3) Solutions/Explanations.
Slip Test1 :( From unit 1)
1. With neat waveforms explain the operation of a low-pass RC circuit for a pulse input.
Also derive expressions for the peak values of output.
2. (a) What is the function of a comparator? Explain its operation.
(b) Explain the response of a low pass circuit to an exponential input is applied.
3. a) Prove that for any periodic input waveform the average level of the steady state output
signal from the RC
high pass circuit is always Zero.
b) Draw the RC high pass circuit. With necessary waveforms and expressions explain its
working for a step
voltage input.
Slip Test2 :( From unit 2)
1. (a)Draw the diode differentiator comparator circuit and explain its operation when a ramp input
signal is
applied.
(b)Draw the basic circuit diagram of a DC restorer circuit and explain its operation
2. (a)Explain negative peak clipper with and without reference voltage.
(b)State and prove clamping circuit theorem
3. (a)Classify different types of clipper circuits. Give their circuits and explain their
operation with the aid
of transfer characteristics.
(b)Design a diode clamper circuit to clamp the positive peaks of the input signal at zero level.
The
frequency of the input signal is 500 Hz.
Slip Test3 :( From unit 3)
1. a) Explain the transistor switch in saturation region.
b) Explain the diode switching characteristics.
2. (a)Give a brief note on piece-wise linear diode characteristics.
(b) Describe the switching times of BJT by considering the charge distribution across the base
region.
Explain this for cut off, active and saturation regions
3. (a) Explain the terms pertaining to transistor switching characteristics.
i. Rise time.
ii. Delay time.
iii. Turn-on time.
iv. Storage time.
v. Fall time.
vi. Turn-off time.
Slip Test4 :( From unit 4)
1. (a)Describe multivibrators from the viewpoints of construction, principle of working,
classification
based on the output states, applications and specifications. Mention one specific application
of each.
(b)With reference to multivibrators, explain: i) stable-state ii) loop-gain iii) quasi stable-state
2. (a)What is a monostable multivibrator? Explain with the help of a neat circuit diagram the
principle of
operation of a monostable multi, and derive an expression for pulse width. Draw the wave
forms at
collector and Bases of both transistors.
(b)What is dead-band in a Schmitt trigger? Draw the hysteresis loop and explain how
hysteresis can be
eliminated in a Schmitt trigger.
3. (a)Draw and explain the circuit of Astable Multivibrator with necessary waveforms and also
derive the
expression for its frequency of oscillations.
(b)Explain the operation of emitter-coupled bistable multivibrator. Also discuss different
methods of
triggering a bistable multivibrator.
Slip Test5 :( From unit 5)
1. (a) Explain the principle of working of Miller sweep circuit. Derive the expression for sweep
speed
by taking Miller integrator circuit.
(b). Draw the circuit of a constant current sweep circuit and derive the expression for
sweep voltage.
2. (a) Draw the circuit of a Boot strap sweep generator and explain its operation. Derive an
expression for its
sweep time.
(b) Explain with a circuit the working of a UJT sweep circuit and obtain the expressions for the
intrinsic
standoff ratio (η).
3. (a) With the help of a neat circuit diagram and waveforms explain the working of a transistor
Bootstrap
time base generator.
(b) What is relaxation oscillator? Name some negative resistance devices used in relaxation
oscillators and
give its applications.
Slip Test6 :( From unit 6)
1.(a)Draw the circuit of two-diode bi-directional sampling gate. Explain its operation & derive
expressions
for gain and minimum control voltage in the circuit.
(b)Explain the application of sampling gate in a sampling scope.
2. a) Illustrate with neat circuit diagram, the operation of unidirectional sampling gate for
multiple inputs.
b) Explain with circuit diagram the operation of a two input sampling gate which does not have
any loading effect on control signal.
3. (a)Derive expressions for gain and minimum control voltages of a bi-directional twodiode sampling
gate.
(b)What is pedestal? How it effect the output of sampling gates?
Slip Test7 :( From unit 7)
1. a) Explain the principle of “synchronization” and ‘synchronization with frequency division’.
b) Explain the method of pulse synchronization of relaxation devices, with examples.
2. (a) Describe the method involved in the synchronization of voltage sweep wave-form with a
sinusoidal
synchronization signal with neat waveforms.
(b) Describe the pulse synchronization of a stable relaxation circuit with neat sketches of
waveforms
3. (a)Describe frequency division employing a transistor monostable multivibrator with necessary
waveforms.
(b)With a neat sketch, explain the frequency division by a factor of 2 in sweep generators
Slip Test8 :( From unit 8)
1.a) Realize two-input AND & OR gates using diodes and explain their operation with the help of
truthtables.
b) Realize a three-input NOR gate using Resistor Transistor Logic and explain its operation
with the help
of truth-table.
2.(a) Draw and explain the circuit diagram of integrated positive DTL NAND gate
(b) Consider a two input positive logic diode OR and AND gates. Sketch the output waveform
for inputs
shown in figure 1.
Figure 1
3. a) Realize a three-input NAND GATE using Transistor Transistor Logic. Explain its operation
with Totem-pole load.
b) With reference to logic gates, explain the terms:
i) Fan-out ii) Noise- Margin iii) Propagation Delay iv) Figure of Merit
(13)ASSESSMENT PLAN FOR ACTIONS:
13.1: Assessment plan for Assignments:
Content
Weightage
Problems
20%
Descriptive
70%
Analytical/
Reasoning
10%
13.2: Assessment plan for Slip Test:
Content
Weightage
Analyzing the
problems
10%
Theoretical
questions
80%
Reasoning
10%
(14)PROGRAM/OUTCOME MATRIX:
OBJECTIVES
Program Education Outcomes
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B
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D
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(15) COURSE/LABORATORY SCHEDULE:
2 hours of lecture class, 1 hour tutorial class, 3 hours laboratory
LIST OF CONTENTS
S.NO
NAME OF THE EXPERIMENT
LINEAR WAVE SHAPING
1
(LOW PASS & HIGH PASS FILTER)
NON- LINEAR WAVE SHAPING
2
(CLIPPERS)
NON- LINEAR WAVE SHAPING
3
(CLAMPERS)
4
BASIC LOGIC GATES & APPLICATIONS
5
TRANSISTOR AS A SWITCH
6
MONOSTABLE MULTIVIBRATOR
7
ASTABLE MULTIVIBRATOR
8
BISTABLE MULTIVIBRATOR
9
SCHMITT TRIGGER
10
FLIP-FLOPS
11
UJT RELAXATION OSCILLATOR
12
BOOTSTRAP SWEEP GENERATOR
(16) EXPERTS DETAILS:
NATIONAL:
1. Dr. Balasubrmanyam S K – Professor,
Department of Electronics Engineering IIT(BHU),
Varanasi.
Email:[email protected]
2. Dr.Banerjee Swapna,
Professor in electronics &EC engineering,
IIT Khragpur
Email: swapna [at] ece.iitkgp.ernet.in
INTERNATIONAL:
1. J. Millman ph.d and C.C.Halkias ph.dAssociate Professor of Electrical Engineering,
Columbia University
2. Prof. Trevor J.Trarnton,
Director of Center for Solid State Electronics Research,
Arizona State University, Tempe, USA
Email:[email protected]
REGIONAL:
1. P. John Paul
Dean Academics in Gurunanak Engineering College,
Hyderabad
2. K.Lal Kishore
Professor of ECE and Director of Academic and Planning,
JNTU Hyderabad
3. Suryaprakash Mothiki
Professor and head of the Deparment,Vishakapatnam, AP
17) MID AND FINAL EXAMINATION QUESTION:
17.1)PREVIOUS MID QUESTION PAPERS:
1. A semiconductor switch can be treated as [ ]
A) Switch activated from an external point
B) Voltage
controlled switch
C) Self activated switch
D) Low power
consuming switch
2. A Clipping circuit will not consist of the following element [ ]
A) Diodes
B) Transistor
C) Resistors
D) Capacitors
3. In the break region of a clipping circuit the diode behaves as an [ ]
A) Fully ON
B) it is difficult to decide
C) Fully OFF
D) neither fully
ON nor fully OFF
4. The purpose of linear wave shaping is [ ]
A) The input and output are always proportional in a circuit.
B) To generate non – sinusoidal waveforms from sine and square wave forms.
C) The rise and fall of the output waveform varies linearly with time.
D) The gain of the circuit is always real.
5. A Bistable multivibrator circuit [ ]
A) Has two unstable states
B) Has one energy –
storage element
C) Switches between its two states automatically
D) Is not a oscillator
6. The important applications of a bistable multivibrator are [ ]
A) Memory element and in combinational logic
B) Counting element and in
binary registers
C) Generation of clock pulses and synchronization pulses
D) As a memory element and counting element
7. It is difficult to clamp the following waveform in the diode clamping circuit [ ]
A) A train of broad pulses
B) A train of narrow pulses
C) Ramp waveform
D) High frequency sinusoidal
waveforms
8. When a sinusoidal waveform is transmitted through a RC high – pass filter, we find
that [ ]
A) The frequency of the wave form is altered.
B) The amplitude and phase of the
wave form is altered.
C) The slope of the wave form does not change.
D) The amplitude is not affected.
9. In a transistor bistable multivibrator the purpose of the collector – catching diodes is [ ]
A) To improve settling time of the bistable multivibrator
B) To protect the transistors from thermal runaway
C) To bypass a fraction of the large collector saturation current
D) To obtain uniform output swing at both the collectors
10. A transistor switch with an inductive load functions more like an [ ]
A) Integrator
B) Wide band amplifier
C) Differentiator
D)
Narrow band amplifier
II Fill in the blanks:
11. For a transistor the Turn-on time, Ton is given by ______________.
12. Clamping circuit theorem is mathematically expressed in the standard notation as
_____________
13. A Differentiator converts ‘triangular ’ wave into ‘_________’ wave
14. A low pass RC circuit acts an ___________________.
15. In symmetrical triggering the bistable multivibrator can make transitions in
__________directions
16. To induce a transition in bistable multivibrator it is very important to make sure that
trigger pulse is
applied to the___________ of the ________ transistor
17. A ramp waveform vi(t) = at during the interval 0 < t < T , is transmitted through the
RC low pass filter
with RC << T. The output wave form is vo(t) _________________
18. Limiting and slicing operations are performed by_________________ circuit
19. The reverse recovery time is the sum of __________ time and __________ time.
20. A transistor used as switches is operated in __________ and ___________region.
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II B.Tech. II Sem., I Mid-Term Examinations, Jan/Feb– 2011
PULSE AND DIGITAL CIRCUITS
Objective Exam
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.
I choose the correct alternative:
1) What is the response of step input to a high pass RC circuit [ ]
a) V e
-t/RC
b) V (1- e
t/RC
)
c) V e
t/RC
d) V (1- e
-t/RC
)
2) A comparator is a basic building block in a system used to analyze the -------- distribution of
noise generated
in active device [ ]
a) Both frequency and phase b) Amplitude
Frequency
c) Phase
d)
3) Common base configurations are little used because [ ]
a) High voltage gain b) High current gain
impedance
c) It has low input impedance
d) High input
4) The Vce (sat) of Si n-p-n transistor at 27 c is [ ]
a) 0.7 v
b) 0.3 v
c) 0.8 v
d) 0.1 v
c) Sine wave
d)
5) Monostable multivibrators generates [ ]
a) Pulse wave form
Square wave
b) Ramp signal
6) When RC high pass circuit act as a differentiator? [ ]
a) RC<<T
d)RC=0
b) RC>>T
c)RC=T
7) The reverse saturation current increases approximately for every ------- rise in temperature [ ]
a) 30 c
b) 50 c
c) 70 c
d) 10 c
8) Zener diode has ---------- temperature coefficient [ ]
a) some times positive and sometimes negative
c) Both positive and negative
b) Only negative
d) Only positive
9) Turn off time of the transistor is = ------- [ ]
a) toff =tf +ts
d) toff =ton +ts
b) toff =tf +ton
c) toff =tfd +ts
10) What is the name of the circuit which converts square wave in to spikes [ ]
a) Low pass RC
shot
b) Bi stable multi
c) High pass RC
d) Mono
II Fill in the blanks:
11) For DC input signal capacitor C acts as a ___________
12) The average value of the output value of an RC high pass circuit is _________
13) In RC integrator circuit the output is taken across -------14) The clamping theorem is given by -------15) No of quasi stable states of astable is---------16) The percentage tilt in the response of a square wave input to a RC differentiator circuit is
given by
17) The current flowing through the capacitor when the voltage across the capacitor is V
__________
18) The expression of pulse width for monostable multivibrator is ____________
19) When the diode is forward biased it acts as ____________
20) The out put voltage Vo of RC differentiator for input Vi is ____________
Code No: 07A4EC07
Set No. 1
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II B.Tech. II Sem., I Mid-Term Examinations, March – 2010
PULSE AND DIGITAL CIRCUITS
Objective Exam
Answer All Questions. All Questions Carry Equal Marks.
Time: 20 Min. Marks: 20.
I. Choose the correct alternative:
1. The lower cutoff frequency of a low pass RC circuit is [ ]
(a) 0
(b) 2πRC
(c) 1/2πRC
(d) infinity
2. The transmission error at the end of the ramp input is defined as [ ]
(a) output inputoutput− ( b ) inputinputoutput− ( c ) outputoutputinput− ( d )
inputoutputinput−
3. The output of an attenuator is ‘n’ times the input, then the rise time of output is [ ]
( a ) n/2 times the rise time of the input ( b ) n times the rise time of the input
( c ) n/2 times the fall time of the output ( d ) n times the fall time of the output
4. Clipping circuits do not require [ ]
( a ) diodes ( b ) resistors ( c ) transistors ( d ) storage devices
5. A non regenerative comparator is [ ]
( a ) clipper ( b ) clamper ( c ) Schmitt trigger ( d ) low pass filter
6. Which of the following circuit is used to convert a sine wave into square wave [ ]
( a ) clipper ( b ) clamper ( c ) bistable multivibrator ( d ) astable multivibrator
7. The loop gain of a Schmitt trigger to eliminate hysteresis is [ ]
( a ) <1 ( b ) >1 ( c) =1 ( d ) = infinity
8. Which of the following multivibrator can be used as voltage to frequency converter? [ ]
( a ) Bistable ( b ) monostable ( c ) astable ( d ) Schmitt trigger
9. The turn off time of a transistor is [ ]
(a) storage time + rise time (b) rise time – fall time (c) storage time + fall time (d) delay time +
rise time
10. For double differentiation, two high –pass networks are connected in cascade with time
constants of [ ]
( a ) first one is small and second is large ( b ) first one is large and next is small
( c ) both are small ( d ) both are large
II Fill in the blanks:
11. High-pass circuit is treated as a differentiator, if the phase shift between the input and
output is at least ___________
12. The dc component introduced in a clamping circuit is ________ the dc component lost
during transmission
13. The condition for perfect compensation of an attenuator is ________
14. The clamping circuit theorem states that __________
15. It is not possible to clamp the _________ pulses precisely
16. The time required for Ic to fall from 90% to 10% saturation level is called the __________
17. The breakdown voltage of a diode depends on _________ of junction
18. Large commutating capacitors are ________ the transition time
19. In the stable state the loop gain is __________
20. For astable operation, the load line must intersect the V-I characteristic at one point on the
_________ portion
of the characterstic
Code No: 54021
Set No. 1
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II B.Tech. II Sem., I Mid-Term Examinations, February – 2012
PULSE AND DIGITAL CIRCUITS
Objective Exam
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.
I Choose the correct alternative:
1. The waveform which preserves its form when transmitted through a linear network is a
___________. [ ]
(a) Sine wave (b) Step signal (c) impulse signal (d) ramp signal
2. An RC high pass circuit has R= 1kΩ and C=0.5 μF. Its lower cutoff frequency is [ ]
(a) zero (b) 318.3 Hz (c) 1kHz (d) infinity
3. A clipping circuit consists of ___________. [ ]
(a) Resistor (b) Diode (c) both a and b (d) c and capacitor
4. For a integrator, if input is square wave then the output waveform is _____ [ ]
(a) Impulse (b) Sawtooth wave (c) Triangular wave (d) Both a and c
5. Gain of integrator ________ with frequency. [ ]
(a) decreases (b) increases (c) both a and b (d) no change
6. A clamping circuit is also called as ____________. [ ]
(a) dc restorer (b) dc reinserter (c) both a and b (d) none of the above
7. A sinusoidal waveform can be converted to a square waveform by using _______ [ ]
(a) Astable multivibrator (b) Bistable multivibrator
(c ) Schmitt trigger (d) None of the above
8. A Schmitt trigger is a __________. [ ]
(a) counter (b) Voltage to frequency converter
(c) Comparator (d) None of the above
9. A ringing circuit has a quality factor Q=24. This circuit will ring for how many number of
cycles? [ ]
(a) 24 (b) 12 (c) 8 (d) 6
10. The rise time of the output of a low pass RC circuit is given by [ ]
(a) 2.2 RC (b) 0.35/f (c) 2.2τ (d) all the above
H
II Fill in the blanks:
11. _____________ is the condition for an RC high pass circuit to acts as a differentiator.
12. Time constant of RL circuit is ____________.
13. Write the clamping circuit theorem ________________
14. Rise time of a Low pass filter is ________________________.
15. The time constant of a monostable multivibrator is __________________.
16. _____________ is called as a free running oscillator.
17. A bistable multivibrator is used for ____________________.
18. _______________ circuit is used to generate the sequence of pulses which are regularly
spaced in time.
19. The process of converting pulses into spikes is called _____________.
20. Write the relationship between time constant and tilt?
Code No: 54021
Set No. 1
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II B.Tech. II Sem., I Mid-Term Examinations, February – 2013
PULSE AND DIGITAL CIRCUITS
Objective Exam
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.
I Choose the correct alternative:
1. Zener break down occurs at voltages below [ ]
A) 6V B) 7V C) 8V D) 5V
2. The hfe of transistor ----- with the temperature [ ]
A) increases B) decreases C) constant D) sometimes increases and decreases
3. Clipping circuits are also called [ ]
A) voltage limiters B) amplitude selectors C) slicers D) all
4. The rise time is --- to the upper 3-db frequency [ ]
A) directly proportional B) inversely proportional C) constant D) none
5. The passive elements are [ ]
A) voltage source B) current source C) resistance D) both a and b
6. Under steady state conditions which of the following blocks dc or any voltage which maintains
a constant level of magnitude [ ]
A) Inductor B) capacitor C) resistor D) all of the above
7. The forward resistance of an ideal diode is [ ]
A) zero B) infinitely large
C) infinitely small D) None
8. For n-p-n transistor, the saturation region for Vce(sat) ON state [ ]
A) 0.3V for silicon transistor, 0.1V for germanium transistor
B) 0.1V for silicon transistor, 0.3V for silicon transistor
C) 0.7V for silicon transistor, 0.3V for silicon transistor
D) 0.3V for silicon transistor, 0.7V for silicon transistor
9. A HPF circuit having phase shift between input and output is at least [ ]
o
o
o
o
A) 89.7 B) 89.4 C) 77.2 D) 67.2
10. A monostable multivibrator has [ ]
A) one stable states and two quasi stable states B) one quasi stable states and two stable
states
C) one quasi stable states and one stable states D) two quasi stable states and two
stable states
II Fill in the blanks:
11. When a sinusoidal voltage is applied to the linear circuit, the output voltage is ________ in
nature.
12. In order to minimize distortion, the time constant must be very large compared to
__________
13. The reverse resistance of an ideal diode is ___________
14. The diode conducts when forward biased and the bias voltage is _______ than cut in
Voltage.
15. The _________ circuit is often referred as dc restorer.
16. The turn- off time of a transistor is the sum of ________ time and _________ time.
17. The attenuator is _________ to make output independent of frequency.
18. __________ Circuits are used to select for transmission that part of an arbitrary wave form
which lies above
or below some particular reference voltage level.
19. At low currents, the diode is represented by a __________ combination
20. __________ may be non- regenerative.
Code No: 07A4EC07
Set No. 1
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II B.Tech. II Sem., II Mid-Term Examinations, April/May – 2010
PULSE AND DIGITAL CIRCUITS
Objective Exam
Answer All Questions. All Questions Carry Equal Marks.
Time: 20 Min. Marks: 20.
I Choose the correct alternative:
1. The relation between the slope error, displacement error and transmission error is [ ]
( a )et=2es=8ed ( b ) 2et= ed=8es ( c ) 8et= 2ed= es ( d ) 2et=8ed=es
2. To get a saw-tooth out put waveform, the restoration time is [ ]
( a ) zero ( b ) rise time ( c ) storage time ( d ) infinity
3. In Miller time base generator, which of the following is used [ ]
(a) an inverting amplifier with a gain of unity (b) an inverting amplifier with a gain of
infinity
(c) non-inverting amplifier with a gain of unity (d) non-inverting amplifier with a gain of
infinity
4. Synchronization with symmetrical signals is possible for [ ]
( a ) Tp = To only ( b ) Tp<To only ( c ) Tp >To only ( d ) both Tp<To and Tp> To
5. The time during which the output increases linearly is called [ ]
( a ) sweep time ( b ) flyback time ( c ) return time ( d ) restoration time
6. The interval of time of transmission of a signal in a sampling gate is selected by means of [ ]
( a ) time delay ( b ) off time of gate ( c ) gating signal ( d ) source signal
7. The following all are disadvantages of unidirectional gate, except [ ]
( a ) interaction between the signal source and control voltage source ( b ) limited used
of gate
( c ) slow rise of the control voltage ( d ) little time delay though the gate
8. Which of the following logic gives the complementary outputs? [ ]
( a ) DTL ( b ) RTL ( c ) TTL ( d ) ECL
9. The voltage at the input of a gate which causes a change in the state of the ouput from one
logic level totheotheris [ ]
( a ) cut-in voltage ( b ) cut-off voltage ( c ) threshold voltage ( d ) peak voltage
10. The high state fan out of a gate is defined at when the [ ]
( a ) input is at logic ‘0’ ( b ) input is at logic ‘1’
( c ) output is at logic ‘1’ ( d ) output is at logic ‘0’
II Fill in the blanks:
11. The time required by the sweep voltage to return to the initial value is called
______________
12. Compensating networks used to improve the ____________ of bootstrap circuit
13. The output of a time-base generator is called ____________
14. The range of synchronization decreases with _____________ of sync signal amplitude
15. When generator with equal frequencies run in synchronism, the synchronization is said to be
on ________
16. Bidirectional sampling gates transmit signals in ____________
17. The sampling gate is used in sampling scope because the display consists of _________
18. The power required by the gate to operated with 50% duty cycle at a specified frequency is
called ______
19. High state nose margin of a gate is defined as ____________
20. The basic TTL gate is _____________
II B.Tech. II Sem., II Mid-Term Examinations, March/April – 2011
PULSE AND DIGITAL CIRCUITS
Objective Exam
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.
I Choose the correct alternative:
1) The time during which the waveform returns to the initial value is called: [ ]
(a) fall time (b) flyback time (c) rise time (d) delay time
2) The circuit which require an amplifier whose gain is nearly infinity [ ]
a) Boot strap ckt b) Miller ckt c) Phantastron ckt d) Inductor ckt
3) When generators with equal frequencies run in synchronism ,the synchronization is said to be
on a [ ]
a) one-to-one basis b) one-to-two basis c) two-to-one basis d) one-to-four basis
4) A Transmission circuit which allows an input Signal to pass through it during a selected
interval and blocks it
passage outside this time interval is called : [ ]
a)sampling gates b) conventional gates c) non-conventional gates d) logic gates
5) In unidirectional sampling gate the combination of RC forms a [ ]
a)Differentiator b) Integrator c) Coupling elements d) Multivibrator
6) The ratio of maximum deviation to the sweep amplitude is called [ ]
a)slope error (b) displacement error (c) Transmission error (d) Linear error
7) A capacitor is charged linearly from a constant current source is used to generate [ ]
a)sine wave form (b) pulse wave form (c) time base waveform (d) trapezoidal wave form
8) The several factors which affect phase delay given rise to [ ]
a)phase jitter b)amplitude jitter c)both amplitude and phase jitter d)frequency jitter
9) The interval of time is selected by means of an externally applied signal termed as: [ ] a)
transient signal b) gating signal c) output signal d)exponential signal
10) Logic gates are the basic elements that make a [ ]
a) analog system b) gating system c) basic system d)digital system
II Fill in the blanks:
11) The maximum number of gates that can be driven by any logic gate is called __________
12) If synchronization is achieved with different frequencies, i.e one frequency being n times the
other, then it is termed----------------------13) Two or more generators are said to be running _______________ if all of them arrive at
some point in the cycle at exactly the same instant of time.
14) _____________gates are used in chopper amplifiers
15) In ____________logic system, the higher of the two voltage levels represent logic 1 and
lower logic is 0
16) A _____________________ is one that provides an output voltage waveform a portion of
which exhibits a linear portion with time
17) The ratio of the difference in slope at beginning and end of the sweep to initial value of
slope is called ________
18) Sampling gates are classified into___________types
19) Chopper often called as __________
20) A positive logic NOR gate is equivalent to negative logic ________gate
Code No: 54021
Set No. 1
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II B.Tech. II Sem., II Mid-Term Examinations, April – 2012
PULSE AND DIGITAL CIRCUITS
Objective Exam
Answer All Questions. All Questions Carry Equal Marks.
Time: 20 Min. Marks: 10.
I Choose the correct alternative:
1. Bootstrap’s sweep circuit produces _____ type of waveform. [ ]
(a) positive going Ramp (b) negative going Ramp
(c) either a or b (d) Both a and b
2. The gate signal is also called as ___________. [ ]
(a) enabling pulse (b) control pulse (c) both a and b (d) either a or b
3. Sampling gates are used in _______. [ ]
(a)Multiplexers (b) D to A converters
(c) Sample and Hold circuits (d) All the above
4. The variations in phase delay occur due to ____. [ ]
(a) variations in loop gain (b) variations in supply voltage
(c) both a and b (d) None
5. Among the logic families, low power dissipation is in _____. [ ]
(a)DTL (b) CMOS (c) TTL (d) ECL
6. Synchronization is said to be with frequency division, if the generators operate at___ [ ]
(a) same frequency (b) different frequency (c) both a and b (d) None
7. Synchronization with symmetrical signals is possible if_______. [ ]
(a) T <= T (b) T >= T (c) both a and b (d) either a or b
p
0
p
0
8. Which of the following logic family has highest fan-out. [ ]
(a) ECL (b) TTL (c) DTL (d) CMOS
9. Among the logic families, Slowest logic family is_____. [ ]
(a)TTL (b)DTL (c)CMOS (d)ECL
10. In Miller circuit, the gain A of the inverting amplifier should be ____. [ ]
(a) unity (b) zero (c) infinite (d) None of the above
II Fill in the blanks:
11. The ratio of the difference between the input and the output to the input at the end of the
sweep time is called _____________________.
12. The output of the time base generator is called _____________.
13. The gain of a sampling gate is defined as ____________.
14. ___________ is a transmission circuit in which the output is an exact replica of input
waveform during
selected time interval and is zero otherwise.
15. The periodic variations in the phase delay are called _________.
16. The range of synchronization increases with increasing _____.
17. The relation between slope error and transmission error is ____________
18. Typical noise margin for DTL family is _______.
19. CML is also called as ___________.
20. In a 4-diode sampling gate, minimum value of Vc is given by ____________.
Code No: 54021
Set No. 1
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II B.Tech. II Sem., II Mid-Term Examinations, April – 2013
PULSE AND DIGITAL CIRCUITS
Objective Exam
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.
I Choose the correct alternative:
1. The most important application of a time-base generator is in [ ]
A) TVs B) radar displays C) CROs D) time measurements
2. In a miller circuit, the amplifier gain A should be [ ]
A) infinite B) finite C) unity D) zero
3. The _____ networks may be used to improve the linearity of miller and bootstrap circuits [ ]
A) RLC series B) RLC parallel C) compensating D) linear
4. A ____________ circuit converts a pulse input into a ramp [ ]
A) bootstrap B) phantastron C) miller D) RLC
5. A chopper amplifier is used to amplify signals of the order of [ ]
A) micro volts B) milli volts C) volts D) hundreds of volts
6. A circuit which generates non sinusoidal waveforms is called [ ]
A) relaxation oscillator B) square wave generator
C) non-sinusoidal oscillator D) none of these
7. The _________ is defined as the ratio of the difference in slope at the beginning and end of
the sweep to
the initial value of slope [ ]
A) slope error B) Displacement error C) transmission error D) none of these
8. The advantage of bidirectional gate over unidirectional gate is [ ]
A) linearity of operation B) efficiency C) non linearity D) cost
9. Fan-out of a standard TTL device driving 74LS device is [ ]
A) 5 B) 15 C) 10 D)20
10. The fastest saturated logic family is [ ]
A) TTL B) ECL C) IIL D) MOS
II Fill in the blanks:
11. A Boot strap circuit employs ___________________ feed back.
12. In a boot strap sweep circuit, the amplifice gain A should be _______________
13. The interval of time of transmission of a signal is selected by means of an externally applied
signal
termed as a _____________________
14. The several factors which affect the phase delay give rise to ___________
15. The chopper is often called a _____________
16. The ____________ is defined as the ratio of the difference between the input and the
output to the input
at the end of the sweep
17. The ___________ is defined as the ratio of the maximum difference between the actual
sweep voltage
and the linear sweep to the amplitude of the sweep.
18. ____________ is a measure of the power consumed by the logic gate when fully driven by all
its inputs,
and it is expressed in milli watts or nano watts.
19. ____________ is defined as the no. of inputs that a logic gate can drive without exceeding its
worst case
loading specifications.
20. ____________ is the non-saturated digital logic family
-oOo-
(17.2)PREVIOUS FINAL QUESTION PAPERS:
Code No: R09220403
R09
SET-3
B.Tech II Year - II Semester Examinations, December-2011 / January-2012
PULSE AND DIGITAL CIRCUITS
(COMMON TO BIO-MEDICAL ENGINEERING, ELECTRONICS & COMMUNICATION ENGINEERING,
ELECTRONICS & TELEMATICS ENGINEERING)
Time: 3 hours
Max. Marks: 80
Answer any five questions
All questions carry equal marks
--1. a) Explain RC double differentiator circuit.
b) An oscilloscope displays a 5Hz square wave with 6% tilt. The signal input has no tilt and is
coupled to
the oscilloscope via a 4.7μF capacitor. Calculate the input resistance of oscilloscope.
c) Draw the basic ringing circuit. Explain how it provides undamped oscillations. [5+5+5]
2. a) Draw the basic circuit diagram of a DC restorer circuit and explain its operation.
b) For the circuit shown in Figure.1, a sine wave input of 100V peak is applied. Sketch the
output voltage V to the same time scale & transfer characteristic. Assume ideal diodes.
O
[10+5]
Figure.1
3.a) Explain the phenomenon of “latching” in a transistor switch.
b) For the CE transistor circuit shown in Figure.2, V = 15V and R = 1.5K. Calculate the
CC
C
power dissipation in the transistor, when it is in
i) cut-off ii) saturation. [5+10]
Figure.2
4.a) With reference to multivibrators, explain: i) stable-state ii) loop-gain iii) quasi stable-state
b) Design a collector coupled astable multivibrator for the following specifications with silicon
transistor. IC (sat) = 10mA; hfe (min) = 20; VCC =10V; pulse width=10μsec; duty cycle = 40%.
[6+9]
5. Define sweep speed error, transmission error and displacement error pertaining to sweep
circuits. Also derive the expressions for the same with respect to an exponential sweep circuit.
[15]
6. Describe multivibrators from the viewpoints of construction, principle of working,
classification based on the output states, applications and specifications. Mention one
specific application of each.
7.a) Draw the circuit of two-diode bi-directional sampling gate. Explain its operation & derive
expressions for gain and minimum control voltage in the circuit.
b) Illustrate the principle of sampling gates with series and parallel switches and compare
them. [8+7]
8.a) Explain about DTL NAND gate.
b) Give some applications of logic gates.
c) Define positive and negative logic systems. [8+3+4]
Code No: R09220403
R09
SET-1
B.Tech II Year - II Semester Examinations, December-2011 / January-2012
PULSE AND DIGITAL CIRCUITS
(COMMON TO BME, ECE, ETM)
Time: 3 hours Max. Marks: 80
Answer any five questions
All questions carry equal marks
--1. What is an attenuator? Draw the circuit of compensated attenuator. While sketching the
response of compensated attenuator for perfect compensation, over compensation and
under compensation, show that the condition for perfect compensation is R C = R C .
1 1
2 2
[15]
2.a) Draw the diode differentiator comparator circuit and explain its operation when a ramp
input signal is applied.
b) For a shunt diode clipper circuit V = 20 sin ωt, V = 10V is obtained from a potential divider
i
R
circuit using 100V supply and 10K potentiometer
i) Draw the circuit diagram.
ii) If R = 50Ω, R = ∞ and V = 0, sketch the transfer characteristic, output waveform for
f
r
γ
the given V . [7+8]
i
3.a) Explain how transistor can be used as a switch in the circuit, under what condition a
transistor is said to be ‘OFF’ and ‘ON’ respectively.
b) A germanium transistor is operated at room temperature in the CE configuration. The
supply voltage is 6 V, the collector-circuit resistance is 200 Ω and the base current is 20
percent higher than the minimum value required driving the transistor into saturation.
Assume the following transistor parameters: [7+8]
I = -5μA, I = -2μA, h = 100, and r = 250Ω. Find V (Sat) and V (Sat).
co
EO
FE
bb'
BE
CE
4.a) With reference to multivibrators, explain:
i) stable-state ii) loop-gain iii) quasi stable-state
b) Design a collector coupled astable multivibrator for the following specifications with silicon
transistor. I (sat) = 10mA; h (min) = 20; V =10V; pulse width=10μsec; duty cycle=40%.
C
fe
CC
[6+9]
5.a) Draw a bootstrap sweep circuit using Darlington pair. Explain its operation with neat
waveforms; also mention its merits and limitations?
b) Briefly describe various methods to achieve sweep linearity in time-base circuits. [10+5]
6.a) With the help of a circuit diagram and waveforms, explain frequency division of an astable
multivibrator with pulse signals.
b) With a neat sketch, explain the frequency division by a factor of 2 in sweep generators.
[10+5]
7.a) For the four-diode sampling gate shown in figure.1, Vs = 25V, R = 50Ω, R = Rc =100KΩand
f
R2 = 2KΩ. Find (Vc) , A, V
min
min
and (Vn)
min
L
for V = V ?
min
Figure.1
b) Explain the application of sampling gate in a sampling scope. [10+5]
8.a) With reference to logic families, define:
i) Positive & negative logic system ii) Fan-in & fan-out
b) Draw and explain the circuit diagram of a diode OR gate for positive logic. [8+7]
********
Code No: R09220403
R09
set-2
B.Tech II Year - II Semester Examinations, December-2011 / January-2012
PULSE AND DIGITAL CIRCUITS
(COMMON TO BIO-MEDICAL ENGINEERING, ELECTRONICS & COMMUNICATION ENGINEERING,
ELECTRONICS & TELEMATICS ENGINEERING)
Time: 3 hours
Max. Marks: 80
Answer any five questions
All questions carry equal marks
---
1.a) Draw the series RLC circuit and derive expression for its transfer function.
b) A ramp input, shown in Figure.1 is applied to a high-pass RC circuit. Draw to scale the
output waveform for the following cases:
i) T = 0.2 RC ii) T = 10 RC
[7+8]
Figure.1
2.a) A square wave input as shown in figure.2 is applied to a negative clamper circuit. Sketch the
steady-state output waveform and derive the necessary expressions.
Figure.2
b) Explain negative peak clipper with and without reference voltage. [10+5]
3.a) With neat sketches and necessary equations, explain in detail about transistor switching
times.
b) Explain Zener & Avalanche breakdown mechanisms in diodes. [10+5]
4. Explain the operation of emitter-coupled bistable multivibrator. Also discuss different
methods of triggering a bistable multivibrator. [15]
5. Define sweep speed error, transmission error and displacement error pertaining to sweep
circuits. Also derive the expressions for the same with respect to an exponential sweep
circuit. [15]
6.a) Define the terms synchronization and frequency division.
b) Describe frequency division employing a transistor monostable multivibrator with necessary
waveforms. [5+10]
7.a) For the four-diode sampling gate shown in figure.3, Vs = 25V, R = 50Ω, R = Rc =100KΩ and
f
R2 = 2KΩ. Find (Vc) , A, V
min
min
and (Vn)
min
for V = V ?
min
L
Figure.3
b) Explain the application of sampling gate in a chopper amplifier. [10+5]
8.a) Realize two-input AND & OR gates using diodes and explain their operation with the help of
truth-tables.
b) Realize a three-input NOR gate using Resistor Transistor Logic and explain its operation
with the help of truth-table. [8+7]
********
Code No: R09220403
R09
Set-4
B.Tech II Year - II Semester Examinations, December-2011 / January-2012
PULSE AND DIGITAL CIRCUITS
(COMMON TO BIO-MEDICAL ENGINEERING, ELECTRONICS & COMMUNICATION ENGINEERING,
ELECTRONICS & TELEMATICS ENGINEERING)
Time: 3 hours Max. Marks: 80
Answer any five questions
All questions carry equal marks
--1.a) Prove that an RC circuit behaves as a reasonably good integrator if RC > 15T, Where T is
the period of an input ‘E sin ωt’.
m
b) What is the ratio of the rise time of the three sections in cascade to the rise-time of Single
section of low pass RC circuit? [8+7]
2.a) State and prove clamping circuit theorem.
b) Determine Vo for the network shown in Figure.1 for the given 16V P-P sine wave input. Also
sketch the transfer characteristics. (Assume ideal diodes). [5+10]
Figure.1
3.a) Explain the transistor switch in saturation region.
b) Explain the diode switching characteristics. [8+7]
4. Design a Schmitt trigger circuit using n-p-n silicon transistors to meet the following
specifications: V =12V, UTP=4V, LTP=2V, h =60, I =3mA. Use relevant assumptions and
cc
fe
C2
the empirical relationships. [15]
5.a) Draw the circuit of a constant current sweep circuit, explain its operation and derive the
expression for sweep voltage.
b) Explain the principle of working of Miller sweep circuit. Derive the expression for sweep
speed by taking Miller integrator circuit. [8+7]
6.a) Explain the principle of “synchronization” and ‘synchronization with frequency division’.
b) Explain with the help of block diagram and waveforms for achieving frequency division of
relaxation devices without phase jitter. [8+7]
7.a) For the four-diode sampling gate shown in Figure.2, Vs = 25V, R = 50Ω, R = Rc =100KΩand
f
R2 = 2KΩ. Find (Vc)
, A, V
min
min
and (Vn)
min
for V = V ?
min
Figure.2
b) Explain the application of sampling gate in a sampling scope. [10+5]
8.a) With reference to logic families, define:
i) Positive & negative logic system
ii) Fan-in & fan-out
L
b) Draw and explain the circuit diagram of a diode OR gate for positive logic. [8+7]
********
Code No:09A51002
R09
Set-1
B. Tech III Year I Semester Examinations, December-2011
PULSE AND DIGITAL CIRCUITS
(COMMON TO ELECTRONICS AND INSTRUMENTATION
ENGINEERING, INSTRUMENTATION AND CONTROL ENGINEERING)
Time: 3 hours
Max. Marks: 75
Answer any five questions
All questions carry equal marks
1.a) A symmetrical square wave whose peak-to-peak amplitude is 2V
and whose average value is zero as applied to on RC integrating
circuit. The time constant is equals to half -period of the square
wave. Find the peak to peak value of the output amplitude. Also
sketch the output waveform.
b) Derive the expression for percentage tilt for a square wave output of
RC high pass circuit. [8+7]
2.a) A square wave input of period T=1000 μ sec, Vpeak = 10V and Duty
cycle = 0.2 is applied to the circuit shown in figure.1. Given, RS =
100Ω, C = 1μF, R = 10K & Diode forward resistance, Rf = 100Ω.
i. Sketch the output waveform with voltage levels at steady state.
ii. Forward and reverse direction tilt
iii. Af / Ar
Figure.1
b) Write a short note on voltage comparators. [10+5]
3.a) Write about diode switching times.
b) Explain Zener & Avalanche breakdown mechanisms in diodes. [7+8]
4. Draw and explain the circuit of Astable Multivibrator with necessary
waveforms and also derive the expression for its frequency of
oscillations. [15]
5.a) Draw the circuit of a constant current sweep circuit and derive the
expression for sweep voltage.
b) Explain the principle of working of Miller sweep circuit. Derive the
expression for sweep speed by taking Miller integrator circuit. [8+7]
6.a) With the help of a circuit diagram and waveforms, explain frequency
division of an astable multivibrator with pulse signals.
b) Describe synchronization with 2:1 frequency division with neat waveforms. [8+7]
7.a) Illustrate with neat circuit diagram, the operation of unidirectional
sampling gate for multiple inputs.
b) Derive expressions for gain and minimum control voltages of a bidirectional two- diode sampling gate. [7+8]
8.a) Define positive and negative logic system
b) Define fan-in and fan-out
c) Draw and explain the circuit diagram of a diode OR gate for positive
logic. [4+4+7]
--ooOoo—
Code No: RR221003
RR
SET-1
B.Tech II Year - II Semester Examinations, December-2011 /
January-2012
PULSE AND DIGITAL CIRCUITS
(ELECTRONICS & INSTRUMENTATION ENGINEERING)
Time: 3 hours Max. Marks: 80
Answer any five questions
All questions carry equal marks
--1.a) With neat waveforms explain the operation of a low-pass RC circuit for a
pulse input. Also derive expressions for the peak values of output.
b) A 10 HZ symmetrical square wave whose peak -to peak amplitude is
2V is applied as an input to a high-pass RC circuit whose lower 3dB frequency is 5HZ. Calculate and sketch the output wave form.
[8+8]
2.a) State and prove clamping circuit theorem.
b) Determine Vo for the network shown in Figure.1 for the given 16V PP sine wave input. Also draw its transfer characteristics. (Assume
ideal diodes). [6+10]
Figure.1
3.a) For a CE transistor circuit shown in Figure.2, VCC = 15V, RC= 1.5K
and IB = 0.3mA. Determine the minimum value of hFE required for
saturation to occur.
Figure.2
b) Explain how transistor can be used as a switch in the circuit, under
what condition a transistor is said to be ‘OFF’ and ‘ON’
respectively. [10+6]
4.a) Draw the circuit of compensated attenuator. Obtain the condition for
perfect compensation?
b) Explain the operation of an emitter coupled monostable multivibrator.
[8+8]
5.a) What is dead-band in a Schmitt trigger? Draw the hysteresis loop and
explain how hysteresis can be eliminated
in a Schmitt trigger.
b) Silicon transistors with hfe(min) = 20 are available. Design a bistable
multivibrator for the following
specifications, VCC = 15V; V0 = 10VP-P ; IC(sat) = 10mA; ICBO = 0mA,
VCE(sat)=0.3V; VBE(off) = -5V. [6+10]
6.a) Draw the circuit of exponential sweep circuit. Derive expressions for
sweep speed error, es and transmission
error, et.
b) Define the terms ‘synchronization’ and ‘frequency division’. [12+4]
7.a) With neat waveforms, explain how an astable multivibrator can be
synchronized?
b) A transistor bootstrap ramp generator is to produce a 15V, 5ms
output to a 2KΩ load resistor. The ramp is to be linear within 2%.
Design a suitable circuit using Vcc = 22V, −VEE = -22V and
transistor with hfe(min) = 25. The input pulse has an amplitude of -
5V, pulse width = 5ms and space width = 2.5ms. [8+8]
8.a) With neat sketches explain the operation of base-timing monostable
blocking oscillator. Derive expression for its pulse width?
b) For the four-diode sampling gate (with a divider resistance, R) shown in
Figure.3, V =25V, Rf = 20Ω, RL = Rc = 200KΩ and R = 100Ω. Find
s
(Vc)min, and (Vn)min? [10+6]
Figure.3
**********
Code No:RR210202
RR
SET-1
B.Tech II Year - I Semester Examinations, December 2011
PULSE AND DIGITAL CIRCUITS
(COMMON TO ELECTRICAL AND ELECTRONICS ENGINEERING,
ELECTRONICS AND COMMUNICATIONS ENGINEERING)
Time: 3 hours
Max. Marks: 80
Answer any five questions
All questions carry equal marks
--1.a) Draw the output waveform of an RC High pass circuit with a square
wave input under different time constants. Explain the same.
b) Prove that for any square wave input waveform the average level of the
steady state output signal from the RC high pass circuit is always Zero.
[8+8]
2.a) Classify different types of clipper circuits. Give their circuits and
explain their operation with the aid of transfer characteristics.
b) Design a diode clamper circuit to clamp the positive peaks of the input
signal at zero level. The frequency of the input signal is 500 Hz. [8+8]
3.a) Give a brief note on piece-wise linear diode characteristics.
b) Describe the switching times of BJT by considering the charge
distribution across the base region. Explain this for cut off, active and
saturation regions. [8+8]
4.a) Discuss the symmetrical and Asymmetrical triggering in case of
Bistable tran sistor multivibrator.
b) A transistor Schmitt trigger uses n-p-n silicion transistors with
hfe(min)=30
Vce(sat)=0.1v,VBE(sat)=0.7v,Vcc=12v,Rc1=2k
Rc2=1k,
R1=20k, R2=100k, Re=500,Rs=2k. Draw the circuit diagram. Calculate
all the steady-state currents & voltages. [8+8]
5.a) What is meant by triggered sweep? What are the merits and demerits
of triggered sweep circuits?
b) In the current sweep circuit used for TV, the transistor used must
operate as a bidirectional switch. Explain. [8+8]
6. With a neat circuit and waveforms explain the frequency division in
blocking oscillator. [16]
7.a) Explain the operation of unidirectional diode sampling gate with neat
sketch of waveforms. Illustrate the effect of different levels of control
voltage on gate output.
b) State the effects of circuit capacitances? [10+6]
8.a) Draw a simple single stage transistor Miller integration circuit and
explain how it behaves as a time-base circuit.
b) Explain the method of pulse synchronization of relaxation devices,
with examples. [8+8]
********
Code No: R05221101
Set No. 2
R05
II B.Tech II Semester Examinations,Dec/Jan 2011
PULSE AND DIGITAL CIRCUITS
Common to Bio-Medical Engineering, Instrumentation and Control
Engineering, Electronics and Computer Engineering, Electronics and Control
Engineering
Time: 3 hours
Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
1. (a) What is the function of a comparator? Explain its operation.
(b) Explain the response of a low pass circuit to an exponential input is applied.
(c) Explain the response of RL circuit when a rectangular pulse is applied [4+6+6]
2. (a) Draw and explain the circuit diagram of integrated positive DTL NAND gate
(b) Consider a two input positive logic diode OR and AND gates. Sketch the output waveform
for inputs
shown in figure 1.
[8+8]
Figure 1
3. (a) Explain the reason for the occurrence of overshoot at the base of normally ON transistor
of one shot.
Derive an expression for overshoot.
(b) Discuss a few applications of a monostable multivibrator. Explain how it differs with that of
a binary.
[8+8]
4. (a) What do you mean by a relaxation circuit? Give few examples of relaxation circuits.
(b) With the help of neat waveforms, explain sine wave frequency division with a sweep
circuit. [8+8]
5. Explain the following
(a) How a transistor can be used as a switch. Under what conditions a transistor is said to be
“OFF" &
“ON" respectively?
(b) The phenomenon of latching" in a transistor switch.
(c) Switching times of transistor. [8+4+4]
6. (a) For the circuit shown in figure 2a an input voltage Vi linearly from 0 to 150V is applied.
Sketch the
output waveform V0 to the same time scale. Assume ideal diodes.
Figure 2a
(b) What in meant by a d.c restoration circuit and explain? [12+4]
7. (a) With the help of a neat circuit diagram and waveforms explain the working of a transistor
Bootstrap
time base generator.
(b) i. In the circuit shown in Figure 3 L=200mH, and it is required that the current in L increases
from zero
to100mA in 1ms. Find Vcc? Assume RL=0 and VCE(sat) = 0.
ii. If Rd, consisting of the diode resistance alone, is 10 ohms draw the wave-forms of iL and VCE
indicating voltage levels and time constants. [8+8]
Figure 3
8. (a) What is sampling gate? Explain how it differs from Logic gates?
(b) What is pedestal? How it effect the output of sampling gates?
(c) What are the drawbacks of two diode sampling gate? [6+6+4]
Code No: R05210203
R05
II B.Tech I Semester Examinations,December 2011
Set No. 2
PULSE AND DIGITAL CIRCUITS
Common to Electronics And Telematics, Electronics And Instrumentation
Engineering, Electronics And Communication Engineering, Electrical And
Electronics Engineering
Time: 3 hours
Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
1. (a) Design a collector coupled transistor monostable multivibrator to produce a time delay of
100 µsec.
Use transistors have hFE of 250. Use ±12V sources,VCE(sat) = 0.3V, VBE(sat) = 0.7V and VBEcutoff =
0V
(b) Show that the astable multivibrator works as voltage controlled oscillator. [10+6]
2. (a) Explain the terms pertaining to transistor switching characteristics.
i. Rise time.
ii. Delay time.
iii. Turn-on time.
iv. Storage time.
v. Fall time.
vi. Turn-on time.
(b) Give the expression for rise time and fall time in terms of transistor parameters and
operating currents.
[
6
+
1
0
]
3. (a) What are the basic logic gates which perform almost all the operations in digital
communication
systems.
(b) Give some applications of logic gates.
(c) Define positive and negative logic systems.
(d) Draw a pulse train representing a 11010111 in a synchronous positive logic digital system.
[4+4+4+4]
4. (a) Explain the basic principle of sampling gates using series switch and also give the
applications of
sampling gates.
(b) Explain the effect of control voltage on gate output of unidirectional sampling gate using
diode with
Some example. [8+8]
5. (a) What is relaxation oscillator? Name some negative resistance devices used in relaxation
oscillators and
give its applications.
(b) With the help of a circuit diagram and waveforms, explain the frequency division by an
astable
multivibrator? [8+8]
6. (a) Compare the principle of operation of Miller sweep circuit and Bootstrap sweep circuit.
(b) Explain how linearity is obtained by adjusting the driving waveform of current sweep
circuit. [8+8]
7. (a) Draw the basic circuit diagram of negative peak clamper circuit and explain its operation.
(b) What is meant by comparator and explain diode differentiator comparator operation with
the help of
ramp input signal is applied. [6+10]
8. (a) i. Three low pass RC circuits are in cascaded and isolated from one another by ideal buffer
amplifiers.
Find the expression for the out put voltage as a function of time if the input is a step
voltage.
ii. Find the rise time of the out put in terms of the product RC.
iii. What is the ratio of the rise time of the three sections in cascade to the rise time of a
single section?
(b) Write short notes on High pass RC circuit as a differentiator. [10+6]
Code No: 07A30401
R07
II B.Tech I Semester Examinations,December 2011
Set No. 2
PULSE AND DIGITAL CIRCUITS
Common to Electronics And Instrumentation Engineering, Electrical And
Electronics Engineering
Time: 3 hours
Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
1. (a) Design a diode clamper to restore a d.c level of +3 Volts to an input sinusoidal signal of
peak value
10Volts. Assume drop across diode is 0.6 volts as shown in the figure 1a.
Figure 1a
(b) Compare series diode clipper and shunt diode clipper. [8+8]
2. (a) A UJT sweep generator operates with a valley voltage Vv =2V, and a peak voltage Vp = 15V.
A
sinusoidal synchronizing voltage of 2V peak is applied between bases. The stand off ratio is
η= 0.6. If
the natural frequency of the sweep is 1000Hz, over what range of sync - signal frequency
will the
sweep remain in 1: 1 synchronism with the sync signal?
(b) Describe the sine wave frequency division with a sweep circuit. [16]
3. (a) Write a short notes on RC low pass circuit in detail.
(b) Draw the output response of RC low pass circuit for a step input signal and explain in
detailed. [8+8]
4. (a) Draw the circuit diagram of diode - resistor logic OR gate and explain its operation.
(b) The transistor inverter (NOT gate) circuit has a minimum value hfe = 30, VCC = 12V, RC = 2.2k,
R1 =
15k and R2 =100k, VBB = 12V. Prove that this circuit works as NOT gate. Assume typical
junction
Voltages. The input is varying between 0 and 12V. [16]
5. (a) Explain the phenomenon of latching in a transistor
(b) Define the following for a transistor switch
i. Rise time
ii. Fall time
iii. Storage time
iv. Delay time. [8+8]
6. (a) Explain the operation of a six - diode gate.
(b) Write the applications of sampling gates.
(c) Briefly describe the chopper amplifier and sampling scope. [16]
7. (a) What is a linear time base generator?
(b) Write the applications of time base generators.
(c) Define the sweep speed error, displacement error and transmission error of voltage time
base
waveform. [16]
8. (a) Draw the equivalent circuit diagram for differential amplifier used as an astable multi
vibrator.
(b) Draw the various waveforms at base and collector of transistors of the astable
multivibrator. [16]
Code No: 07A4EC07 R07 Set No. 2
II B.Tech II Semester Examinations,Dec/Jan 2011
PULSE AND DIGITAL CIRCUITS
Common to BME, ICE, E.COMP.E, ETM, E.CONT.E, ECE
Time: 3 hours
Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
1. For the germanium transistors binary of the given figure 1, assume that junction voltages at
saturation and
base-to-emmiter voltages at cutoff and in the active region may all be taken as zero. The
circuit is to
operate properly (one transistor OFF and other one ON) over the temperature range -50 to
+75 0C and to
just start mal functioning at these extreme temperatures. The circuit is to be designed subject
to the
following specifications: VCC=4.5V, VBB=3.0V hFE=40 at -50 0C and 60 at +75 0C,ICBO=4 µA at 25 0C
and doubles for every 10 0C and collector current is 10mA.
(a) find RC.
(b) find R1 and R2. [16]
Figure 1
2. (a) With the help of neat diagram explain the working of transistor Bootstrap time base
generator.
(b) Draw a simple current sweep circuit and explain its working with the help of diagrams. [16]
3. (a) Define level logic system and pulse logic system.
(b) The transistor inverter (NOT gate) circuit has hfemin = 40, Vcc = 12V, Rc =2.2kΩ, R1 = 15kΩ
and R2 =
100kΩ, VBB = 12V. The input is varying between -12V and 0V. Assume typical junction
voltages of
pnp transistor. Prove that this circuit works as NOT gate. [16]
4. (a) For the clipper circuit shown in figure 2, the input vi = 60 sin !t. Calculate and plot to Scale
i. The transfer characteristic indicating slopes and intercepts.
ii. Input / output on the same scale. Assume ideal diodes.
Figure 2
(b) Explain positive peak clipping without reference voltage. [12+4]
5. (a) A symmetrical square wave whose peak-to-peak amptitude is 2V and whose average value
is zero is
applied to an RC integrating circuit. The time constant is equal to half -period of the square
wave. Find
the peak to peak value of the output amplitude.
(b) Describe the relationship between rise time and RC time constant of a low pass RC circuit.
[8+8]
6. (a) Distinguish between sampling gates and logic gates?
(b) Explain the operation of a chopper amplifier with neat block diagram and waveforms.
(c) Distinguish between unidirectional and bidirectional gates. [4+8+4]
7. (a) Explain how a transistor can be used as a switch.
(b) Explain the phenomenon of 'Latching" in a transistor switch [8+8]
8. (a) Describe the method involved in the synchronization of voltage sweep wave-form with a
sinusoidal
synchronization signal with neat waveforms.
(b) Describe the pulse synchronization of a stable relaxation circuit with neat sketches of
waveforms. [8+8]
CODE NO: R09220403
R09
SET No -1
II B.TECH - II SEMESTER EXAMINATIONS, APRIL/MAY, 2011
PULSE AND DIGITAL CIRCUITS
(COMMON TO ELECTRONICS AND COMMUNICATION ENGINEERING,
ELECTRONICS AND TELEMATICS)
Time: 3hours
Marks: 75
Max.
Answer any FIVE questions
All Questions Carry Equal Marks
---
1.a) The output of a high pass RC circuit for a symmetrical square wave input is shown in
Figure.1. Derive the expression for percentage tilt in the output.
Figure.1
b) An oscilloscope displays a 5Hz square wave with 6% tilt. The signal input has no tilt and
is coupled to the oscilloscope via a 4.7μF capacitor. Calculate the input resistance of
the oscilloscope. [10+5]
2.a) Draw the circuit diagram of an Emitter-Coupled clipping circuit. Explain its operation
with its transfer characteristic and necessary expressions
b) State and prove clamping circuit theorem. [8+7]
3. a) A silicon transistor has h = 75, I = 0.1μA and cut-in voltage V = 0.5V. The parameter
FE
CO
γ
“n” of avalanche
multiplication is 4 and BV
CBO
= 50V.
i) Calculate BV
CEO
ii) Calculate BV
CER
iii) Calculate BV
if R = 1.M Ω
CEX
B
assuming V = 10V and R = 10K.
BB
B
b) Write about diode switching times. [10+5]
4. a) What are transpose capacitors? Explain how the commutating capacitors will increase
the speed of a fixed
bias binary.
b)For the circuit shown in figure.4, Vcc = 18V, V = 6V, V = 6V, Rc = 1.5K, R = 5K, R = 25K
BB
1
2
and h (min)
FE
of each transistor is 40. Neglect the drop across the forward biased junctions. Indicate all
the circuit voltages
in the quiescent state and indicate also the voltages immediately after a 5V positive step
is applied. [5+10]
Figure.4
5. a) Draw the circuit of a Boot strap sweep generator and explain its operation. Derive an
expression for its
sweep time.
b) Explain with a circuit the working of a UJT sweep circuit and obtain the expressions for
the intrinsic
standoff ratio (η). [8+7]
6. a) Illustrate with neat circuit diagram, the operation of unidirectional sampling gate for
multiple inputs.
b) Explain with circuit diagram the operation of a two input sampling gate which does not
have any loading
effect on control signal. [7+8]
7. a) With neat waveforms explain sine wave synchronization and compare it with pulse
synchronization.
b) The relaxation oscillator when running freely generates output sweep amplitude of
100V and frequency
1kHz. Synchronizing pulses are applied such that at each pulse the breakdown voltage is
lowered by 20V.
Over what frequency range the synchronizing pulse frequency may be varied if 1:1
synchronization is to
result? [8+7]
8. a) Realize two-input AND & OR gates using diodes and explain their operation with the
help of truth-tables.
b) Realize a three-input NOR gate using Resistor Transistor Logic and explain its operation
with the help of
truth-table. [8+7]
********
CODE NO: R09220403
R09
SET
No -2
II B.TECH - II SEMESTER EXAMINATIONS, APRIL/MAY, 2011
PULSE AND DIGITAL CIRCUITS
(COMMON TO ELECTRONICS AND COMMUNICATION ENGINEERING,
ELECTRONICS AND TELEMATICS)
Time: 3hours
Max. Marks: 75
Answer any FIVE questions
All Questions Carry Equal Marks
--1.a) Prove that an RC circuit behaves as a reasonably good integrator if RC > 15T, Where T is
the period of an input ‘E sin ωt′.
m
b) What is the ratio of the rise time of the three sections in cascade to the rise-time of
Single section of low pass RC circuit? [8+7]
2.a) A square wave input of period T = 1000 μ sec, Vpeak = 10V and Duty cycle = 0.2 is
applied to the circuit shown in figure.2. Given, R = 100Ω, C = 1μF, R = 10K & Diode
S
forward resistance, R = 100Ω.
f
i) Sketch the output waveform with voltage levels at steady state.
ii) Forward and reverse direction tilt
iii) A / A
f
r
figure.2
b) Write a short note on voltage comparators. [12+3]
3.a) Explain the terms pertaining to transistor switching characteristics.
i) Rise time. ii) Delay time. iii) Turn-ON time.
iv) Storage time. v) Fall time. vi) Turn-OFF time.
b) Calculate the maximum operating frequency of a diode with storage time of 1ns and
transition time of 8ns. [12+3]
4.a) What do you mean by collector catching diodes? Explain the need of these diodes in a
bistable multivibrator.
b) For the given circuit shown in figure. 4, find UTP & LTP. What is this circuit called? Data
given h (min) = 40, V (sat) = 0.1 V, V (sat)=0.7 V, V = 0.5V, V (active) = 0.6V.
fe
CE
BE
γ
BE
[5+10]
Figure.4
5.a) Define the three errors that occur in a sweep circuit and obtain an expression for these
errors for an exponential sweep circuit.
b) In the UJT sweep circuit, V = 20V, V = 50V, R = 5k, C = 0.01 micro F. UJT has η= 0.5.
BB
yy
Calculate
i) Amplitude of sweep signal
ii) Slope and displacement errors and
iii) Estimated recovery time. [8+7]
6.a) With the help of a neat diagram, explain the working of two-diode sampling gate.
b) Derive expressions for gain and minimum control voltages of a bi-directional two- diode
sampling gate. [7+8]
7.a) Explain how monostable multivibrator is used as frequency divider?
b) Write short notes on
i) Phase delay
ii) Phase jitters [7+8]
8.a) What is logical noise in a diode AND gate? Explain how it can be reduced by connecting
a clamping diode in the circuit?
b) Realize NAND & NOR gates using CMOS Logic and explain their operation with the help
of truth-tables. [7+8]
********
CODE NO: R09220403
R09
SET No -3
II B.TECH - II SEMESTER EXAMINATIONS, APRIL/MAY, 2011
PULSE AND DIGITAL CIRCUITS
(COMMON TO ELECTRONICS AND COMMUNICATION ENGINEERING,
ELECTRONICS AND TELEMATICS)
Time: 3hours
Max. Marks: 75
Answer any FIVE questions
All Questions Carry Equal Marks
--1.a) What are the drawbacks of uncompensated attenuators? Prove that the condition to
prevent input signal from distortion is R C = R C in an adequately compensated
1 1
2 2,
attenuator.
b) An RC differentiator circuit is driven from a 500Hz symmetrical square wave of 10V
Peak-to peak. Calculate the output voltage levels under steady state if RC =
1msec.[10+5]
2.a) Draw the basic circuit diagram of negative peak clamper and explain its operation.
b) For the circuit shown in figure.2, an input voltage V linearly varies from 0 to 150V is
i
applied. Sketch the output voltage V and transfer characteristics. Assume ideal diodes.
O
[5+10]
figure.2
3.a) Consider the transistor switch in CE configuration shown in figure.3, operated with V =
CC
12V and Vbb =
0V. It is given that R = 2R = 68KΩ, R = 2.2KΩ. Determine
2
1
C
i) The values of I and I of the transistor.
B
C
ii) The minimum value of h required for the transistor to operate in saturation
FE
when it is in ON state?
Figure 3.
b) Explain Zener & Avalanche breakdown mechanisms in diodes. [10+5]
4. Draw and explain the circuit of Astable Multivibrator with necessary waveforms and also
derive the
expression for its frequency of oscillations. [15]
5.a) What are the essential requirements of TV horizontal sweep circuit? How do you
achieve them using a
current sweep?
b) With neat sketches and necessary expressions, explain the transistor Miller time-base
generator. [7+8]
6.a) Draw the circuit of an emitter-coupled bidirectional sampling gate and explain.
b) What is Pedestal? How pedestal can be reduced in a sampling gate circuit? [7+8]
7.a) Explain the principle of “synchronization” and ‘synchronization with frequency division’.
b) Explain the method of pulse synchronization of relaxation devices, with examples. [7+8]
8.a) Realize a two-input NAND gate using Diode Transistor Logic and explain its operation
with the help of
truth-table.
b) Explain the terms:
i) Wired- AND connection ii) Current Source – Sink logic iii) Tri-state logic [6+9]
********
Code N o: R09220403
R09
SET No -4
II B.TECH - II SEMESTER EXAMINATIONS, APRIL/MAY, 2011
PULSE AND DIGITAL CIRCUITS
(COMMON TO ELECTRONICS AND COMMUNICATION ENGINEERING,
ELECTRONICS AND TELEMATICS)
Time: 3hours
Marks: 75
Max.
Answer any FIVE questions
All Questions Carry Equal Marks
--1.a) Prove that for any periodic input waveform the average level of the steady state output
signal from the RC high pass circuit is always Zero.
b) Draw the RC low pass circuit. With necessary waveforms and expressions explain its
working for a step voltage input. [8+7]
2.a) Explain negative peak clipper with and without reference voltage.
b) Sketch the steady state output voltage for the clamper circuit shown in
figure.2 and locate the output d.c level and the zero level. The diode used
has R = 1KΩ, R = 600 KΩ, V = 0. C = 0.1μF and R = 20 KΩ. The input
f
r
γ
is a ± 20 Volts square wave with 50% duty cycle. [5+10]
figure.2
3.a) The circuit shown in figure.3 uses a silicon transistor with h = 100 and V = 0.7V. Find
FE
BE
the value of R which saturates the transistor, when input voltage is +5V.
B
Given R = 1K & V = +5V.
C
CC
Figure 3
b) Write about diode switching times. [10+5]
4. What is a monostable multivibrator? Explain with the help of a neat circuit diagram the
principle of operation
of a monostable multi, and derive an expression for pulse width. Draw the wave forms at
collector and Bases
of both transistors. [15]
5. A UJT is used as a switch across a sweep capacitor C which charges through R. A single
voltage supply V is
BB
used in the circuit. If V &V are the valley and peak voltages respectively,
V
P
a) Prove that the sweep duration is exactly given byT RC ln (V –V )/(V –V )
s=
BB
V
BB
P
b) Prove that if V >>V , then T ≈ RC ln [1/(1-η)] [8+7]
BB
V
S
6. a) Draw the circuit of FOUR-DIODE sampling gate. Derive expressions for its gain(A) and
V .
min
b) Explain the application of sampling gate in a sampling scope. [10+5]
7. a) With neat sketches and necessary waveforms explain how an astable multivibrator can
be synchronized?
b) A symmetrical astable multivibrator using transistor operates from 10V supply has a
period of 1msec.
Triggering pulses of spacing 750 μsec are applied to one base through a small capacitor
from a highimpedance source. Find the minimum triggering pulse amplitude required to achieve
1:1 synchronization.
[8+7]
8. a) Realize a three-input NAND GATE using Transistor Transistor Logic. Explain its
operation with Totem-pole load.
b) With reference to logic gates, explain the terms:
i) Fan-out ii) Noise- Margin iii) Propagation Delay iv) Figure of Merit
[7+8]
(18)LIST OF TOPICS FOR STUDENT’S SEMINARS:
1) Trigate TRANSISTOR
2) BiCMOS Technology
3) Thermistor
4) Class-F CMOS Oscillator
5) Digital to Analog Converters
6) DSL filter
7) Diplexer
8) Design of Low Voltage Low Power Operational Amplifier
9) Mobile TV Technologies
10) Low Pass Block Digital Filter
11) Capacitor less low dropout voltage regulator
12) Real time performance analysis of buck DC-DC converter
Subject: PRINCIPLES OF ELECTRICAL
ENGINEERING
CONTENTS
(1)
-
Objectives and Relevance
(2)
-
Scope
(3)
-
Prerequisites
(4)
-
Syllabus
(5)
Notes,
a.JNTUH
b. GATE
c.IES
Websites/Useful links (PPTs,
Lecture
Programs, Software’s, Tutorials,
Demos etc.)
(6)
-
Expert Details
(7)
-
Journals
(8)
-
Subject (lesson) Plan
(9)
-
Suggested Books
(10)
-
Question Bank
(11)
(12)
-
Assignment Question sets
List of topics for student’s seminars
(1)
OBJECTIVES AND RELEVANCE
This course introduces the basic concepts of Electrical and Electronics, which forms the core of
the advanced concepts in the area of Electrical and Electronics. The emphasis is laid on the basic
circuit designing to the solutions of complex circuits, also concepts regarding construction and
working of electrical machines and measuring equipments is covered.
(2)
SCOPE
The scope of this subject is to provide a thorough knowledge of the flow of voltage and current in
electrical networks and circuits. It also provides the insight of the working and applications of
electrical machines and measuring instruments.
(3)
PREREQUISITES
Before the start of the subject one should have the knowledge of voltage, current, basic electrical
components, relation between V and I w.r.t electrical components, impedance and admittance,
filters, difference between ac and dc, Faraday’s Laws, Lenz Law, Fleming’s Hand Rules and basic
principles of electrical engineering.
(4)
SYLLABUS
(4.1) - JNTU
UNIT-I
OBJECTIVE
 To study the transient analysis.
 To study the basic electrical components and their behavior.
 To study the response of different electrical circuits excited with DC.
SYLLABUS
TRANSIENT ANALYSIS(FIRST AND SECOND ORDER CIRCUITS) :Transient response of
rc,rl ,rlc circuits, for dc excitations, initial conditions ,solution using differential equations,
approach and Laplace transform
UNIT – II
OBJECTIVE
 To study the impedance(Z), admittance (Y) parameters.
 To study the h- and ABCD-parapeters.
 To convert one to other parameters.
 To study the reciprocity and symmetry condition.
SYLLABUS
TWO PORT NETWORKS: Impedance parameters, admittance parameters, hybrid parameters,
transmission (abcd) parameters, conversion of one parameter to another, conditions for symmetry
and reciprocity, inter connection of two networks in series, parallel and cascaded configurations,
image parameters, illustrative parameters
UNIT –III
OBJECTIVE
 To study the concept of filters.
 Different types of filters.
 Designing of different types of filters.
SYLLABUS
FILTERS: Classification of filters, filter network, classification of pass band and stop band,
characteristic impedance in the pass band and stop band, constant-k low pass filter, high pass
filter,m-derived T-section band pass filter and band elimination filter, illustrative problems
Unit – IV
OBJECTIVE
 To study the concept of attenuators.
 .To study the different types of attenuators
 Construction of different types of attenuators.
SYLLABUS
SYMMETRICAL ATTENUATORS: Symmetrical attenuators,- -T type attenuator ,d-type
attenuators, bridged T type attenuators, lattice attenuators
UNIT – V
OBJECTIVE
 To study the principle operation of DC machines.
 To study classification of DC generators depending on excitation.
 To study the relation between different parameters of a DC Machine
rotating in forward direction.
SYLLABUS
D.C Generators: Principle operation of DC machines, types of DC generators, emf
equation in DC generator.
UNIT – VI
OBJECTIVE
 To study the working of DC motors.
 To know the classification of dc motors.
 To study losses associated with dc motor.
 Torque developed, and efficiency.
SYLLABUS
DC Motors: Principle operation of DC motors, types of dc motors, losses and
torque equations, losses and efficiency calculations in dc motors.
Unit –VII
OBJECTIVE
 To study the application of mutual induction a nd self induction.
 Construction and working of transformer.
 To know different types of transformers.
 To calculate losses and efficiency in a transformer using transformer tests
and calculation of Regulation.
SYLLABUS
Transformers: Principles of operation, Constructional Details, Ideal
Transformer and Practical
Transformer, Losses, Transformer Test,
Efficiency and Regulation Calculations.
Unit –VIII
OBJECTIVE




To
To
To
To
stydy
study
study
study
about the single phase induction motors
their construction.
their working, erformance
their characterectics and applications
SYLLABUS
SINGLE PHASE INDUCTION MOTORS:Principle of operation, shaded pole motors, capacitors,
ac servo motors, ac techomotor, synchors, stepper motor, characteristics
(4.2)
SYLLABUS - GATE
UNIT I to UNIT VIII: Not Applicable.
(4.3)
SYLLABUS - IES
UNIT I to UNIT VIII: Not Applicable.
(5)
WEBSITES
1. http://www.autoshop101.com/forms/elec02.pdf
2. http://www.didaktik.itn.liu.se/thesis/margarita_thesis2.pdf
3. www.mit.edu
4. www.iitk.ac.in
5. http://nptel.iitm.ac.in/Onlinecourses/Nagendra/
6. http://www.nptel.iitm.ac.in/courses/Webcourscontents/IIT%20Kharagpur/Basic%20Electrical
%20Technology/pdf/L-03(GDR)(ET)%20((EE)NPTEL).pdf
7. www.iitr.ac.in
8. www.circuit-magic.com
9. www.ece.rice.edu
10. www.electrical4u.com
(6) EXPERT DETAILS:
INTERNATIONAL
1.
Nicolaos G. Alexopoulos
Professor Emeritus, Electrical Engineering and Computer Science
305 Rockwell Engineering Center Irvine, CA 92697-2700
2.
Dr. Steven W. Blume
Professor of Electrical Engi neering, Dept. of Electrical Engg.
University of California,
New Jersey.USA.
NATIONAL
Lecture
Suggested
Topics as per JNTU syllabus
Topics to be covered
No.
Page No
Book
Unit I
L1, L2
Transient response of R-L D.C
Excitation & Sinusoidal Excitation
Transient response of R-L D.C
Excitation& Sinusoidal Excitation
T2
P 11.1, P 11.11
L3, L4
Transient response of R-C, (Series
combinations only) for d.c. &
Sinusoidal Excitation
Transient response of R-C, (Series
combinations only) for d.c. &
Sinusoidal Excitation
T2
P 11.2, P 11.14
Transient response of R-L-C circuits
(Series combinations only) for d.c.
and sinusoidal excitations – Initial
Transient response of R-L-C circuits
(Series combinations only) for d.c and
T2
P 11.6, P 11.17
T2
P 11.8, P 11.22
T2
P 11. 34
T2
P 15.1, 15.2,15.5
T2
P 15.8 - 15.16
T2
P 15.16
T2
P 15.21
T2
P 15.24
T2
P 15.37
T2
P 15.59
L5, L6
conditions
Solution
using
differential equation approach
sinusoidal excitations–Initial conditions
- Solution using differential equation
approach
Transient response of R-L-C circuits
(Series combinations only) for d.c.
and sinusoidal excitations – Initial
L7, L8,L9
conditions - Solution using Laplace
transform methods of solutions
L10
Transient response of R-L-C circuits
(Series combinations only) for d.c. and
sinusoidal
excitations
–
Initial
conditions -Solution using Laplace
transform methods of solutions
Exercise Problems & Solutions
Unit II
Impedance Parameters,
Impedance Parameters, Admittance
Admittance Parameters
Parameters
Hybrid Parameters,
Hybrid Parameters, Transmission
Transmission (ABCD)Parameters
(ABCD) Parameters
Conversion of one parameter to
another parameter
Conversion of one parameter to another
L11,L12
L13,L14
L15, L16
parameter
L17
Conditions for Reciprocity and
Symmetry, interconnection of Two
port Networks in series
Conditions
for
Reciprocity
and
Symmetry, interconnection of Two port
Networks in series
Interconnection of Two port
L18,L19
Interconnection of Two port Networks
in Parallel & Casacaded configuration
Networks in Parallel & Casacaded
configuration
Image Parameters, Illustrative
L20
Image Parameters
Problems
L21
Exercise Problems & Solution
Unit III
L 22
Classsification
Networks
of
Filters,
Filter
L 23
Classfication of Pass Band and Stop
Band
L 24
Classsification
Networks
of
Filters,
Filter
T2
P 17.1, P 17.3
Classfication of Pass Band and Stop
Band
T2
P 17.9
Characteristic Imapedance in the
pass and stop bands
Characteristic Impedance in the pass
and stop bands
T2
P 17.12
L 25,L 26
Constant K low Pass Filter, High
pass filter
Constant K low Pass Filter, High pass
filter
T2
P 17.13
L 27
m- derived T- section, Band Pass
Filter
m- derived T- section, Band Pass Filter
T2
P 17.20
L 28
Band Elimination Filter, Illustrative
Problems
Band Elimination Filter
T2
P 17.33
L 29
Exercise Problems & Solution
T2
P 17.35
Unit IV
L 30
Symmetrical , T - Type Attenuators
Symmetrical , T - Type Attenuators
T2
P 17.42
L 31
δ - Type Attenuator
δ - Type Attenuator
T2
P 17.44
L 32
Bridged T type Attenuator
Bridged T type Attenuator
T2
P 17. 48
L 33
Lattice Attenuator
Lattice Attenuator
T2
P 17.45
L 34
Exercise Problems & Solution
T2
P 17. 77
T3
P 294
Unit V
L 35
Principle of
Machines
Operation
of
DC
Principle of Operation of DC Machines
L 36
EMF Equation
EMF Equation
T3
P307
L 37
Types of Generators
Types of Generators
T3
P 335
L 38
Magnetization
and
Load
Characteristics of DC Generators
Magnetization and Load Characteristics
T3
P 362
T3
P 362
of DC Generators
L 39
Exercise Problems & Solution
Unit VI
L 40
DC Motors, Types of DC Motors
DC Motors, Types of DC Motors
T3
P 370
L 41
Characteristics of DC Motors
Characteristics of DC Motors
T3
P 377
L 42
Losses and Efficiency
Losses and Efficiency
T3
P 385
L 43
Swinburne's Test
Swinburne's Test
T3
P341
L 44
Speed Control of DC Shunt Motor
Speed Control of DC Shunt Motor
T3
P 387
L 45
Flux and Armature Voltage Control
Flux and Armature Voltage Control
T3
P 389
Methods
Methods
L 46
Exercise Problems & Solution
T3
P 406
L 47
Exercise Problems & Solution
T3
P 414
T3
P 419
T3
P 436
Losses and Efficiency of Transformer
and Regulation
T3
P 442
T3
P 447
T3
P 447
T3
P 459
T3
P 431
Unit VII
L 48, L49
Principle of Operation of Single
Phase
Transformer,
Types,
Constructional Features
Principle of Operation of Single Phase
Transformer, Types, Constructional
Features
L 50
Phasor Diagram on No Load and
Load, Equivalent Circuit
Phasor Diagram on No Load and Load,
Equivalent Circuit
L 51, 52
Losses
and
Efficiency
Transformer and Regulation
of
L 53
OC and SC Tests
OC and SC Tests
L 54
Predetermination of efficiency and
Predetermination of efficiency and
Regulation ( Simple Problems)
Regulation ( Simple Problems)
Exercise Problems & Solution
Exercise Problems & Solution
L 55
Unit VIII
L 56
Principle of operation of Shaded
Pole motors
Principle of operation of Shaded Pole
motors
L 57
Capacitor Motors
Capacitor Motors
T3
P 433
L 58
AC Servo Motors, AC Tachometers
AC Servo Motors, AC Tachometers
T3
P 512,P434,435
L 59
Synchros, Stepper Motors,
Synchros,
Characteristics
T3
P 450
Stepper
Motors,
Characteristics
L 60
Exercise Problems & Solution
T3
P 453
L 61
Exercise Problems & Solution
T3
P 460
Dr. Amitava Das Gupta,
Dept. of EEE,
IIT Bombay,
2.
Prof .G S Punekar,
Dept of EEE,
NITK.
REGIONAL
1.
Prof. Shyam Mohan S Palli,
HoD of Dept. EEE,
SIR CRR College Of Engineering.
2.
Dr. D M Vinod Kumar,
Professor – Dept of EEE,
NITW.
(7) JOURNALS
INTERNATIONAL
1.
IEEE Transactions on Circuits and Systems.
2.
IEEE Proceedings Circuits, Devices and Systems.
3.
IEEE Transactions on Electrical Machines.
4.
Springer Publications.
NATIONAL
1.
Electrical India
2.
Circuit Engineering
3.
Abhinav Journal
4.
SADHANA
(8)Lesson Plan
OBJECTIVE & OUTCOME BASED PLAN FOR SUBJECT
(OOPS)
FACULTY: S.SUNDEEP
DEPT: ECE
SUBJECT: PRINCIPLES OF ELECTRICAL ENGINEERING
Lecture
No.
L1,L2
L3,L4
L5,L6
L7,L8
L9,L10
L11,L12
JNTUH Topic
Objective of each
Topic
Learning
Outcome
Practical Inferences
UNIT – 1 TRANSIENT ANALYSIS (FIRST AND SECOND ORDER SYSTEMS)
Differentiating
between
Explanation
of
Transient
transients and
Transients
for
Useful in determining the
response of
steady
state
different
relationship between time
series circuits
responses of RL,
combinations of
constant and performance of
for DC
RC,
RLC
circuit
the circuit.
excitations.
circuits
and
parameters.
plotting
the
response.
Knowledge
about
the
response of the
Initial
system
before Useful in calculating the
conditions for Explanation of the
and
after transient response of the
transient DC initial conditions
occurring of the circuit.
series circuits
transient’s w.r.t
mathematical
equations.
Should be able
to calculate the
current
response
(complete
solution),
voltage
and
power. Be able
to
write
differential
equation for a
Solution using
dc
circuits Useful to understand some
Explanation
to
Differential
containing two terminologies that are highly
calculate complete
Equation and
storage elements linked with the system.
solution of the
Laplace
in presence of a Performance of a second
transient circuit.
transform
resistance. To order system.
understand the
meaning of the
terms (i) over
damped
(ii)
critically
damped,
and
(iii)
Under
damped
in
context with a
second
order
dynamic system.
UNIT – 2 TWO PORT NETWORKS
Should
get
knowledge of
the
The two-port network model is
Explanation of the
Two port
relationship
used in mathematical circuit
network having
networks
between
analysis techniques to isolate
two ports.
voltage and portions of larger circuits.
currents and
input, output
Method
of
Teachin
g
M1
M1
M1 &
M5
M4
Z - parameters
Explanation
of
network in terms
of Z - parameters.
Y - parameters
Explanation
of
network in terms
of Y - parameters.
Hybrid
parameters
Explanation
of
network in terms
of h - parameters.
JNTUH Topic
Objective of each
Topic
L16
ABCD
parameters
Explanation
of
network in terms
of
ABCD
parameters.
L17
Conversion of
one parameter
to other
parameter
Explaining
conversions of one
parameter
to
other.
Conditions for
Reciprocity
and Symmetry
Explaining
different
conditions
reciprocity
symmetry
network
parameters.
L13
L14
L15
Lecture
No.
L18
L19,L20
Interconnectio
n of two port
networks
L21
Image
parameters
L22
Classification
of filters
for
and
for
in a two port
network.
Knowledge of
simplifying
network
in
terms of Z –
parameters.
Knowledge of
simplifying
network
in
terms of Y –
parameters.
Knowledge of
simplifying
network
in
terms of h –
parameters.
Learning
Outcome
Knowledge of
simplifying
network
in
terms
of
ABCD
parameters.
Should
get
knowledge of
defining one
parameter in
terms
of
other.
Gives
knowledge of
general
properties of
two
port
networks.
Can calculate
network
parameters
Explanation
of
when 2 two
different
port
combinations of
networks are
two
port
in
series,
networks.
parallel and
cascade
connection.
Knowledge of
Explanation
of simplifying
network in terms network
in
of
image
- terms
of
parameters.
image
–
parameters.
UNIT – 3 FILTERS
Explanation
of Defining of
different types of low pass, high
filters.
pass,
band
Used to determine bipolar
current mirror with emitter
degeneration
circuit
parameters.
Used to determine bipolar
current mirror with emitter
degeneration
circuit
parameters.
Used to determine common base
amplifier circuit parameters.
Practical Inferences
Used to determine telephony
four-wire Transmission Systems
parameters.
M1 &
M5
M1 &
M5
M1 &
M5
Method
of
Teachin
g
M1 &
M5
Used
in
networks
for
determining the parameters in
terms of any one particular
parameters for simplicity.
M6
Used to determine parameters
for linear passive network.
M1
Used to determine parameters
of 2 or more networks
interconnected
when
port
conditions are maintained as
usual.
M2 &
M5
Used
to
determine
the
parameters of network which
are defined in terms of incident
and reflected wave at ports
M1
Used to realize particular
frequency from n number of
frequencies.
M4
L23
Filter
Networks
L24,L25
Pass Band &
Stop Band
L26,L27
Low Pass,
High Pass,
Band Pass &
Band
Elimination
filter.
L28,L29
m- derived T –
section
L30
Attenuators
L31
Symmetrical
Attenuators
L32
T- type
Attenuator
L33
δ- type
Attenuator
Lecture
No.
Topic
pass,
band
stop, all pass
filter.
Should able
to find out or
Explanation
of
realize
the
network
Used for realization of the
network
containing
signals
with
varying
consisting of
different levels of
frequencies.
different
filters.
levels
of
filters.
Knowledge of
band
pass,
Explanation
of
band stop, all
frequency
Used in the networks were
pass band &
responses
into
selected band of frequencies are
characteristic
different
to be passed.
impedance in
bandforms.
pass and stop
band.
Knowledge
on
characteristic
Explanation
of
Used to built filter based on
s
and
Pass
&
technologies such as analog
operation and
Elimination
of
filter, mechanical filter and
application of
filters.
digital filter.
Pass
&
Elimination
filters.
Knowledge of
image based
Explanation
of filter design
design
& & frequency
characteristics of bands
in Used
with
m- derived T – transmission
telephone multiplexing.
section
w.r.t lines were mfrequency.
derived T –
section
is
used.
UNIT – 4 SYMMETRICAL ATTENUATORS
Gives idea about attenuator
Used to reduce
General definition and
classification
of
the amplitude o
of
attenuator, attenuator depending on
r power of
units and types.
network and output of the
a signal.
attenuator.
Used to match
Explanation
of
Knowledge of input and impedances of
symmetrical
output impedance control.
input
and
attenuator.
output.
Knowledge of input and Used to match
output impedance control and impedances of
Explanation of Tdetermining
Attenuation input
and
type attenuator.
constant.
output for T
configuration.
Knowledge of determining Used to match
Explanation of δ- Attenuation constant.
impedances of
type attenuator.
input
and
output.
Objective of each
Topic
Learning Outcome
Practical
Inferences
M4
M4
M4
M4
M10
M10
M10
M10
Method
of
Teachin
g
L34
Bridged Ttype
Attenuator
Explanation
of
Bridged T- type
attenuator.
L35
Lattice
Attenuator
Explanation
Lattice
attenuator.
Knowledge of input and
output impedance control.
Knowledge of input and
output impedance control and
determining
Attenuation
constant.
UNIT – 5 DC GENERATORS
of
L36
DC Machines
Explanation
of
DC
Machines,
classification and
principle
operation.
L37
EMF equation
of DC
Generator
Derivation
of
back EMF for DC
Generator.
Knowledge
on
different
parameters and their relation
of DC Generator.
L38
Types of DC
Generators
Explanation
of
classification
of
different
DC
Generators.
Should able to understand
various
types
of
DC
Generators depending on type
of
excitations
(self
&
separately).
L39
Characteristics
of DC
Generators
Explanation
of
magnetization and
load
characteristics of
DC generator.
Knowledge
of
losses,
efficiency and power stages of
DC Generator.
L40
DC Motors
L41
Characteristics
of DC Motors
L42
Swimburne’s
Test
L43,L44
L45,L46
L47
Knowledge of DC Machines
(DC generators and DC
motors) and their working.
UNIT – 6 DC MOTORS
General definition
and
principle Knowledge on design and
operation of DC working of DC Motor.
Motor.
Knowledge
on
relation
Explanation
of
between
torque,
speed,
torque – speed
current, voltage of stator and
characteristics.
rotor.
Explanation
on
conduction
of
Swinburne’s test
on DC Motor.
Knowledge on measuring
losses
on
no-load
and
efficiency
at
any
predetermined load.
Used to match
impedances of
input
and
output.
Used to match
impedances of
input
and
output.
Dc
Machines
are designed to
be
used
in
batteries,
boosters and for
speed control.
Used
to
determine the
voltage
regulation.
Used for the
design of DC
Generators
depending the
application.
Used
in
determining the
different losses
and efficiency
of
DC
generator.
Used for speed
control of fans.
Used
in
determining the
efficiency of DC
Motor.
Used
to
determine the
losses
and
efficiency of a
DC Motor.
Explanation of the
Used for wide
relations between
Speed control
Should be able to determine range of speed
torque and speed
of DC Shunt
the relations between torque calculations
for constant and
motor
and speed.
and
speed
variable
speed
control.
applications.
Explanation
of
Used for wide
Flux and
speed
control Knowledge on calculating the range of speed
Armature
based on flux and speed and control based on calculations
voltage control
armature voltage armature voltage and flux.
and
speed
methods
control.
control.
UNIT – 7 TRANSFORMERS AND THEIR PERFORMANCE
Definition
and
Used
in
Knowledge on l view of
Transformer
pictorial
variation
of
transformer.
representation.
voltage levels
M10
M10
M1
M1 &
M6
M3
M5
M9
M5
M1 &
M5
M4 &
M5
M9 &
M7
M4
L48
Principal
operation of
single phase
transformer
L49,L50
Types
Explanation
classification
transformers.
Topic
Objective of each
Topic
Constructional
Features
Explanation
of
different
transformers and
their
operation
based
on
construction.
Lecture
No.
L51
L52,L53
Equivalent
circuit and
phasor
diagram
L54
Losses,
efficiency and
Regulation
L55,L56
OC & SC
Tests
L57
Principle
operation
L58
Shaded pole
motors
L59
Capacitor
motors
Explanation
of
input to output
and the process in
transformer.
Knowledge of primary and
secondary side parameters
and their determination.
Knowledge of transformers
based on type of operation,
construction, service.
of
of
Explanation
of
equivalent circuit
of
transformer
and determining
the
phasor
relations between
voltages
and
currents.
Explanation and
derivation
of
various
losses,
efficiency
and
voltage regulation
in transformer.
Explanation and
derivation of OC
and SC tests.
for
constant
frequency.
Used to operate
voltage levels
for single phase
applications.
Used
in
determining
transformer to
be
installed
according
to
application.
M1
M1 &
M2
Method
of
Teachin
g
Learning Outcome
Practical
Inferences
Knowledge of shell type and
core type of transformers and
their operation.
Shell type used
for high voltage
applications
and core type
used for low
voltage
application.
M2
Knowledge of flow of current,
voltage and flux in primary
and secondary side of the
transformer
and
their
relations.
Useful
to
determine the
voltage levels in
electrical power
systems.
M1 &
M4
Knowledge on the leakages in
transformer w.r.t physical
and electrical, efficiency and
maintaining of voltage levels
in transformer.
Useful
in
analyzing the
status of the
transformer.
M5
Knowledge in determining the
various parameters using OC
& SC tests on transformer.
Used
to
determine
various losses
and parameters
in
a
transformer.
M5
UNIT – 8 SINGLE PHASE INDUCTION MOTORS
Knowledge
on working of
IM
and
Working of single
Used
in
fans,
relation
phase IM.
centrifugal pumps.
between
torquespeed.
Knowledge
Schematic
on working
diagram
and
and relation Used in toys.
working of shaded
between
pole IM.
torque.
Schematic
Knowledge
diagram
and on working
Used in compressors.
working
of and relation
Capacitor motors. between
blowers,
M1 &
M4
M9
M6
L60
AC
Servomotors
and AC
Tachometers
L61
Synchros,
Stepper
motors
Schematic
diagram
and
working of AC
Servomotors and
AC Tachometers.
Schematic
diagram
and
working
of
Synchros, Stepper
motors.
torque.
Knowledge
on working
and relation
between
torque.
Knowledge
on working
and relation
between
torque.
Used in determining the speed.
Used in control of speed for
various applications.
M8
M1 &
M9
METHODS OF TEACHING:
M1 : Lecture Method
M6 : Tutorial
M2 : Demo Method
M7 : Assignment
M3 : Guest Lecture
M8 : Industry Visit
M4 : Presentation /PPT
M9 : Project Based
M5 : Lab/Practical
M10 : Charts / OHP
(9) SUGGESTED TEXT BOOKS:
T1- Principles of electrical engineering by A Sudhakar, Shyammohan, S Palli
T2- Principles of electrical and electronics engineering by V.K.Mehata
REFERENCE BOOKS:
R1- Circuits and networks:- A. Sudhakar, Shyammohan 3rd edition..2009
R2- Networks, Lines and fields by John.D.Ryder, 2ndedition
R3- Basic electrical engineering by Kothari and Nagarath 2nd edition
(10)QUESTION BANK
Unit-1
1. 1 For the circuit shown below Figure. 1, find the current equation when switch S is
opened at t = 0.
2. Convert the current source shown below Figure. 2 in to a voltage source in the S
domains.
3. For the below circuit (Figure.1), find the current in 20Ω when the
switch is opened
at t = 0.
4. Transform the below circuit (Figure. 2) in to ‘S’ domain and determine the Laplace
transform impedance.
5. For the below circuit find the current equation i(t), when the switch is opened at t = 0.
UNIT-2
1. Determine the Y – parameters for the two – port network shown in Fig.3 and also
find g – parameters.
2. Find the Transmission parameters and Z – Parameters for the two – port network
3. Determine the Z – Parameters and transmission parameters of the current shown in
Fig.
4. Determine h – parameters for the network shown in Fig.
5. Find Z and Y parameter of the network shown below Figure
UNIT-3
1.
Design a band stop, constant – K filter with cut off frequencies of 4
KHz and 10 KHz and nominal characteristic impedance of 500 Ω.
Design a band pass, constant – K filter with cut – off frequency of 4 KHz and
nominal characteristic impedance of 400 Ω.
Design a low pass constant – K (i) T – Section and (ii) π – section filter with cut – off
frequency (f ) 6 kHz and nominal characteristic impedance of 500 Ω.
2.
3.
c
A high pass constant – K filter with cut – off frequency 40 kHz is required to
procedure a maximum attenuation at 36 kHz when used with terminated resistance of
500 Ω. Design a suitable m – derived T – section.
Design a band elimination filter having a design impedance of 600Ω and cut – off
frequencies f = 2 KHz and f = 6 KHZ
4.
5.
1
2
UNIT-4
1. Explain about a symmetrical π – attenuator.
2. Design a symmetrical π – attenuator to provide attenuation of 20dB
and design impedance of 400 Ω.
3. Explain Symmetrical Bridge T – type attenuator
4. Design a symmetrical bridge T – attenuator with attenuation of 20 dB
and design impedance of 600 Ω.
5. Explain symmetrical lattice Attenuator
1.
2.
3.
4.
5.
UNIT-5
Derive an expression for the induced emf in the armature of a DC
Machine.
The armature of a 4 – pole lap wound shunt generator has 480
conductors. The flux per pole is 0.05 Wb. The armature and field
resistances are 0.05 Ω and 50 Ω. Find the speed of the machine when
supplying 450A at a terminal voltage of 250V
Explain different types of dc generators with neat sketches and give
the application of each.
A – 4 pole, lap wound armature when driven at 600 rpm generates
120V. If the flux per pole is 0.025 Wb, find the number of conductors
on its armature.
Explain in detail the Load characteristics of various DC generators
with appropriate sketches and also give the applications of various
generators
UNIT-6
1. Write about the various losses occurring in a dc motor and name the
parts of the machine in which these occur
2. A 250V DC shunt motor takes 4A when running unloaded. Its
armature and field resistances are 0.3 Ω and 250 Ω respectively.
Calculate the efficiency when the dc shunt motor taking a current of
60A.
3. What are the various methods of speed control of dc shunt motor?
4. A 250 V, 10 kW shunt motor takes 2.5A when running light. The
armature and field resistances are 0.3 Ω and 400 Ω respectively.
Brush contact drop of 2V. Find the full – load efficiency of motor?
5. Explain in detail the Load characteristics of various DC generators
with appropriate sketches and also give the applications of various
generators
UNIT-7
1. Explain the principle of operation of 1-Ø Transformer.
2. Derive the equivalent circuit of 1-Ø Transformer and discuss its
significance
3. Derive the expression for the induced emf of a Transformer
4. A 6600/400V, 50 Hz, single phase Transformer has a net cross2
sectional area of the core of 428 cm . The maximum flux density in
the core is 1.5 Tesla. Calculate the number of turns in the primary
and secondary windings.
5. Explain the importance of open circuit and short – circuit tests on a
transformer.
UNIT-8
1. Write short notes on the following
a) AC Tachometers.
b) Stepper motors. c) Capacitor motors.
2. Explain the working principle of capacitor – start and capacitor – run
single phase induction motors with the circuit diagram and also give
their applications.
3. Write short notes on the following a)Capacitor motor b) Stepper
motor. c) AC Servo motor.
4. Write short notes on the following: a) Capacitor – start motors. b)
Shaded pole motors c) AC Tachometers.
5. Write short notes on the following a) AC Servo motors. b) Shaded pole
motor. c) Synchros.
(11) ASSIGNMENT QUESTIONS SETS
SET-1

Transform the below circuit (Figure.2) in to ‘S’ domain and determine the laplace
impedance

Determine Y – parameters of the below network. Hence determine the
o h-parameters








Design a m – derived high pass filter with a cut – off frequency of
10KHz; design impedance of 5Ω and m = 0.4.
Determine the current i for t ≥ 0 if initial current i(0) = 1 for the below
circuit (Figure. 1).
What is a constant – K low pass filter, derive its characteristics
impedance
Compare magnetic circuit with electric circuit and write down the analogy between
the two
Derive the expression of induced emf of dc generator.
Explain the following with reference to the indicating instruments
Deflecting torque (b) Controlling torque (c) Damping torque (d) Scale and pointer
A 6 pole induction motor is fed by three phase 50 HZ supply and running with a full
load slip of 3%. Find the full load speed of induction motor and also the frequency of
rotor emf.
SET-2

Switch is opened at t = 0 in the below circuit (Figure. 2). Then find the
current ‘i’.
o

Determine the transmission parameter and hence determine the short circuit
admittance parameters for the below circuit (Figure.3).
o








A low pass π section filter consists of an inductance of 25 mH in
series arm and two capacitors of 0.2μF in shunt arms. Calculate the
cut – off frequency, design impedance, attenuation at 5 KHz and
phase shift at 2 KHz. Also find the characteristic impedance at 2 KHz
Determine losses of transformer.
A 4 pole lap wound dc generator has1000 conductors, a flux of 20webers and is
driven at 1400 rpm. Find induced emf.
Explain difference between ideal and practical transformer.
Derive expression for emf in DC generator.
Derive emf equation of DC motor.
State difference between MC & MI instruments.
A 8 pole induction motor is fed by three phase 50 HZ supply and running with a full
load slip of 3%. Find the full load speed of induction motor and also the frequency of
rotor emf.
SET-3

Obtain Z parameters of the below circuit (Figure. 3) and from there Z – parameters
derive h – parameters

For the circuit shown below Figure, find the current equation when switch S is
opened at t = 0.

Design a low pass constant – K (i) T – Section and (ii) π – section filter with cut – off
frequency (f ) 6 kHz and nominal characteristic impedance of 500 Ω.

A high pass constant – K filter with cut – off frequency 40 kHz is required to
procedure a maximum attenuation at 36 kHz when used with terminated resistance of
500 Ω. Design a suitable m – derived T – section.

Design a symmetrical lattice attenuator to have characteristic
impedance of 600 Ω and attenuation of 20 Db
Describe with suitable diagrams the principle of operation of a dc
generator

c




A 4 pole dc generator runs at 1000 rpm. Its armature is lap wound
and has 740 conductors on its periphery. The useful flux per pole is
0.04 wb. Calculate the emf generated on open circuit.
Explain in detail the construction and principle of operations of transformer
Write short notes on the following: a) Capacitor – start motors. b)
Shaded pole motors c) AC Tachometers.
Explain the working principle of capacitor – start and capacitor – run
single phase induction motors with the circuit diagram and also give
their applications
SET-4

Convert the current source shown below Figurein to a voltage source in the S
domains

Determine the Z – Parameters and transmission parameters of the current shown in
Fig.

Determine h – parameters for the network shown in Fig.

Draw the circuit of symmetrical lattice attenuation. Derive the design
equation
Design a symmetrical lattice attenuator to have attenuation of 20 dB
and characteristic impedance of 500 Ω.
Explain the various losses which occurs in a dc motor
A 500V dc shunt motor draws 4A on no load. The field current of the
motor is 1.0A. Its
armature resistance including brushes is 0.2
Ω. Find the efficiency, when the input current is 20A.
Sketch the speed – load characteristics of a dc shunt, series and
compound motors. Account for the shape of the above characteristic
curves






Open circuit and short circuit tests conducted on a 10KVA,
500/2000V, 50 Hz, Single phase transformer gave the following
readings OC Test: 500V, 120W on primary side, SC Test: 15V, 20A,
100W on primary side, Determine the efficiency on full load unity
power factor
Write short notes on the following
o AC Tachometers.
o Stepper motors. c) Capacitor motors.
( 12)List of topics for student’s seminars :
1. Calculation as well as conversion of one to other parameters.
2. Classification of filters.
3. Explain transformer application with different rating.
4. Classify DC generators.
5. Classify DC motors.
6. Explain recent developments in electrical machines.
7. Explain need for speed control of DC Motor.
8. Construction and working of transformers.
9. Principle and operation of single phase induction motor.
10. Working and real time applications of stepper motor.
Subject: SWITCHING THEORY & LOGIC DESIGN
S.NO
(1)
(2)
(3)
-
(4)
-
CONTENT
Objectives and Relevance
Scope
Prerequisites
Syllabus
1.
JNTU
2.
GATE
3.
IES
(5)
-
Suggested Books
(6)
-
Websites
(7)
-
Expert Details
(8)
-
Journals
(9)
-
Subject (lesson) Plan
(10)
-
Question Bank
1.
JNTU
2.
GATE
(11)
-Tutorial Question sets on each unit
(12)
-List of topics for student’s seminars
COURSE OBJECTIVE & RELEVANCE:
This course introduces the basic concepts of logic gates which is the most useful for designing
the IC Technology in engineering discipline. The emphasis of this course is laid on the basic
analysis of digital circuits.
Second Year – 4 credits
Topics:







8.
NUMBER SYSTEMS & CODES
BOOLEAN ALGEBRA AND SWITCHING FUNCTIONS
MINIMIZATION OF SWITCHING FUNCTIONS
COMBINATIONAL LOGIC DESIGN
PROGRAMMABLE LOGIC DEVICES, THRESHOLD Lo
SEQUENTIAL CIRCUITS - I
SEQUENTIAL CIRCUITS - II
ALGOROTHIMIC STATE MACHINES
1. SCOPE
The scope of this subject is to provide an insight into designing the DTL, TTL ECL circuits which
are useful in digital devices. This concept is more useful in further applications of minimizing the
complexity of logic circuits.
2. PREREQUISITES:
This subject recommends continuous practice of various simple arithmetic operations like
addition, subtraction. It needs requisite knowledge about assuming and designing the logic
circuits. How to R educe the size and complexity of the digital circuits.
3. SYLLABUS:
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY
HYDERABAD
II Year B.Tech ECE-II sem
L T/P/D C
4 1/-/- 4
SWITCHING THEORY & LOGIC DESIGN
UNIT-I
NUMBER SYSTEMS & CODES: Philosophy of number systems – complement representation of
negative numbers-binary arithmetic-binary codes-error detecting & error correcting codes –hamming codes
UNIT – II
BOOLEAN ALGEBRA AND SWITCHING FUNCTIONS : Fundamental postulates of Boolean
Algebra - Basic theorems and properties - switching functions–Canonical and Standard forms-Algebraic
simplification digital logic gates, properties of XOR gates –universal gates-Multilevel NAND/NOR
realizations
UNIT –III
MINIMIZATION OF SWITCHING FUNCTIONS : Map method, Prime implicants, Don’t care
combinations, Minimal SOP and POS forms, Tabular Method, Prime –Implicant chart, simplification rules
UNIT – IV
COMBINATIONAL LOGIC DESIGNDesign using conventional logic gates, Encoder, Decoder,
Multiplexer, De-Multiplexer, Modular design using IC chips, MUX Realization of switching functions
Parity bit generator, Code-converters, Hazards and hazard free realizations
UNIT – V
PROGRAMMABLE LOGIC DEVICES, THRESHOLD LOGIC : Basic PLD’s-ROM, PROM, PLA,
PLD Realization of Switching functions using PLD’s. Capabilities and limitations of Threshold gate,
Synthesis of Threshold functions, Multigate Synthesis
UNIT – VI
SEQUENTIAL CIRCUITS - I : Classification of sequential circuits (Synchronous, Asynchronous, Pulse
mode, Level mode with examples) Basic flip-flops-Triggering and excitation tables. Steps in synchronous
sequential circuit design. Design of modulo-N Ring & Shift counters, Serial binary adder,sequence
detector.
UNIT – VII
SEQUENTIAL CIRCUITS - II : Finite state machine-capabilities and limitations, Mealy and Moore
models-minimization of completely specified and incompletely specified sequential machines, Partition
techniques and Merger chart methods-concept of minimal cover table.
UNIT – VIII
ALGOROTHIMIC STATE MACHINES : Salient features of the ASM chart-Simple examples-System
design using data path and control subsystems-control implementations-examples of Weighing machine
and Binary multiplier.
TEXTBOOKS :
1. Switching & Finite Automata theory – Zvi Kohavi, TMH,2nd Edition.
2. Digital Design – Morris Mano, PHI, 3rd Edition, 2006.
3. Switching Theory and Logic Design- A,Anand Kumar,2008,PHI.
REFERENCES :
1. An Engineering Approach To Digital Design – Fletcher, PHI.
2. Fundamentals of Logic Design – Charles H. Roth, Thomson Publications, 5th Edition, 2004,
Thomson publications.
3. Digital Logic Applications and Design – John M. Yarbrough, Thomson Publications, 2006,
Thomson publications
(5) WEBSITES :
1.
www.ieee.org
2.
www.2dix.com
3.
www.xillinx.com
4.
www.cdac.com
5.
www.vlsi.edu
6.
www.vlsi.iitkgp.ernet.in
7.
www.educypedia.be/electronic/digital.com
8.
www.iitb.ac.in
9.
www.iitm.ac.in
10. www.iitr.ac.in
11. www.iitg.ernet.in
12. www.bits-pilani.ac.in
13. www.metorgraphics.com
14. www.vlsi-reasearch.com
15. www.iisc.ernet.in
16. www.samsung.com
17. www.vedaiit.com
(6) SUJECT EXPERTS DETAILS:
INTERNATIONAL
1. Prof. K Subbarangaiah is Director of VEDA IIT, Hyderabad
NATIONAL
1.
Dr.K. LAL KISHORE, Ph.D., MIEEE, FIETE, MISTE, MISHM, JNTU, Hyderabad
2.
Mr .Sundaram, AGM, CAD R&D, ECIL, Hyderabad..
3.
Mr. Rajendra naik, Asst Prof, Dept of ECE, Osmania University, Hyderabad.
REGIONAL

Dr. N.S.Murthy, Professor and Head Dept. of ECE, REC,Warangal - 506004 (India) email:
[email protected]



S.G Vinayaka Prasad, Sr. App. Engineer, Silicon Micro Systems
DR. M. Madhavi Latha, JNTU, Hyderabad
Sarat Chandra Babu, Centre Head C-DAC, Hyderabad email: [email protected]
(7) SUBJECT LESSON PLAN
S.no
1
Jntu Syllabus
UNIT -1
Sub topics
No. Of
lectures
Required
Suggested
Books
L1, L2
T2
M1
T2
M1
1.Philosophy of
number systems
Methodology
Remarks
(Eg. T1,
T2,R5)
2.Complement
NUMBER
CODES
SYSTEMS
representation of
negative numbers
L3, L4
GATE & IES
3.Binary
arithmetic-binary
odes-error
detecting & error
correcting codes –
hamming codes.
TOTAL CLASSES
T2
L5 ,L6
L6
M1
2
.
1.Fundamental
postulates of
Boolean Algebra Basic theorems and
properties
UNIT-II
2.Switching
functions–
Canonical and
Standard formsAlgebraic
simplification
digital logic gates
BOOLEAN ALGEBRA
AND SWITCHING
FUNCTIONS
3.Properties of XOR
gates –universal
gates-Multilevel
NAND/NOR
realizations.
L9,L10, L11
T2
M1
T2
M1
T2
M1
L12,L13,L14
L15,L16
GATE & IES
L8
TOTAL CLASSES
3.
UNIT-III
MINIMIZATION OF
SWITCHING
FUNCTIONS
1.Map method,
Prime implicants,
Don’t care
combinations
L17,L18
T2
2.Minimal SOP and
POS forms,
Tabular Method
L19,L20
T2
3.Prime
–
Implicants chart,
M2
M2
M3
L21,L22,27
T2
TOTAL CLASSES
L7
4.
UNIT-IV
1
1.Design
using
conventional logic
gates
2.Encoder, Decoder,
L28,L29
T2
L30,L31
T2
M3
GATE & IES
M2
Multiplexer
3.De-Multiplexer,
Modular design
using IC chips
L32,L33
T2
L34,L35
T2
M1
Combinational Logic
Design
4.MUX Realization
of switching
functions Parity bit
generator
5.Code-converters,
Hazards and hazard
free realizations
TOTAL CLASSES
5.
UNIT-V
M1
GATE & IES
L36,L37,L38
T2
L11
1.Basic PLD’s-ROM,
PROM, PLA, PLD
M3
L39,L40
T2
2.Realization of
Switching functions
using PLD’s
PROGRAMMABLE
LOGIC DEVICES,
THRESHOLD LOGIC
3.Capabilities and
limitations of
Threshold gate,
M1
N.A
M2
L41,L42
4.Synthesis of
N.A
T2
Threshold
functions,Multigate
Synthesis
TOTAL CLASSES
6.
UNIT-VI
1.Classification of
sequential circuits
(Synchronous,
Asynchronous,
Pulse mode, Level
mode with
L4
L43
T2
M1
examples
SEQUENTIAL
CIRCUITS-I
2.Basic flip-flopsTriggering and
excitation tables.
Steps in
synchronous
sequential circuit
M1
L44,L45
T2
GATE & IES
3.Design of moduloN Ring & Shift
counters, Serial
binary
adder,sequence
detector.
M1
L46,L47,L48
T2
L6
TOTAL CLASSES
UNIT-VII
7.
SEQUENTIAL CIRCUITS
- II
1.Finite state
machine-capabilities
and limitations
2.Mealy and Moore
modelsminimization of
completely specified
and incompletely
specified sequential
machines
L49
T2,T1
M1
M1
L50,L51
T2,T1
3.Partition
techniques and
Merger chart
methods-concept of
minimal cover table
TOTAL CLASSES
8.
UNIT-VIII
M1
L52,53,54
GATE
T2,T1
L6
1.Salient features of
the ASM chartSimple examples
L55
2.System
design
using data path and
control subsystems
L56
T2
T2
M1
M1
ALGOROTHIMIC STATE
MACHINES
3.control
implementationsexamples of
Weighing machine
and Binary
multiplier
GATE & IES
M1
L57,L58
T2
L4
TOTAL CLASSES
OBJECTIVE & OUTCOME BASED PLAN FOR SUBJECT (OOPS)
FACULTY: K.PRAVEENA
DEPT: ECE
Lecture No.
SUBJECT: SWITCHING THEORY & LOGIC DESIGN
JNTUH Topic
Objective of each
Topic
Learning Outcome
Practical Inferences
Method
of
Teaching
UNIT – 1 NUMBER SYSTEMS & CODES
Philosophy of
L1, L2
L3, L4
L5 ,L6
L7,L8
number
systems.
complement
representation
of negative
numbers
Binary
arithmeticaddition,
subtraction
,multiplication
and division.
Error detecting
–parity codes
& error
correcting
codes –
hamming
codes
Explanation of the
decimal,
binary,
hexadecimal & octal
number systems
Explanation
of
complement
representation
of
negative no’s 1’s &
2’s complement
Explanation of Binary
addition,subtraction
,multiplication
&
division.
Explanation of the
error detecting parity codes & error
correcting –hamming
codes.
To know the different types of
numbering system
Complemented
representations like the decimal
complements
These number systems
are
used
in
Microprocessor
and
digital computers.
M1
This method is useful
in arithmetic logic
circuits and used in
computers
for
addition
and
subtraction.
M1
To know binary addition,
subtraction, multiplication and
division
Using binary number
system is execution
time will be less.
M1,M7
Knowledge about detection of
errors and to correct the errors
in digital circuits that are find
with the coding
Applications that
require extremely low
error rates (such as
digital money
transfers) must use
ARQ
M1
Boolean algebra is basis
of digital systems like
computers, calculators
etc.
M1
Boolean algebra as the
calculus of two values is
fundamental to digital
logic,
computer
programming,
and
mathematical logic, and
is also used in other
areas of mathematics
M1,M7
UNIT – 2 BOOLEAN ALGEBRA AND SWITCHING FUNCTIONS
L9,L10, L11
Fundamental
postulates of
Boolean
Algebra - Basic
theorems and
properties
L12,L13,L14
switching
functions–
Canonical and
Standard
formsAlgebraic
simplification.
Explanation
of
fundamental
postulates
of
Boolean algebra &
basic theorems
Explanation
of
switching functions
canonical & standard
forms-algebraic
simplifications.
To know the fundamental
concepts of Boolean algebra
Basic theorems to
reduce the complexity
and size of the digital circuits
such as set theory and
statistics.
L15,L16
digital logic
gates
properties of
XOR gates –
universal
gatesMultilevel
NAND/NOR
realizations
Explanation of digital
logic gates using
universal gates
Knowledge of universal gates
NAND & NOR
XOR gates used in
magnitude comparator
,parity generator &
used in adder and
subtractor.
M1,M5
UNIT – 3 MINIMIZATION OF SWITCHING FUNCTIONS
L17,L18
L19,L20
L21,L22,27
Map method,
Prime
implicants,
Don’t
care
combinations
Explanation of 2,3
and
4
variable
karnaugh maps
Minimal SOP
and POS forms,
Tabular
Method
Explanation
of
minimal SOP & POS
forms.
Prime –
Implicants
chart,
simplification
rules
Explanation
of
Tabular
method,
prime implicant chat,
simplification rules.
It is fast method of
simplification for upto 4
variable functions only.
To understand Map
method
M1
It gives visual method
of simplification.
Minimization of SOP and
POS forms
Tabular
method
simplifications
and
In this each term is
product of variables&
total function is sum of
OR function of terms.
M1,M6
It is developed while
minimizing
the
functions by forming
cubes. It is fast method
of simplification for up
to four variables.
M1
UNIT – 4 COMBINATIONAL LOGIC DESIGN
L28,L29
Design
using
conventional
logic gates
Explanation of design
using conventional
logic gates.
Designing
of
various
combinational circuits
Multiple input
single output
circuits
can
realized
conventional
gates.
and
logic
be
using
logic
M1
L30,L31
L32,L33
L34,L35
L36,L37,L38
Encoder,
Decoder,
Multiplexer
Design using encoder
and decoder.
DeMultiplexer,
Modular
design using IC
chips
Design using
multiplexerand demux.
MUX
Realization of
switching
functions
Parity bit
generator
Codeconverters,
Hazards and
hazard free
realizations
Modular design using
Ic chips, MUX
realization of
switching functions
Code converters and
hazard free
realization
This will be useful for doing
arithmetic operations
Designing
of
Encoder,
Decoder,
Multiplexer,
Demultiplexer
Micro
processor
memory system and
micro
processor
instruction decoding.
M1,M2
It is used to convert
BCD
into
seven
segment
display.It
can be used as logic
function generator.
M1,M4
It can be used as
logic function
generator in sop
form. parallel to
serial convertor.
Data distribution,
security monitoring
systems.
Designing of IC chips and
MUX realization
Hazard is getting
function value
opposite than
expected for small
span of time. These
hazards occurs in
combinational
circuits.
Explanation of hazards and
hazard free realizations
M1,M4
M1
UNIT – 5 MINIMIZATION OF SWITCHING FUNCTIONS
L39,L40
L41,L42
Basic
PLD’sROM, PROM,
PLA,
PLD
Realization of
Switching
functions using
PLD’s
Explanation of Basic
PLDs-PROM,PLA
&
realization
of
switching functions
using PLD’s.
Capabilities
and limitations
of
Threshold
gate, Synthesis
of
Threshold
functions,
Multigate
To
know
the
capabilities
and
limitations
of
threshold gate and
synthesis
of
threshold functions.
To design conventional logic
gates
and design
ROM,PROM,EPROM,EEPROM
To
design
PLD’s
Multigate synthesis
and
One application of a
PLA is to implement
the control over a
data path.
M1,M4
Display
ControllerImage Rotation, LCD
Control,
Display
Interface
Multiplexing/Demulti
plexing
M1,M4
Synthesis
UNIT – 6 SEQUENTIAL CIRCUITS - I
L43
L44,L45
L46,L47,L48
Classification
of sequential
circuits
Basic flip-flopsTriggering and
excitation
tables. Steps in
synchronous
sequential
circuit
Design of
modulo-N Ring
& Shift
counters, Serial
binary adder,
sequence
detector
Explanation
of
sequential circuits
Explanation of SR &
JK Flip flops and
excitation tables.
Explanation of design
of modulo-N ring
,serial adder and
sequence detector.
To classify the Sequential
circuits
Sequential
circuit
need
a
memory
component. It is
harder to design
M1,M2
Basic types of Flip flops and
designing of these flipflops
Flip flops are used as
Registers, latch or
memory element.
M1.M5
Counters are one of
the
many
applications
of
sequential logic that
has a widespread use
from simple digital
alarm
clocks
to
computer
memory
pointers.
M1,M5
Algorithmic
representation
like designing the
State
machines,
which
is
the
another way to
reduce
the
complexity
and
size
of
digital
circuits
M1,M2,
M10
This
introduces
the concept of
Melay
Moore
Machines
M1,M2,
M10
Designing serial adder
sequence detector.
and
UNIT – 7 SEQUENTIAL CIRCUITS - II
L49
Finite state
machinecapabilities
and limitations
L50,L51
Mealy and
Moore modelsminimization
of completely
specified and
Explanation of FSM
capabilities
&
limitations
Mealy & Moore
models differences
To know the algorithmic
representation
like
designing
the
State
machines, which is the
another way to reduce the
complexity and size of
digital circuits
This introduces the concept
of Melay Moore Machines
incompletely
specified
sequential
machines
L52,53,54
Partition
techniques and
Merger chart
methodsconcept of
minimal cover
table
Merger
chart
methods
and
concept of minimal
cover table.
To know merger chart methods
and minimal cover table.
To know merger
chart methods and
minimal cover table
M1
UNIT – 8 ALGORITHEMIC STATE MACHINES
L55
Salient
features of the
ASM chartSimple
examples
Explanation of ASM
chart.
L56
System design
using datapath
and control
subsystems
Explanation
of
system design using
data
path
and
control sub system.
control
implementatio
ns-examples of
Weighing
machine and
Binary
multiplier
Explanation
of
Weighting machine
and Binary multiplier
L57,L58
To know the features of
ASM charts
Design using data path and
control subsystems.
Implementation
multipliers
METHODS OF TEACHING:
M1 : Lecture Method
M6 : Tutorial
M2 : Demo Method
M7 : Assignment
of
Binary
ASM
chart
is
constructed
from
ASM blocks. It is
associated with one
specific block.
M1
Design using data
path and control
subsystems
M1
The binary multiplier
involves the shifting
and adding features.
M1
M3 : Guest Lecture
M8 : Industry Visit
M4 : Presentation /PPT
M9 : Project Based
M5 : Lab/Practical
M10 : Charts / OHP
(8) SUGGESTED BOOKS:
TEXTBOOKS :
1. Switching & Finite Automata theory – Zvi Kohavi, TMH,2nd Edition.
2. Digital Design – Morris Mano, PHI, 3rd Edition, 2006.
3. Switching Theory and Logic Design- A,Anand Kumar,2008,PHI.
REFERENCE BOOKS:
1. An Engineering Approach To Digital Design – Fletcher, PHI.
2. Fundamentals of Logic Design – Charles H. Roth, Thomson Publications, 5th Edition, 2004,
Thomson publications.
3. Digital Logic Applications and Design – John M. Yarbrough, Thomson Publications, 2006,
Thomson publications
(9) COURSE / SUBJECT OBJECTIVES:
1. To know the different types of numbering system
2. Complemental representations like the decimal complements
3. To detect the errors and to correct the errors in digital circuits that are find with the
coding
4. The fundamental concepts of Boolean algebra
5. Basic theorems to reduce the complexity and size of the digital circuits
6. Introduces the universal gates
7. To know the Map method
8. Minimization of SOP and POS forms
9. Tabular method and simplifications
10. Designing of various combinational circuits
11. This will be useful for doing arithmetic operations
12. Designing of Encoder,Decoder,Multiplexe,Demultiplexer
13. Hazards and hazard free realizations.
14. To design conventional logic gates
15. To design ROM,PROM,EPROM,EEPROM
16. To design PLD’s
17. Multigate synthesis
18. To classify the Sequential circuits
19. Basic types of Flip flops
20. Different types of Flip flops and designing of these flipflops
21. To know the algorithemic representation like designing the State machines,
which is thae another way to reduce the complexity and size of digital
circuits
22. This introduces the concept of Melay Moore Machines
23. Salient features of ASM charts
24. Implemetations of Binary multipliers
10. QUESTION BANK
UNIT-I
1. (a) Convert the following numbers:
i. (6753)8 to base 10
ii. (00111101.0101)2 to base 8 and base 4
iii. (95.75)10 to base 2.
(b) Represent +65 and -65 in sign-magnitude, sign-1’s complement and sign-2’s
Complement representation.
(c) Why the computer works for binary number system only?
2. Explain the procedure for the following with an example
(a) Conversion from Binary to decimal number
(b) Binary subtraction using 1's complement
(c) Binary subtraction using 2's complement
(d) Conversion from gray to binary number
3. (a) i. Convert (1596.675)10 to hexadecimal
ii. Convert (11110.1011)2 to decimal
iii. Convert (10110001.01101001)2 to octal
iv. Convert (235.0657)8 to Binary
(b) Obtain the 1's complement and 2's complement of the binary numbers
i. 1011011
ii. 0110101
iii. 10110
iv. 00110
4. a) Convert the number (17.125) to base 10, base 4, base 5 and base 2.
16
b) Perform the binary arithmetic operations on (-14)-(-2) using signed 2's complement representation.
c) Justify the statement that “Gray code is a class of reflected code”.
UNIT-II
1.(a) State and prove the following Boolean laws:
i. Commutative
ii. Associative
iii. Distributive.
(b) Find the complement of the following Boolean functions and reduce them to
minimum number of literals:
i. (bc’+ a’d) (ab’ + cd’)
ii. b’d + a’bc’ + acd + a’bc
(c) Which gate can be used as parity checker? Why?
2. Design an arithmetic circuit that adds 2 binary digits. The circuit should have 2
outputs, one for the sum and the other for the carry. Implement the same in a
PAL.
UNIT-III
1. (a) What are the advantages of Tabulation method over K-map?
(b) Simplify the following Boolean function using Tabulation method.
Y(A,B,C,D) = _(2,3,5,7,8,10,12,13)
2. Map the following function and simplify using K-Map
(a) F = (A+B+C)(A+B0+C)(A+B0+C0)(A0+B+C)
(b) F = (A0BC0D0+A0BC0D+AB0CD+AB0CD0+ABCD+A0B0C0D0)
3.a) Prove that if w'x + yz' = 0, then wx + y'(w' + z') = wx + xz + x'z' + w'y'z.
b) For the given function T(w,x,y,z) = Σ (0,1,2,3,4,6,7,8,9,11,15)
i) Show the map
ii) Find all prime implicants and indicate which are essential.
iii) Find a minimal expression for T and realize using basic gates. Is it unique?
4. Simplify the following to least number of literals using Boolean Algebra
(a) AB0CD0 +ABD0+BCD0+A0B+BC0
(b) X+XY0Z+X0YZ+XW+XW0+X0Y
(c) (AB+A0C+BC)(A+B0+AB0)
(d) (A+B+C0)(A+B0+C0)(A0+B+C0)(A0+B0+C0)
UNIT-IV
1. (a) Design 4-bit odd parity generator. Mention truth table.
(b) Using 4 MSI circuits construct a binary parallel adder to add two 16-bit binary
numbers. Label all carries between the MSI circuits.
2. Write short notes on Integrated circuits. Classify the ICs based on the levels of integration. Discuss on PLDS. What are the di_erent types of programmable devices?.
3.a) Design a 2-bit comparator which compares the magnitude of two numbers X and Y and generates
three output f1,f2, and f3.
b) Realize 16 × 1 Mux using only 2 × 1 Mux.
4. Implement the following functions using appropriate DECODER
F1 = _m(2,4,6,8,12)
F2 = _m(1,3,6,7,9,10)
F3 = _m(1,3,4,5,6,9,12,14)
F4 = _m(2,4,8)
UNIT-V
1. (a) Implement the following boolean functions using PLA.
f1(w,x,y,z) = P(0,1,3,5,9,13)
f2 (w,x,y,z) = P(0,2,4,5,7,9,11,15). [16]
(b) Write short notes on PLD’S.
2. (a) Implement the following boolean functions using PLA.
f1(w,x,y,z) = P(0,1,3,5,9,13)
f2 (w,x,y,z) = P(0,2,4,5,7,9,11,15).
(b) Write short notes on PLD’S.
3. .a) Realize the given function using PLD circuit.
F(x,y,z) = xy + yz + x'y' .
b) What is meant by Logic simulation, Functional simulation, timing simulation and Logic synthesis?
UNIT-VI
1. (a) Usign a shift register, how do you obtain a circular shift?
(b) Whta is the principle used to convert an even modulo counter into an odd
modulo counter?
2. Design a 4 bit counter that counts either in Binary or gray depending on the input
given to the select line. When select line = 0, the counter is to count in Binary,
and when select line = 1, the counter is to count in gray. Draw the logic diagram.
3. A sequential circuit has three D ip ops, A, B, C and one input x. The minterms
of the D ip ops are given below. Construct the State table and Draw an ASM
chart.
DA(X,A,B,C) = _ (0,3,4,7,9,10,13,14)
DB(X,A,B,C) = _ (4,5,6,7,12,13,14,15)
DC(X,A,B,C) = _ (2,3,6,7,10,11,14,15)
4. a) Design a BCD counter using JK Flip-Flops.
b) Write the differences between synchronous and asynchronous counters.
c) Draw the state diagram and characteristic table of Master Slave JK flip-flop.
UNIT-VII
1. Explain the following related to sequential ckts with suitable examples.
(a) State diagram
(b) State table
(c) State assignment.
2. a) Differentiate between Mealy and Moore machine with examples.
b) Write about the implementation of Binary multiplier.
3. a) Write the differences between completely specified function and incompletely specified functions
with examples.
b) Design an asynchronous sequential circuit with two inputs X and Y and with one output Z. Whenever Y
is 0, input X is transferred to Z, otherwise, the output remains same.
UNIT-VIII
1. Design the circuit using one flip flop per each state.
2. Design the ASM chart, Data path circuit & Control circuit to implement traditional
division of two four bit binary numbers.
11.Assignments:
UNIT-I
1. Give a brief description about the following number systems with suitable examples.
1.
2.
3.
4.
(a).Decimal number system
(b).Binary number system.
©.Octal number system
(d).Hexadecimal number system.
Generate hamming code for a 4bit XS3 message to detect and correct single bit errors.
Explain the complement representation of negative numbers with examples.
What is the gray code? what are the rules to construct gray code? Construct 4 bit gray code for the
decimal 0 to 15.
Convert the following Decimal and then to Binary
101116
ABCD16 72348 12810
UNIT-II
1.
2.
3.
State Boolean algebra postulates and explain in detail with examples.
What are logic gates? How do the gates differ from logic operators? Explain positive logic and
negative logic. Explain each term with examples.
What are universal gates? Why they are so called? Give their truth tables.
4.
a) State and Prove De Morgan's theorem of Boolean Algebra.
b) Determine the canonical product-of-sums and sum-of-products form of T(x,y,z) = x'(y' + z')
c) Realize the basic gates using NAND and NOR gates only.
UNIT-III
1.
2.
3.
4.
5.
What is k-map? Give its advantages and disadvantages?
What is a cell of a k-map? What is meant by pair, a quad an octet of a map and how many
variables are eliminated?
What do you mean by don care care combinations?
What do you mean by min terms and max terms of Boolean expressions?
List the Boolean function simplification rules using tabulation method.
UNIT-IV
1.
3.
4.
5.
What is hazard in switching circuits? Explain the design of hazard free switching circuit with an
example.
Design a combinational logic to subtract one bit from the other.Draw the logic diagram using
NAND and NOR gates.
Explain working of a serial adder.
Design a full adder circuit using 2 half adders.
Draw the block diagram of BCD adder using 4 bit parallel adder and logic gates
6.
What is decoder? Construct 3*8 decoder using logic gates and truth table
2.
UNIT-V
1.
2.
3.
Write short notes on PLD’s.
Draw the basic cell macro cell logic diagram and explain.
Explain general CPLD configuration with suitable block diagram.
4.
5.
6.
7.
Design XS3 to BCD convert using ROM and PAL.
Discuss the capabilities and limitations of threshold gate.
Explain synthesis of threshold functions with examples.
Write short notes on the properties of threshold functions.
UNIT-VI
1.
2.
3.
4.
5.
6.
7.
Compare synchronous and asynchronous circuits.
Classify the required circuits into synchronous , clock mode, pulse mode, with suitable examples.
Define the following terms in connection with a flip flop
Set up time
Hold time
Propagation delay time
Preset
Clear
Draw the circuit of JK master flip flop with active high clear and active low preset and explain its
operation.
Convert JK flip flop to T flip flop and RS flip flop to D flip flop.
Draw the circuit of RS master flip flop with active high clear and active low preset and explain its
operation.
Discuss the disadvantages due to level triggering. Explain the effects of level triggering in a JK
flip flop.
UNIT-VII
1.
2.
3.
4.
Explain the following related to sequential circuits with suitable examples.
State diagram
State table
State assignment.
Draw the diagram of Mealy type FSM for serial adder.
Draw the diagram of Moore type FSM for serial adder.
Explain merger chart methods of minimal convertible.
UNIT-VIII
1.
2.
3.
Explain in detail the block diagram of ASM chart.
Explain in detail the Mealy state diagram and ASM chart for it with an example
Design the ASM chart, data path, control circuit using multiplexer for binary multiplier.
11.1 SLIP TESTS:
1. List the Boolean function simplification rules using tabulation method.
2. Design a 4 bit parallel adder using full adders.
3 Design XS3 to BCD convert using ROM and PAL.
4 Define the following terms in connection with a flip flop
Set up time
5 Design the ASM chart, data path, control circuit using multiplexer for binary multiplier.
6 Draw the diagram of Moore type FSM for serial adder.
7 Draw the logic diagram of a SR latch using NOR gates. Explain its operation using excitation table.
11.2 TUTORIAL QUESTIONS
1. Explain the procedure for the following with an example
(a) Conversion from Binary to decimal number
(b) Binary subtraction using 1's complement
(c) Binary subtraction using 2's complement
(d) Conversion from gray to binary number
2.(a) State and prove the following Boolean laws:
i. Commutative
ii. Associative
iii. Distributive.
3. Find the complement of the following Boolean functions and reduce them to
minimum number of literals:
4. (a) What are the advantages of Tabulation method over K-map?
(b) Simplify the following Boolean function using Tabulation method.
5. Write short notes on Integrated circuits. Classify the ICs based on the levels of inte-gration. Discuss on
PLDS. What are the di_erent types of programmable devices?.
6. Design a 4 bit counter that counts either in Binary or gray depending on the input
given to the select line. When select line = 0, the counter is to count in Binary,
and when select line = 1, the counter is to count in gray. Draw the logic diagram.
7. Explain the following related to sequential ckts with suitable examples.
(a) State diagram
(b) State table
(c) State assignment.
8.
Design the ASM chart, Data path circuit & Control circuit to implement traditional division of two
four bit binary numbers.
12.ASSESSMENT PLAN FOR ACTIONS:
12.1: Assessment plan for Assignments:
Content
Weightage
Problems
80%
Descriptive
10%
Analytical/
Reasoning
10%
12.2: Assessment plan for Slip Test:
Content
Weightage
Analyzing the
problems
80%
Theoretical
questions
10%
Reasoning
10%
13. GATE
1. X=01110 and Y=11001 are two 5-bit binary numbers represented in Two’s complement format. The sum
of X and Y represented in Two’s complement format using 6 bit is
A) 100111
B) 001000
C) 000111
D) 101001
2. The Boolean function Y=AB+CD is to be realized using only 2-input NAND gates. The minimum
number of gates required is
A) 2
B) 3
C) 4
D) 5
3. The Boolean Expression Y=A’B’C’D+A’BCD’+AB’C’D+ABC’D’ can be minimized to
A)Y=A’B’C’D+A’BC’+AC’D
B)Y=A’B’C’D+BCD’+AB’C’D C)Y=A’BCD’+B’C’D+AB’C’D
D) Y=A’BCD’+B’C’D+ABC’D’
4.The circuit diagram of a standard TTL NOT gate is shown in figure. When V1 =2.5
operation of the transistor will be
V,the modes of
A) Q1: reverse active Q2: normal active Q3: saturation Q4: cut-off
B) Q1: reverse active Q2: saturation Q3: saturation Q4: cut-off
C) Q1: normal active Q2: cut-off
Q3: cut-off Q4: saturation
D) Q1: saturation Q2: saturation
Q3 saturation: Q4: normal active
15. The following circuit X is given by
Department of Electronics& Communication Engineering
CMR Engineering College
a)X=AB’C’+A’BC’+A’B’C+ABC
b) X=A’BC+AB’C+ABC’+A’B’C’
c)X=AB+BC+AC
d) X=A’B’+B’C’+A’C’
14. OBJECTIVE QUESTIONS:
Code No: 07A4EC09 Set No. 1
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II B.Tech. II Sem., II Mid-Term Examinations, April/May – 2010
SWITCHING THEORY AND LOGIC DESIGN
Objective Exam
Name: ______________________________ Hall Ticket No.
Answer All Questions. All Questions Carry Equal Marks.Time: 20 Min. Marks: 20.
I Choose the correct alternative:
1. An n-stage ripple counter can count up to [ ]
n
n
n-1
(a) 2 (b) 2 -1 (c) n (d) 2
2. A mod-13 counter must have [ ]
(a) 13 flip flops (b) 3 flip flops (c) 4 flip flops (d) synchronous clocking
3. In programmable logic array [ ]
(a) AND –array is fixed &OR- array is programmable
(b) AND-array is programmable & OR-array is fixed
(c) both AND &OR array are programmable
(d) both AND &OR array are fixed
4. Total no.of programmable fuses in ‘n’ input ‘m’ output PROM is [ ]
m
(a) n (b) nXm (c) 2nXm (d) 2 Xn
5. A decision box in an ASM chart [ ]
(a) does not have exit paths (b) have only one exit path
(c) has two exit paths (d) has one entry and has one exit path
6. The functional difference between an SR flip-flop and J-K flip-flop is that [ ]
(a) J-K flip-flop is faster (b) J-K flip-flop has feedback
(c) J-K flip-flop accepts both inputs 1 (d) J-K flip-flop does not require clock
7. An Asynchronous counter differs from synchronous counter in [ ]
(a) Mod number (b) Method of clocking
(c) the type of flip-flops used (d) the numberof states in a sequence
8. To serially shift a byte of data in to shift register there must be [ ]
(a)1 clock pulse (b)one load pulse (c)eight clock pulses d)one clock pulse in each 1 in the data
9. Programming a PLD device means [ ]
(a) writing software program (b) blowing electronic fuses
(c) writing assembly language program (d) writing C program
10. When power supply of ROM is switched off, its contents [ ]
(a) becomes zero (b) becomes all ones (c) remains same (d) are unpredictable
Cont…..2
II Fill in the blanks:
11. The sequential circuit is a combination of ______________________________
12. The characteristic equation of J-K flip flop is ______________
13. If the binary word 1101 is entered serially into the 4-bit serial in parallel out shift register (initially clear), the Q outputs after
two clock pulses are _________
14. A combinational PLD with programmable AND array and programmable OR array is called as __________
1
II/IIB.Tech-ECE Academic Planner for AY 2013-14
Department of Electronics& Communication Engineering
CMR Engineering College
15. Next state variables in asynchronous sequential circuits are called __________________
16. A counter that triggers all the flip-flops together is called _______________ counter.
17. In synchronous circuit output depends only on the present state of flip-flop is called ______________
18. The full form of PROM is ________________________
19. ______________ is a pictorial representation of behavior of a sequential circuit.
20. A Jhonson counter uses __________ flip flops.
-oOowww.jntuworld.com www.jntuworld.com www.jwjobs.net
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II B.Tech. II Sem., II Mid-Term Examinations, April/May – 2010
SWITCHING THEORY AND LOGIC DESIGN
Objective Exam
Name: ______________________________ Hall Ticket No.
Answer All Questions. All Questions Carry Equal Marks.Time: 20 Min. Marks: 20.
I Choose the correct alternative:
1. Total no.of programmable fuses in ‘n’ input ‘m’ output PROM is [ ]
m
(a) n (b) nXm (c) 2nXm (d) 2 Xn
2. A decision box in an ASM chart [ ]
(a) does not have exit paths (b) have only one exit path
(c) has two exit paths (d) has one entry and has one exit path
3. The functional difference between an SR flip-flop and J-K flip-flop is that [ ]
(a) J-K flip-flop is faster (b) J-K flip-flop has feedback
(c) J-K flip-flop accepts both inputs 1 (d) J-K flip-flop does not require clock
4. An Asynchronous counter differs from synchronous counter in [ ]
(a) Mod number (b) Method of clocking
(c) the type of flip-flops used (d) the number of states in a sequence
5. To serially shift a byte of data in to shift register there must be [ ]
(a)1 clock pulse (b)one load pulse (c)eight clock pulses (d)one clock pulse in each 1 in the data
6. Programming a PLD device means [ ]
(a) writing software program (b) blowing electronic fuses
(c) writing assembly language program (d) writing C program
7. When power supply of ROM is switched off, its contents [ ]
(a) becomes zero (b) becomes all ones (c) remains same (d) are unpredictable
8. An n-stage ripple counter can count up to [ ]
n
n
n-1
(a) 2 (b) 2 -1 (c) n (d) 2
9. A mod-13 counter must have [ ]
(a) 13 flip flops (b) 3 flip flops (c) 4 flip flops (d) synchronous clocking
10. In programmable logic array [ ]
(a) AND –array is fixed &OR- array is programmable
(b) AND-array is programmable & OR-array is fixed
(c) both AND &OR array are programmable
(d) both AND &OR array are fixed
Cont…..2
II Fill in the blanks:
11. A combinational PLD with programmable AND array and programmable OR array is called as ________________
12. Next state variables in asynchronous sequential circuits are called __________________
13. A counter that triggers all the flip-flops together is called _______________ counter.
14. In synchronous circuit output depends only on the present state of flip-flop is called ______________
15. The full form of PROM is ________________________
16. ______________ is a pictorial representation of behavior of a sequential circuit.
2
II/IIB.Tech-ECE Academic Planner for AY 2013-14
Department of Electronics& Communication Engineering
CMR Engineering College
17. A Jhonson counter uses __________ flip flops.
18. The sequential circuit is a combination of ______________________________
19. The characteristic equation of J-K flip flop is _____________
20. If the binary word 1101 is entered serially into the 4-bit serial in parallel out shift register (initially clear), the Q outputs after
two clock pulses are _________
-oOoJAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II B.Tech. II Sem., II Mid-Term Examinations, April/May – 2010
SWITCHING THEORY AND LOGIC DESIGN
Objective Exam
Name: ______________________________ Hall Ticket No.
Answer All Questions. All Questions Carry Equal Marks.Time: 20 Min. Marks: 20.
I Choose the correct alternative:
1. The functional difference between an SR flip-flop and J-K flip-flop is that [ ]
(a) J-K flip-flop is faster (b) J-K flip-flop has feedback
(c) J-K flip-flop accepts both inputs 1 (d) J-K flip-flop does not require clock
2. An Asynchronous counter differs from synchronous counter in [ ]
(a) Mod number (b) Method of clocking
(c) the type of flip-flops used (d) the number of states in a sequence
3. To serially shift a byte of data in to shift register there must be [ ]
(a)1 clock pulse (b)one load pulse (c)eight clock pulses (d)one clock pulse in each 1 in the data
4. Programming a PLD device means [ ]
(a) writing software program (b) blowing electronic fuses
(c) writing assembly language program (d) writing C program
5. When power supply of ROM is switched off, its contents [ ]
(a) becomes zero (b) becomes all ones (c) remains same (d) are unpredictable
6. An n-stage ripple counter can count up to [ ]
n
n
n-1
(a) 2 (b) 2 -1 (c) n (d) 2
7. A mod-13 counter must have [ ]
(a) 13 flip flops (b) 3 flip flops (c) 4 flip flops (d) synchronous clocking
8. In programmable logic array [ ]
(a) AND –array is fixed &OR- array is programmable
(b) AND-array is programmable & OR-array is fixed
(c) both AND &OR array are programmable
(d) both AND &OR array are fixed
9. Total no.of programmable fuses in ‘n’ input ‘m’ output PROM is [ ]
m
(a) n (b) nXm (c) 2nXm (d) 2 Xn
10. A decision box in an ASM chart [ ]
(a) does not have exit paths (b) have only one exit path
(c) has two exit paths (d) has one entry and has one exit path
Cont…..2
II Fill in the blanks:
11. A counter that triggers all the flip-flops together is called _______________ counter.
12. In synchronous circuit output depends only on the present state of flip-flop is called ______________
13. The full form of PROM is ________________________
14. ______________ is a pictorial representation of behavior of a sequential circuit.
15. A Jhonson counter uses __________ flip flops.
16. The sequential circuit is a combination of ______________________________
17. The characteristic equation of J-K flip flop is ______________
18. If the binary word 1101 is entered serially into the 4-bit serial in parallel out shift register (initially clear), the Q outputs after
two clock pulses are _________
3
II/IIB.Tech-ECE Academic Planner for AY 2013-14
Department of Electronics& Communication Engineering
CMR Engineering College
19. A combinational PLD with programmable AND array and programmable OR array is called as _________________
20. Next state variables in asynchronous sequential circuits are called __________________
-oOowww.jntuworld.com www.jntuworld.com www.jwjobs.net
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II B.Tech. II Sem., II Mid-Term Examinations, April/May – 2010
SWITCHING THEORY AND LOGIC DESIGN
Objective Exam
Name: ______________________________ Hall Ticket No.
Answer All Questions. All Questions Carry Equal Marks.Time: 20 Min. Marks: 20.
I Choose the correct alternative:
1. To serially shift a byte of data in to shift register there must be [ ]
(a)1 clock pulse (b)one load pulse (c)eight clock pulses (d)one clock pulse in each 1 in the data
2. Programming a PLD device means [ ]
(a) writing software program (b) blowing electronic fuses
(c) writing assembly language program (d) writing C program
3. When power supply of ROM is switched off, its contents [ ]
(a) becomes zero (b) becomes all ones (c) remains same (d) are unpredictable
4. An n-stage ripple counter can count up to [ ]
n
n
n-1
(a) 2 (b) 2 -1 (c) n (d) 2
5. A mod-13 counter must have [ ]
(a) 13 flip flops (b) 3 flip flops (c) 4 flip flops (d) synchronous clocking
6. In programmable logic array [ ]
(a) AND –array is fixed &OR- array is programmable
(b) AND-array is programmable & OR-array is fixed
(c) both AND &OR array are programmable
(d) both AND &OR array are fixed
7. Total no.of programmable fuses in ‘n’ input ‘m’ output PROM is [ ]
m
(a) n (b) nXm (c) 2nXm (d) 2 Xn
8. A decision box in an ASM chart [ ]
(a) does not have exit paths (b) have only one exit path
(c) has two exit paths (d) has one entry and has one exit path
9. The functional difference between an SR flip-flop and J-K flip-flop is that [ ]
(a) J-K flip-flop is faster (b) J-K flip-flop has feedback
(c) J-K flip-flop accepts both inputs 1 (d) J-K flip-flop does not require clock
10. An Asynchronous counter differs from synchronous counter in [ ]
(a) Mod number (b) Method of clocking
(c) the type of flip-flops used (d) thenumber of states in a sequence
Cont…..2
II Fill in the blanks:
11. The full form of PROM is ________________________
12. ______________ is a pictorial representation of behavior of a sequential circuit.
13. A Jhonson counter uses __________ flip flops.
14. The sequential circuit is a combination of ______________________________
15. The characteristic equation of J-K flip flop is _________________
16. If the binary word 1101 is entered serially into the 4-bit serial in parallel out shift register (initially clear), the Q outputs after
two clock pulses are _________
17. A combinational PLD with programmable AND array and programmable OR array is called as _________________
18. Next state variables in asynchronous sequential circuits are called __________________
4
II/IIB.Tech-ECE Academic Planner for AY 2013-14
Department of Electronics& Communication Engineering
CMR Engineering College
19. A counter that triggers all the flip-flops together is called _______________ counter.
20. In synchronous circuit output depends only on the present state of flip-flop is called ______________
-oOoCode No: 54010 Set No. 1
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II B.Tech. II Sem., I Mid-Term Examinations, February – 2012
SWITCHING THEORY AND LOGIC DESION
Objective Exam
Name: ______________________________ Hall Ticket No.
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.
I Choose the correct alternative:
1. The minimum number of bits required to represent negative numbers in the range of -1 to -11 using 2’s complement arithmetic
is [ ]
(a)2 (b) 3 (c) 4 (d) 5
2. The following code is not a BCD code. [ ]
a)Gray code (b) Xs-3 code (c) 8421 code (d) All of these
3. A 15-bit hamming code requires [ ]
(a)4 parity bits (b) 5 parity bits (c) 15 parity bits (d) 7 parity bits
4. The logic expression (A+B)(+) can be implemented by giving the inputs A and B to a two-input [ ]
(a)NOR gate (b) NAND gate (c) X-OR gate (d) X-NOR gate
5. Which of the following Boolean algebraic expressions is incorrect? [ ]
(a)A+B=A+B (b) A+AB=B (c) (A+B)(A+C)=A+BC (d) (A+)(A+B)=A
6. If=5,the base(radix) of the number system is [ ]
a)5 (b) 6 (c) 7 (d) 8
7. The hexadecimal number system is used in digital computers and digital systems to [ ]
(a) Perform arithmetic operations (b) Perform logic operations
(c) Perform arithmetic and logic operations (d) Input binary data into the system.
8. The logic expression A+B can be implemented by giving inputs A and B to a two-input [ ]
(a)NOR gate (b) NAND gate (c) X-OR gate (d) X-NOR gate
9. A gate is enabled when its enable input is at logic 0. The gate is [ ]
(a)NOR (b) AND (c) NAND (d) None of these
10. The output of a logic gate is 1 , when all its inputs are at logic 0.The gate is either [ ]
(a)a NOR or an X-NOR (b) a NAND or an X-OR
(c) an OR or an X-NOR (d) an AND or an X-OR
Cont…..2
II Fill in the blanks:
11. In b’s complement method, the carry is ______ and in(b-1)’s complement method the carry is _______
12. The MSB of a binary number has a weight of 512,the number consists of _________ bits.
13. __________ are codes which represent letters of the alphabets and decimal numbers as
a sequence of 0s and 1s.
14. The interconnection of gates to perform a variety of logical operations is called ___________
15. The NOR gate can function as a NOT gate if _______________
16. The implicants which will definitely occur in the final expression are called _____________________.
17. The prime implicant mode of a bunch of 0s is called a __________________________.
18. ______________ is a process of converting familiar numbers or symbols into a coded format.
19. A decoder with 64 output lines has _____ select lines.
20. A decimal – to – BCD encoder is a ________ line to ____ line encoder.
-o0oJAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II B.Tech. II Sem., I Mid-Term Examinations, February – 2012
SWITCHING THEORY AND LOGIC DESION
5
II/IIB.Tech-ECE Academic Planner for AY 2013-14
Department of Electronics& Communication Engineering
CMR Engineering College
Objective Exam
Name: ______________________________ Hall Ticket No.
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.
I Choose the correct alternative:
1. The logic expression (A+B)(+) can be implemented by giving the inputs A and B to a two-input [ ]
(a)NOR gate (b) NAND gate (c) X-OR gate (d) X-NOR gate
2. Which of the following Boolean algebraic expressions is incorrect? [ ]
(a)A+B=A+B (b) A+AB=B (c) (A+B)(A+C)=A+BC (d) (A+)(A+B)=A
3. If=5,the base(radix) of the number system is [ ]
a)5 (b) 6 (c) 7 (d) 8
4. The hexadecimal number system is used in digital computers and digital systems to [ ]
(a) Perform arithmetic operations (b) Perform logic operations
(c)Perform arithmetic and logic operations (d) Input binary data into the system.
5. The logic expression A+B can be implemented by giving inputs A and B to a two-input [ ]
(a)NOR gate (b) NAND gate (c) X-OR gate (d) X-NOR gate
6. A gate is enabled when its enable input is at logic 0. The gate is [ ]
(a)NOR (b) AND (c) NAND (d) None of these
7.. The output of a logic gate is 1 , when all its inputs are at logic 0.The gate is either [ ]
(a)a NOR or an X-NOR (b) a NAND or an X-OR
(c) an OR or an X-NOR (d) an AND or an X-OR
8. The minimum number of bits required to represent negative numbers in the range of -1 to -11 using 2’s complement arithmetic
is [ ]
(a)2 (b) 3 (c) 4 (d) 5
9. The following code is not a BCD code. [ ]
a)Gray code (b) Xs-3 code (c) 8421 code (d) All of these
10. A 15-bit hamming code requires [ ]
(a)4 parity bits (b) 5 parity bits (c) 15 parity bits (d) 7 parity bits
Cont…..2
II Fill in the blanks:
11. The interconnection of gates to perform a variety of logical operations is called ______________
12. The NOR gate can function as a NOT gate if _________________
13. The implicants which will definitely occur in the final expression are called _____________________.
14. The prime implicant mode of a bunch of 0s is called a __________________________.
15. ______________ is a process of converting familiar numbers or symbols into a coded format.
16. A decoder with 64 output lines has _____ select lines.
17. A decimal – to – BCD encoder is a ________ line to ____ line encoder.
18. In b’s complement method, the carry is _______ and in(b-1)’s complement method the carry is ____
19. The MSB of a binary number has a weight of 512,the number consists of ___________ bits.
20. ___________ are codes which represent letters of the alphabets and decimal numbers as
a sequence of 0s and 1s.
-o0oJAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II B.Tech. II Sem., I Mid-Term Examinations, February – 2012
SWITCHING THEORY AND LOGIC DESION
Objective Exam
Name: ______________________________ Hall Ticket No.
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.
I Choose the correct alternative:
1. If=5,the base(radix) of the number system is [ ]
a)5 (b) 6 (c) 7 (d) 8
2. The hexadecimal number system is used in digital computers and digital systems to [ ]
(a) Perform arithmetic operations (b) Perform logic operations
6
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(c )Perform arithmetic and logic operations (d) Input binary data into the system.
3. The logic expression A+B can be implemented by giving inputs A and B to a two-input [ ]
(a)NOR gate (b) NAND gate (c) X-OR gate (d) X-NOR gate
4. A gate is enabled when its enable input is at logic 0. The gate is [ ]
(a)NOR (b) AND (c) NAND (d) None of these
5. The output of a logic gate is 1 , when all its inputs are at logic 0.The gate is either [ ]
(a)a NOR or an X-NOR (b) a NAND or an X-OR
(c) an OR or an X-NOR (d) an AND or an X-OR
6. The minimum number of bits required to represent negative numbers in the range of -1 to -11 using 2’s complement arithmetic
is [ ]
(a)2 (b) 3 (c) 4 (d) 5
7. The following code is not a BCD code. [ ]
a)Gray code (b) Xs-3 code (c) 8421 code (d) All of these
8. A 15-bit hamming code requires [ ]
(a)4 parity bits (b) 5 parity bits (c) 15 parity bits (d) 7 parity bits
9. The logic expression (A+B)(+) can be implemented by giving the inputs A and B to a two-input [ ]
(a)NOR gate (b) NAND gate (c) X-OR gate (d) X-NOR gate
10. Which of the following Boolean algebraic expressions is incorrect? [ ]
(a)A+B=A+B (b) A+AB=B (c) (A+B)(A+C)=A+BC (d) (A+)(A+B)=A
Cont…..2
II Fill in the blanks:
11. The implicants which will definitely occur in the final expression are called __________________.
12. The prime implicant mode of a bunch of 0s is called a __________________________.
13. ______________ is a process of converting familiar numbers or symbols into a coded format.
14. A decoder with 64 output lines has _____ select lines.
15. A decimal – to – BCD encoder is a ________ line to ____ line encoder.
16. In b’s complement method, the carry is_________ and in(b-1)’s complement method the carry is _______
17. The MSB of a binary number has a weight of 512,the number consists of ___________ bits.
18. ______________ are codes which represent letters of the alphabets and decimal numbers as
a sequence of 0s and 1s.
19. The interconnection of gates to perform a variety of logical operations is called ______________
20. The NOR gate can function as a NOT gate if _________________
-o0oJAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II B.Tech. II Sem., I Mid-Term Examinations, February – 2012
SWITCHING THEORY AND LOGIC DESION
Objective Exam
Name: ______________________________ Hall Ticket No.
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.
I Choose the correct alternative:
1. The logic expression A+B can be implemented by giving inputs A and B to a two-input [ ]
(a)NOR gate (b) NAND gate (c) X-OR gate (d) X-NOR gate
2. A gate is enabled when its enable input is at logic 0. The gate is [ ]
(a)NOR (b) AND (c) NAND (d) None of these
3. The output of a logic gate is 1 , when all its inputs are at logic 0.The gate is either [ ]
(a)a NOR or an X-NOR (b) a NAND or an X-OR
(c) an OR or an X-NOR (d) an AND or an X-OR
4. The minimum number of bits required to represent negative numbers in the range of -1 to -11 using 2’s complement arithmetic
is [ ]
(a)2 (b) 3 (c) 4 (d) 5
5. The following code is not a BCD code. [ ]
7
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CMR Engineering College
a)Gray code (b) Xs-3 code (c) 8421 code (d) All of these
6. A 15-bit hamming code requires [ ]
(a)4 parity bits (b) 5 parity bits (c) 15 parity bits (d) 7 parity bits
7. The logic expression (A+B)(+) can be implemented by giving the inputs A and B to a two-input [ ]
(a)NOR gate (b) NAND gate (c) X-OR gate (d) X-NOR gate
8. Which of the following Boolean algebraic expressions is incorrect? [ ]
(a)A+B=A+B (b) A+AB=B (c) (A+B)(A+C)=A+BC (d) (A+)(A+B)=A
9. If=5,the base(radix) of the number system is [ ]
a)5 (b) 6 (c) 7 (d) 8
10. The hexadecimal number system is used in digital computers and digital systems to [ ]
(a) Perform arithmetic operations (b) Perform logic operations
(c)Perform arithmetic and logic operations (d) Input binary data into the system.
Cont…..2
II Fill in the blanks:
11. ______________ is a process of converting familiar numbers or symbols into a coded format.
12. A decoder with 64 output lines has _____ select lines.
13. A decimal – to – BCD encoder is a ________ line to ____ line encoder.
14. In b’s complement method, the carry is ________ and in(b-1)’s complement method the carry is _______
15. The MSB of a binary number has a weight of 512,the number consists of ____________ bits.
16. _____________ are codes which represent letters of the alphabets and decimal numbers as
a sequence of 0s and 1s.
17. The interconnection of gates to perform a variety of logical operations is called _____________
18. The NOR gate can function as a NOT gate if ___________________
19. The implicants which will definitely occur in the final expression are called ________________.
20. The prime implicant mode of a bunch of 0s is called a __________________________.
-o0owww.jntuworld.com www.jntuworld.com www.jwjobs.net
15.TOPICS FOR STUDENTS SEMINAR
1.
2.
3.
4.
5.
8
ROM,PROM P,PLA Realization
Hazards and hazard free realization.
Counters
Multiplexer
Encoders and decoders.
II/IIB.Tech-ECE Academic Planner for AY 2013-14
Department of Electronics& Communication Engineering
CMR Engineering College
1. LABORATORY DETAILS
1.2
1.2.1
ECA Lab
1.2.1
Objectives and Relevance
1.2.2
Scope
1.2.3
Prerequisites
1.2.4
Syllabus
1.2.5
LEAD Experiments
1.2.6
Lab Schedule
1.2.7
Suggested Books
1.2.8
Websites
1.2.9
Experts’ Details
OBJECTIVES AND RELEVANCE
The main objective of this lab is to gain practical hands on experience by exposing the students to electronic circuit
design using Multisim simulation software.
1.2.2
SCOPE
Understanding of ECA lab has the scope to make the learner comfortable to work in the area of electronic design and
also to implement various projects on amplifiers using Multisim software.
1.2.3
PREREQUISITES
Theoretical knowledge on subject Electronic Devices and Circuits is required. Also student should be acquainted with
Multisim Design Suite.
PREAMBLE
This lab covers the experiments in ECA subject. The JNTU has given 17 experiments in the syllabus out of which 12
experiments are compulsory.
1.2.4
SYLLABUS - JNTU
PART-I: Design and Simulation in Simulation Laboratory using any Simulation Software.
(Any 6 Experiments):
1. Common Emitter Amplifier.
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2. Common Source Amplifier.
3. Two Stage RC Coupled Amplifiers.
4. Current Shunt and Voltage Series Feedback Amplifier.
5. Cascode Amplifier.
6. Wien Bridge Oscillator using Transistors.
7. RC Phase Shift Oscillator using Transistors.
8. Class A Power Amplifier (Transformer less).
9. Class B Complementary Symmetry Amplifier.
10. Common Base (BJT)/Common Gate (JFET) Amplifier.
PART-II: Testing in the Hardware Laboratory (6 Experiments)
A) Any Three circuits simulated in Simulation laboratory
B) Any Three of the following.
1.
Class A Power Amplifier(with transformer load)
2.
Class C Power Amplifier
3.
Single Tuned Voltage Amplifier
4.
Hartley & Colpitt’s Oscillators
5.
Darlington Pair
6.
MOS Amplifier
Note: Any SIX of the above experiments from each part are to be conducted (Total 12)
EXPERIMENT NO. 1
Common Emitter Amplifier
OBJECTIVE
To analyze the performance of given CE amplifier circuit with respect to gain & band width.
PREREQUISITES
Basic knowledge of BJT and Multisim design suite.
DESCRIPTION
The CE amplifier provides high gain and wide frequency response. The emitter lead is common to both the input and
output circuits are grounded. The emitter base junction is at forward biased .The collector current is controlled by the base current
rather than the emitter current. The input signal is applied to the base terminal of the transistor and amplified output taken across
collector terminal. A very small change in base current produces a much larger change in collector current. When the positive is
fed to input circuit it opposes forward bias of the circuit which cause the collector current to decrease, it decreases the more
negative. Thus when input cycle varies through a negative half cycle, increases the forward bias of the circuit, which causes the
collector current increases .Thus the output signal in CE is out of phase with the input signal.
APPLICATIONS
1. Low frequency voltage amplifier.
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2. Radio frequency circuits.
EXPERIMENT NO.2
Common Source Amplifier
OBJECTIVE
To analyze the performance of given CS amplifier circuit with respect to gain & bandwidth.
PREREQUISITES
Basic knowledge of FET and Multisim design suite.
DESCRIPTION
A weak signal is applied between gate and source and output is obtained at drain. For the proper operation of
FET, gate must be reverse biased. A small change in reverse bias on the gate produces a large drain current. This fact makes FET
capable of raising the strength of a weak signal. The gain of the common source FET amplifier is very high which is greater than
unity.
The most common decoder circuit is an n-to-2n decoder or binary decoder. Such a decoder has an n-bit binary input code
and a 1-out-of-2n output code. A binary decoder is used when you need to activate exactly one of 2 n outputs based on an n-bit
input value.
APPLICATIONS
1. Voltage amplifier.
2. Transconductance amplifier.
EXPERIMENT NO.3
Two Stage RC Coupled Amplifier.
OBJECTIVE
To analyze the performance of given Two stage RC coupled amplifier circuit with respect to gain & bandwidth.
PREREQUISITES
Basic knowledge of single stage amplifiers and Multisim design suite.
DESCRIPTION
This is most popular type of coupling as it provides excellent audio fidelity.
A coupling capacitor is used to connect output of first stage to input of second stage. Resistances R1, R2,Re form biasing and
stabilization network. Emitter bypass capacitor offers low reactance paths to signal coupling Capacitor transmits ac signal,
blocks DC. Cascade stages amplify signal and overall gain is increased total gain is less than product of gains of individual
stages. Thus for more gain coupling is done and overall gain of two stages equals to A=A1*A2
A1=voltage gain of first stage A2=voltage gain of
second stage.
When ac signal is applied to the base of the transistor, its amplified output appears across the collector resistor Rc.It is given to
the second stage for further amplification and signal appears with more strength. Frequency response curve is obtained by
plotting a graph between frequency and gain in db .The gain is constant in mid frequency range and gain decreases on both sides
of the mid frequency range. The gain decreases in the low frequency range due to coupling capacitor Cc and at high frequencies
due to junction capacitance Cbe.
APPLICATIONS
1. Impedance matching.
2. Voltage amplifier.
3. Increased power gain.
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EXPERIMENT NO.4
Voltage Series Feedback Amplifier.
OBJECTIVE
To write VHDL program for comparator and do simulation and synthesis. To study the effect of voltage series feedback on gain &
bandwidth of the amplifier.
PREREQUISITES
Basic knowledge of negative feedback amplifiers and Multisim design suite.
DESCRIPTION
When any increase in the output signal results into the input in such a way as to cause the decrease in the output
signal, the amplifier is said to have negative feedback.
The advantages of providing negative feedback are that the transfer gain of the amplifier with feedback can be stabilized against
variations in the hybrid parameters of the transistor or the parameters of the other active devices used in the circuit. The most
advantage of the negative feedback is that by prepare use of this , there is significant improvement in the frequency response and
in the linearity of the operation of the amplifier. This disadvantage of the negative feedback is that the voltage gain is decreased.
In Voltage-Series feedback, the input impedance of the amplifier is decreased and the output impedance is increased.
Noise and distortions are reduced considerably.
APPLICATIONS
1. Emitter Follower.
EXPERIMENT NO. 5
RC Phase Shift Oscillator.
OBJECTIVE
To obtain the frequency of oscillations for given RC Phase Shift Oscillator.
PREREQUISITES
Basic kno wledge of oscillators and Multisim design suite.
RC-Phase shift Oscillator has a CE amplifier followed by three sections of RC phase shift feedback networks. The
output of the last stage is return to the input of the amplifier. The values of R and C are chosen such that the phase shift
of each RC section is 60º. Thus the RC ladder network produces a total phase shift of 180º between its input and output
voltage for the given frequencies. Since CE Amplifier produces 180 º phases shift the total phase shift from the base of
the transistor around the circuit and back to the base will be exactly 360º or 0º. This satisfies the Barkhausen condition
for sustaining oscillations and total loop gain of this circuit is greater than or equal to 1, this condition used to generate
the sinusoidal oscillations.
The frequency of oscillations of RC-Phase Shift Oscillator is,
f = 1 / (2πRC* √6)
APPLICATIONS
1. Audio frequency oscillators.
2. Voice synthesis.
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3. Musical instruments.
4. GPS units.
EXPERIMENT NO. 6
Wien Bridge Oscillator
OBJECTIVE
To obtain the frequency of oscillations for given RC Phase Shift Oscillator.
PREREQUISITES
Basic kno wledge of oscillators and Multisim design suite.
DESCRIPTION
The Wien Bridge oscillator consists of two RC coupled Amplifiers which provide a phase of 360° or 0°. A balanced
bridge is used as the feedback network which has no need to provide additional phase shift to satisfy the Barkhausen criteria for
sustain the oscillations. The loop gain of the circuit is greater than equal to one, this condition generates the sinusoidal
oscillations. The feedback network consists of Lead Lag network and a Voltage divider. The Lead Lag network provides the
positive feedback to the input of the first stage and the voltage divider provides a negative feedback to the emitter of the first
stage. The frequency of oscillations is
f = 1 / (2πRC)
APPLICATIONS
1. To provide excitation for ac bridges
2. To provide a signal for testing filters.
3. Excitation for LVDT
4. To produce pure tones.
5. Distortion testing of power amplifiers.
1.2.5
LEAD EXPERIMENTS:
EXPERIMENT NO. 01
Single Tuned Voltage Amplifier.
OBJECTIVE
To plot the frequency response of a single tuned voltage amplifier.
APPARATUS
Multisim design suite.
CIRCUIT DIAGRAM
13
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THEORY:
The signal to be amplified is applied between the terminals base and emitter. The tank circuit is tuned (i.e L or C may
be varied) in such a way that the resonant frequency becomes equal to the frequency of the input signal. At resonance the tuned
circuit offers very high impedance and thus, the given input signal is amplified by the amplifier and appears with large value
across it and other frequencies will be rejected. So the tuned circuit selects the derived frequency and rejects all other frequencies.
PROCEDURE:
1.
Connections are made as per the circuit diagram.
2.
Set Vi = 50mV using the signal generator.
3.
Keeping the input voltage constant, ring the circuit for ac analysis.
4.
Calculate the bandwidth from the graph.
THEORITICAL CALCULATIONS:
L = 100mH, C = 0.1 μf
f = 1 / (2π√(LC)) = 1 / (2π * √(100*10 -3 * 0.1*10-6)) = 1.6 K Hz
PRACTICAL CALCULATIONS:
Td =
f = 1 / Td
PRECAUTIONS:
Transistor terminals must be identified properly
EXPERIMENT NO. 1
CLASS A AMPLIFIERS
OBJECTIVE
To study the operating points of Class-Apower amplifiers.
PREREQUISITES
Basic Knowledge of Class A Power Amplifier
DESCRIPTION
a. Introduction to experiment -30 min
b Connection of experiment and its verifications
c. Calculate the Efficiency and compare with the theoretical values.
EXPERIMENT NO. 2
TUNED RF AMPLIFIER
14
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CMR Engineering College
OBJECTIVE.
1. To calculate the Resonant Frequency.
2. To calculate the Inductive reactance.
3. To calculate the capacitive reactance.
PREREQUISITES
Theory of Tuned circuits , Working Principle of Tuned circuits and Knowledge on Transfer
Characteristics
DESCRIPTION
a. Introduction to experiment -30 min
b. Connection of experiment and its verifications
c. Experimental determination of Tuned circuits .
EXPERIMENT NO. 3
TWO STAGE RC COUPLED AMPLIFIER
OBJECTIVE
1. To study the Two- stage RC coupled Amplifier.
2. To measure the voltages gain of the amplifier at 1 kHz.
3. To obtain the frequency response characteristics and the bandwidth of the amplifier.
PREREQUISITES
Basic operation of RC coupled Amplifier, Theory of RC coupled Amplifier
DESCRIPTION
a. Introduction to experiment -30 min
b. Connection of experiment and its verifications
c. Experimental determination of RC coupled Amplifier for various Reference Voltages
EXPERIMENT NO. 4
RC PHASE SHIFT OSCILLATOR
OBJECTIVE
a) Design RC phaseshift oscillator to have resonant frequency of 6KHz.
Assume R1 = 100k, R2 = 22K, RC = 4 K ,RE =1K & VCC = 12V.
b)Obtain hfe for the above designed value for AV > - 29, R≥ 2 RC.
PREREQUISITES
Working Principle of RC phaseshift oscillator, knowledge on oscillators.
DESCRIPTION
a. Introduction to experiment -30 min
b. Connection of experiment and its verifications
c. Experimental determination of RC phaseshift oscillator Operation by applying DC input.
d. Observe the wave forms .
15
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EXPERIMENT NO. 5
HIGH FREQUENCY COMMON BASE AMPLIFIER
OBJECTIVE
Design a common Base high frequency amplifier with a over all gain of 30 and Lower cut off frequency of 130 Hz
and
Higher cut frequency 10 MHz .
PREREQUISITES
Working of common base amplifier .
DESCRIPTION
a. Introduction to experiment -30 min
b. Connection of experiment and its verifications
c. verification of common base amplifier
EXPERIMENT NO. 6
WEIN BRIDGE OSCILLATOR
OBJECTIVE
a) Design Wein Bridge oscillator to have resonant frequency of 6KHz.
Assume R1 = 100k, R2 = 22K, RC = 4 K ,RE =1K & VCC = 12V.
PREREQUISITES
Working Principle of Wein Bridge oscillator, knowledge on oscillators.
DESCRIPTION
a. Introduction to experiment -30 min
b. Connection of experiment and its verifications
c. Experimental determination of Wein Bridge oscillator Operation by applying DC input.
d. Observe the wave forms .
EXPERIMENT NO. 7
Collpit’s OSCILLATOR
OBJECTIVE
a) Design Collpitt’s oscillator to have resonant frequency of 6KHz.
PREREQUISITES
Working Principle of Collpitt’s oscillator, knowledge on oscillators.
DESCRIPTION
a. Introduction to experiment -30 min
b. Connection of experiment and its verifications
c. Experimental determination of Collpitt’s oscillator Operation by applying DC input.
d. Observe the wave forms .
16
II/IIB.Tech-ECE Academic Planner for AY 2013-14
Department of Electronics& Communication Engineering
1.2.6
CMR Engineering College
LAB SCHEDULE:
CYCLE 1:
Batches
09/12/13
16/12/13
23/12/13
30/12/13
06/01/14
20/01/14
27/01/14
B1
Demo
Exp.1
Exp.2
Exp.3
Exp.4
Exp.5
Exp.6
B2
Demo
Exp.1
Exp.2
Exp.3
Exp.4
Exp.5
Exp.6
10/02/14
17/02/14
24/02/14
03/03/14
10/03/14
17/03/14
CYCLE 2:
Batches
1.2.7
1.
2.
3.
4.
5.
6.
7.
8.
4.
5.
6.
7.
8.
9.
B1
Exp.7
Exp.8
Exp.9
Exp.10
Exp.11
Exp.12
Revision
B2
Exp.7
Exp.8
Exp.9
Exp.10
Exp.11
Exp.12
Revision
SUGGESTED BOOKS
Integrated Electronics – Jacob Millman and Christos C Halkies, 1991 Ed. 2008, TMH.
Electronic Devices and Circuits – S. Salivahanan, N. Suresh Kumar, A Vallavaraj, 2.Ed., 2009, TMH
Design of Analog CMOS Integrated Cicuits – Behzad Razavi, 2008, TMH.
Electronic Devices and Circuit Theory – Robet L. Boylestad, louis Nashelsky, 9.Ed., 2008 PE.
Introductory Electronic Devices and Circuits – Robert T. Paymer, 7.Ed., 2009, PEI.
Electronic Circuit Analysis – K. Lal Kishore, 2004, BSP.
Electronic Devices and Circuits, david A. Bell, 5.ed., Oxford University Press.
Microelectronics Circuits – Sedra and smith – 5.Ed., 2009, Oxford University.
1.2.8
1.
2.
3.
03/02/14
WEB SITES
http://www.ni.com/multisim/what-is/
http://www.mhhe.com/engcs/electrical/neamen01/
http://www.unix.eng.ua.edu/~huddl/mystuff/ECE333/ISM--Electronic%20Circuit%20Analysis%20and%20Design.pdf
http://www.stanford.edu/class/ee122/Handouts/EE113_Course_Notes_Rev0.pdf
http://www.ee.hacettepe.edu.tr/~solen/Matlab/MatLab/Matlab%20%20Electronics%20and%20Circuit%20Analysis%20using%20Matlab.pdf
http://www.zen22142.zen.co.uk/Theory/tr_model.htm
http://en.wikipedia.org/wiki/Negative_feedback_amplifier
http://www.learnabout-electronics.org/Amplifiers/amplifiers10.php
http://www.electronics-tutorials.ws/oscillator/rc_oscillator.html
1.2.9
EXPERTS’ DETAILS
INTERNATIONAL
1. Prof. Donald Neamen
Professor and Associate Chairman for the Department of Electrical and Computer Engineering
The University of New Mexico.
e-mail: [email protected]
2.
17
Prof. Anantha P. Chandrakasan
Professor of Electrical Engineering and Computer Science
Massachusetts Institute of Technology.
e-mail: [email protected]
II/IIB.Tech-ECE Academic Planner for AY 2013-14
Department of Electronics& Communication Engineering
CMR Engineering College
NATIONAL
1. Prof. Anindya Sundar Dhar
Professor Department of Electronics & Electrical Communication Engineering
IIT Kharagpur.
e-mail: [email protected]
2. Prof. Indrajit Chakrabarti
Professor Department of Electronics & Electrical Communication Engineering
IIT Kharagpur.
e-mail: [email protected]
REGIONAL
1. Dr. Krishna Prasad K S R
Professor Department of Electronics & Communication Engineering
NIT Warangal.
e-mail: [email protected]
18
II/IIB.Tech-ECE Academic Planner for AY 2013-14
Department of Electronics& Communication Engineering
1.
CMR Engineering College
LABORATORY DETAILS
1.1
PULSE AND DIGITAL CIRCUITS LAB
1.1
Objectives and Relevance
1.2
Scope
1.3
Prerequisites
1.4
Syllabus
1.5
Lab Schedule
1.6
Suggested Books
1.7
Websites
1.8
Experts’ Details
1.9
LEAD Experiment
1.1
OBJECTIVES AND RELEVANCE
The main objective of the lab course is to gain practical hands on experience by exposing the students
to understand the basic working principle of electronic devices To provide the student with an understanding
of the transistor level design of the most commonly used BJT and MOSFET logic families. Emphasis is placed
on design and analysis of the logic gate hardware rather than logic design via interconnection of standard gates.
Dynamic response of the logic gates and other specialized pulse and switching circuits is a key topic including
transmission line effects for high frequency circuits.
1.2
SCOPE
Understanding of Pulse and Digital Circuits Lab has the scope to make the learner comfortable to work in the area of
and also to implement various projects like monitoring and controlling applications. Industries involved in design and
fabrication of devices, integrated circuits, embedded systems, electronic equipments etc have also provide large scale
placements for engineers with this specializations. The study of pulse and digital circuits emphasizes the application of
basic scientific principles to the design of equipment, which includes electronic and electro-mechanical systems, for use
in measurements, communications, and digital electronics and VLSI circuits.
1.3
PREREQUISITES
The prerequisites for this lab are the each student expected to be familiar with the fundamentals of linear circuit
analysis and small signal models of electronic devices, like semiconductor diodes and transistors and knowledge
of different theorems, analyzing circuits, mesh analysis for getting output and input relations
1.4
SYLLABUS-JNTU
EXPERIMENT NO. 1
UNIT-I
Linear Wave Shaping (Low Pass Filter &High Pass Filter)
(JNTU SL.No.1)
OBJECTIVE
Design a RC Low pass Filter and High Pass Filter at various time constants and verify the responses for
wave input
Square
PREREQUISITES
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Basic Knowledge of High Pass Filter and Low pass Filter and derivations of rise time and tilt
DESCRIPTION
a. Introduction to experiment -30 min
b Connection of experiment and its verifications
c. Calculate the rise time for low pass filter and tilt for high pass filter and compare
with the theoretical values.
d. Graphical determination of LPF &HPF for time constants ( 1) RC == T(2) RC>>T (3) RC>>T
APPLICATIONS
1. High Pass Filter can be used as Differentiator
2. High Pass Filter can be used in Image Processing and Audio Frequency Applications
3. Low Pass Filter Can be used as Integrator
4. Used in analog to digital converters and digital filters etc
VIVA QUESTIONS:
1. When HP-RC circuit is used as Differentiator?
2. Draw the responses of HPF to step, pulse, ramp inputs?
3. Draw the responses of LPF to step, pulse, ramp inputs?
4. Define % tilt and rise time?
5. When LP-RC circuit is used as integrator?
6. Why noise immunity is more in integrator than differentiator?
7. What is the Applications of High Pass Filter?
8. What is meant by linear wave shaping?
9. Write the formula for rise time tr?
10. What is the Applications of Low Pass Filter?
EXPERIMENT NO. 2
UNIT –II
Non Linear Wave Shaping (Clippers)
(JNTU SL.No.2)
OBJECTIVE
To study the clipping circuits for different reference voltages and to verify the responses.
PREREQUISITES
Theory of Linear Wave Shaping, Working Principle of Series and Shunt Clippers and
Knowledge on Transfer Characteristics
DESCRIPTION
a. Introduction to experiment -30 min
b. Connection of experiment and its verifications
c. Experimental determination of Series and Shunt Clippers.
d. Graphical determination of clippers with Transfer characteristics
APPLICATIONS
1. Clippers can be used as Slicers.
2. Used as Amplitude Limiters.
3. Series Clippers are used in Noise Limiters in FM Transmitters.
4. Clippers are also used in TV Receivers.
VIVA QUESTIONS:
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1.
Define clipping circuit?
2.
What are the different types of clippers?
3.
What is a break region?
4.
Which kind of a clipper is called a slicer circuit?
5.
What are the disadvantages of the shunt clipper?
6.
What are the disadvantages of the series clipper?
7.
What is piecewise linear mode of a diode?
8.
What are the Applications of clippers?
CMR Engineering College
EXPERIMENT NO. 3
UNIT –II
Non Linear Wave Shaping (Clampers)
(JNTU SL.No.3)
OBJECTIVE
To study the clipping circuits for different reference voltages and to verify the responses.
PREREQUISITES
Basic operation of Clamper circuits, Theory of Nonlinear Wave Shaping
DESCRIPTION
a. Introduction to experiment -30 min
b. Connection of experiment and its verifications
c. Experimental determination of Clamping Circuit for various Reference Voltages
d. Graphical Determination of Clamping Circuits for various Reference Voltages
APPLICATIONS
1. Clampers can be used as DC Restorer or DC inserters.
2. TV Transmitters and Receivers.
3. Used in RADAR Systems
4. Computer Displays.
VIVA QUESTIONS
1. What are the applications of clamping circuits?
2. What is the synchronized clamping?
3. Why is a clamper called a dc inserter?
4. What is clamping circuit theorem. How does the modified clamping
Circuit theorem differs from this?
5. Differentiate –ve clamping circuit from +ve clamping circuits in the
above circuits?
6. Describe the charging and discharging of a capacitor is each circuit?
7. What is the function of capacitor?
8. What are the effects of diode characteristics on the output of the
Clamper?
EXPERIMENT NO. 4
UNIT –III
Transistor as a Switch
(JNTU SL.No.4)
OBJECTIVE
To design and observe the performance of a transistor as a switch.
PREREQUISITES
Working Principle of Transistor, knowledge on Transistor Switching Times
DESCRIPTION
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a. Introduction to experiment -30 min
b. Connection of experiment and its verifications
c. Experimental determination of Transistor Operation by applying Square wave input.
d. Observe the wave forms at collector and base of the transistor.
APPLICATIONS
1. Used in Switching Applications
2. Power Supply circuits.
VIVA QUESTIONS
1. Differentiate between Diode and Transistor as a switch?
2. Mention typical values of VBE Sat, VCE Sat for both Si, Ge Transistors?
3. Define ON time, OFF time of the transistor?
4. In which regions Transistor acts as a switch?
5. Explain phenomenon of “ latching “ in a Transistor switch?
6. Define Rise time & fall time of a transistor switch?
7. Define Storage time of a Transistor?
8. In which region Transistor acts as a Amplifier?
9. Explain the Applications of Transistor?
10. Define Transition time of a Transistor?
EXPERIMENT NO. 5
UNIT-VIII
Study of Logic Gates & Some Applications (JNTU SL.No.5)
OBJECTIVE
Study of Logic Gates Using IC’S and Discrete Components.
.
PREREQUISITES
Definitions of Logic Gates and Truth Tables
DESCRIPTION
a. Introduction to experiment -30 min
b. Connection of experiment and its verifications
c. verification of all gates truth tables by Using Discrete components and IC’S
APPLICATIONS
1. Logic Gates are used in Multiplexers and Registers
2. Flip Flops & Computer Memory Applications
3. Burglar alarams
4. Logic Gates are used to store data.
VIVA QUESTIONS
1. Why NAND & NOR gates are called universal gates?
2. Realize the EX – OR gates using minimum number of NAND gates?
3. Give the truth table for EX-NOR (EX-OR+NOT) and realize using NAND gates.
4. Explain the applications of Logic gates?
5. Explain the operation of NAND gate when realized using discrete components?
6. In what regions does the transistor is operated such that it behaves like a switch?
7. What are the logic low and High levels of TTL IC’s and CMOS IC’s?
8. Compare TTL logic family with CMOS family?
9. Which logic family is called fastest and which logic family is called low power
Dissipated?
10. Explain the operation of OR, NOR gates when realized using discrete
Components
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EXPERIMENT NO. 6
Study of Flip Flops & some Applications
(JNTU SL.No.6)
OBJECTIVE
To Construct different types of Flip – Flops and verify their truth tables.
PREREQUISITES
Basic Operation Of SR FlipFlop,JK FlipFlop,T FlipFlop & D FlipFlop with their Truth tables.
DESCRIPTION
a. Introduction to experiment -30 min
b. Connection of experiment and its verifications
c. Verification of all flipflops with truth tables.
APPLICATIONS
1. Used in Data Storage and Data Transfer applications
2. Counters and Registers
3. Parallel Data Storage applications
4. Frequency Division applications
VIVA QUESTIONS
1.Difference between latch and flip-flop?
2.List the applications of flip-flops?
3.Explain the operation of JK master slave flip-flop?
4.What is the difference between SR-flip flop and clocked SR-FF?
5.What is ment by level triggering and edge triggering in flip-flops?
6. Explain the difference between +ve edge and –ve edge triggering?
7. Which type of edge triggering is used in IC 7476 J-K M/S Flip-flop?
8. Explain the preset and clear inputs of a flip-flop and why are these
Called asynchronous inputs?
9. What is meant by toggle and where do the T-FF’s are used?
10. Where do the D-FF’s are used and why it is called a delay flip flop?
11.Explain the race around problem in JK-FF and how it is eliminated in master slave JK- FF?
UNIT-VII
EXPERIMENT NO. 7
Sampling Gates
(JNTU SL.No.7)
OBJECTIVE
To observe the output of the Unidirectional diode gate for different Control Input Voltages
PREREQUISITES
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Working Principle of Sampling gates and applications
DESCRIPTION
a. Introduction to experiment -30 min
b. Connection of experiment and its verifications
c. Experimental determination of Sampling gate for different control input voltages
d. Graphical determination of sampling gate for different control input voltages
APPLICATIONS
1.Used in Multiplexers and Sampling Scopes
2.Digital to Analog Converters
3.Sample and Hold Circuits
4.Chopper Stabilized Amplifiers
VIVA QUESTIONS
1. What is sampling gate?
2. Sketch the simple diode Unidirectional sampling gates that functions as a coincidence
gate
3. Write some applications of sampling gate?
4. Write short notes on four diode bi- directional diode sampling gate?
5.What is the disadavantage of Unidirectional Sampling gate?
6.What is the diffrence between Sampling gate and Logic gate?
EXPERIMENT NO. 8
UNIT –IV
Astable Multivibrator
(JNTU SL.No.8)
OBJECTIVE
To design an Astable Multivibrator to generate clock pulse for a given frequency and obtain the wave forms
and test its performance
PREREQUISITES
Operation of Astable Multivibrator and Applications
DESCRIPTION
a. Introduction to experiment -30 min
b. Connection of experiment and its verifications
c. Observe the waveforms at VBE1, VBE2, VCE1, VCE2 using CRO
d. Calculation of Frequency of astable multivibrator and compare with theoretical value.
APPLICATIONS
1. Free Running Oscillator.
2. Square Wave Generator
3. Astable Multi vibrator can be used as Relaxation Oscillator.
VIVA QUESTIONS
1. Explain charging and discharging of capacitors in an Astable Multivibrator?
2. How can an Astable multivibrator be used as VCO?
3. Why do you get overshoots in the Base waveforms?
4. What are the applications of Astable Multivibrator?
5. How can Astable multivibrator be used as a voltage to frequency converter?
6. What is the formula for frequency of oscillations?
7. What are the other names of Astable multivibrator?
EXPERIMENT NO. 9
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UNIT –IV
MonoStable Multivibrator
(JNTU SL.No.9)
OBJECTIVE
To design a Monostable multivibrator to generate clock pulse for a given frequency and obtain the
waveforms and test its performance
PREREQUISITES
Operation of Monostable Multivibrator and Applications, Derivation for gate width of
Monostable Multivibrator
DESCRIPTION
a. Introduction to experiment -30 min
b. Connection of experiment and its verifications
c. Observe the waveforms at VBE1, VBE2, VCE1, VCE2 using CRO
d. Compare the theoretical and practical gate widths
APPLICATIONS
1. Monostable Multivibrator finds extensive applications in Pulse Circuits.
2. Used as Gating Circuit or a Delay Circuit
VIVA QUESTIONS
1. What are applications of Monostable Multivibrator?
2. Why is a Monostable Multivibrator called a gating circuit?
3. Explain the waveform of VB1?
4. Describe the operation of the capacitor C3 in the circuit?
5. Why is the time period T also called Delay time?
6. Justify, Why Monostable Multivibrator is called one-shot circuit?
7. Why is the –ve voltage given at the base of Q1 transistor.
8. What is the no of quasi & stable states of Monostable Multivibrator
EXPERIMENT NO. 10
UNIT –IV
Bistable Multivibrator
OBJECTIVE
Design the Bistable Multivibrator circuit and verify the operation.
(JNTU SL.No.10)
PREREQUISITES
Working principle of Bistable Multivibrator
DESCRIPTION
a. Introduction to experiment -30 min
b. Connection of experiment and its verifications
c. Observe the waveforms at VBE1, VBE2, VCE1, VCE2 using CRO
d. Graphical determination of bistable multivibrator
APPLICATIONS
1. Used as Basic Memory Element
2. Used to Perform Many Digital Operations such as counting and Storing of Binary Data.
3. Generation and Processing of Pulse type wave forms.
VIVA QUESTIONS
1. What are the applications of a Bitable multivibrator?
2. Describe the operation of commutating capacitors?
3. Why is a Binary also called a flip-flop?
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4. Mention the name of different kinds of triggering used in the circuit shown?
5. What are the disadvantages of direct coupled Binary?
6. How many types of unsymmetrical triggering are there?
7. What are catching diodes?
8. Which triggering is used in binary counting circuits?
EXPERIMENT NO. 11
UNIT –IV
Schmitt Trigger
(JNTU SL.No.11)
OBJECTIVE
To design a Schmitt Trigger and Observe the Wave forms for a given UTP and LTP values and
test its performance
PREREQUISITES
Working principle of Schmitt Trigger and Derivations of UTP and LTP
DESCRIPTION
a. Introduction to experiment -30 min
b. Connection of experiment and its verifications
c. Experimental determination of UTP and LTP values and comparision with its theoritical values.
d. Observe the input and output waveforms on CRO
APPLICATIONS
1.Used as Squaring Circuit
2.Used in Amplitude Comparator Applications
3.Schmitt Trigger is also used as Bistable Multivibrator.
VIVA QUESTIONS
1.What are the applications of Schmitt Trigger?
2.Define hysteresis action?
3.Why is Schmitt Trigger called a squaring circuit?
4.What is UTP?
5. What is LTP?
6. What is the difference between a Binary and Schmitt Trigger ?
EXPERIMENT NO. 12
UNIT -V
UJT Relaxation Oscillator
(JNTU SL.No.12)
OBJECTIVE
To Obtain the Sawtooth Wave form Using UJT and test its perforamance as a Oscillator.
PREREQUISITES
Working principle and Characteristics of UJT
DESCRIPTION
a. Introduction to experiment – 30 min
b. Connection of experiment and its verification.
c. Observe the Output wave forms on the CRO at Base1, Base2 and volatge across the capacitor
d. Graphical determination of UJT Characteristics
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APPLICATIONS:
1. Most popular application is UJT Relaxation Oscillator.
2. Timing Circuits.
3. Saw tooth wave Generators.
4. Triggering of SCR.
VIVA QUESTIONS
1. What is a relaxation oscillator?
2. Specifications of UJT?
3. What is the importance of UJT?
4. When will be UJT is switched
5. Describe some important applications of a UJT?
6. Define the intrinsic stand off ratio and explain its importance?
EXPERIMENT NO. 13
UNIT -V
Bootstrap Sweep Generator
(JNTU SL.No.13)
OBJECTIVE
To design a bootstrap sweep circui and test its performance
PREREQUISITES
Working principle of Bootstrap Sweep Generator
DESCRIPTION
a. Introduction to experiment – 30 min
b. Connection of experiment and its verification.
c. Observe the input and output wave forms of CRO and plot the waveforms.
d. Calculate the sweep & retrace time from the CRO and Compare the values with the theoretical vaiues
APPLICATIONS
1. Used in Time base Generators
2. Sweep Circuits
3. TV and RADAR Dispalys
VIVA QUESTIONS
1. Explain the basic principle involved in Bootstrap Sweep generator?
2. Mention the type of feed back employed in Bootstrap Sweep generator?
3. Mention the characteristics of the amplifier used in Bootstrap sweep generator?
4. Describe some important applications of Bootstrap Sweep Generator?
5.What type of sweep does a Bootstrap Sweep Generator produce?
1.5
LAB SCHEDULE: (GROUP-I)
CYCLE 1:
Batches
B1
B2
B3
B4
B5
Demo
Demo
Demo
D emo
Demo
Exp.1
Exp.2
Exp.10
Exp.9
Exp.8
Exp.2
Exp.10
Exp.9
Exp.8
Exp.1
Exp.10
Exp.9
Exp.8
Exp.1
Exp.2
Exp.9
Exp.8
Exp.1
Exp.2
Exp.10
Exp.8
Exp.1
Exp.2
Exp.10
Exp.9
Revision
Revision
Revision
Revision
Revision
Demo
Exp.4
Exp.6
Exp.11
Exp.12
Exp.5
Revision
CYCLE 2:
Batches
B1
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B2
B3
B4
B5
Demo
Demo
Demo
Demo
CMR Engineering College
Exp.6
Exp.11
Exp.12
Exp.5
Exp.11
Exp.12
Exp.5
Exp.4
Exp.12
Exp.5
Exp.4
Exp.6
Exp.5
Exp.4
Exp.6
Exp.11
Exp.4
Exp.6
Exp.11
Exp.12
Revision
Revision
Revision
Revision
Demo
Demo
Demo
Demo
Demo
Exp.1
Exp.2
Exp.10
Exp.9
Exp.8
Exp.2
Exp.10
Exp.9
Exp.8
Exp.1
Exp.10
Exp.9
Exp.8
Exp.1
Exp.2
Exp.9
Exp.8
Exp.1
Exp.2
Exp.10
Exp.8
Exp.1
Exp.2
Exp.10
Exp.9
Revision
Revision
Revision
Revision
Revision
Demo
Demo
Demo
Demo
Demo
Exp.4
Exp.6
Exp.11
Exp.12
Exp.5
Exp.6
Exp.11
Exp.12
Exp.5
Exp.4
Exp.11
Exp.12
Exp.5
Exp.4
Exp.6
Exp.12
Exp.5
Exp.4
Exp.6
Exp.11
Exp.5
Exp.4
Exp.6
Exp.11
Exp.12
Revision
Revision
Revision
Revision
Revision
LAB SCHEDULE: (GROUP-II)
CYCLE 1:
Batches
B1
B2
B3
B4
B5
CYCLE 2:
Batches
B1
B2
B3
B4
B5
1.6 SUGGESTED BOOKS
TEXT BOOKS:
1. Principles Millman’s Pulse, Digital and Switching Waveforms – J.Millman, H.Taub and Mothiki
S. Prakash Rao, 2 ed., 2008, TMH.
2.Solid State Pulse circuits – David A. Bell, 4 ed., 2002 PHI.
REFERENCE BOOKS:
1. Pulse and Digital Circuits – A. Anand Kumar, 2005, PHI.
2. Fundamentals of Pulse and Digital Circuits – Ronald J Tocci, 3 ed., 2008
3. Pulse and Digital Circuits – Motheki S. Prakash Rao, 2006, TMH.
4. Wave Generation and Shapping- L .Strauss
1.7 WEB SITES
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
http://www.electronics-tutorials.ws/waveforms/monostable.html
http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/logfam.html
www.stanford.edu/class/ee122/Handouts/0%20Intro.pdf
http://openbookproject.net/electricCircuits/
http://www.elexp.com/links.htm
http://simple.wikipedia.org/wiki/Category:Electronic_components
nptel.iitm.ac.in/courses/Web course-contents/IIT.../main1.html
www.iisc.ernet.in
www.e-booksdictionary.com
http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=6576263
http://www.engineersgarage.com/electronic-circuits
1.8 EXPERTS’ DETAILS
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INTERNATIONAL:
1. J. Millman ph.d and C.C.Halkias ph.dAssociate Professor of Electrical Engineering,
Columbia University
2. Prof. Trevor J.Trarnton,
Director of Center for Solid State Electronics Research,
Arizona State University, Tempe, USA
Email:[email protected],
NATIONAL:
1.Dr. Balasubrmanyam S K – Professor,
Department of Electronics Engineering IIT(BHU), Varanasi.
Email:[email protected]
2.Dr.Banerjee Swapna,
Professor in electronics &EC engineering,
IIT Khragpur
Email: swapna [at] ece.iitkgp.ernet.in
REGIONAL
1. P. John Paul
Dean Academics in Gurunanak Engineering College,
Hyderabad
2. K.Lal Kishore
Professor of ECE and Director of Academic and Planning,
JNTU Hyderabad
1.9
3. Suryaprakash Mothiki
professor and head of the Deparment,
Vishakapatnam, AP
LEAD Experiment:
FM wireless transmitter circuit:
This the fm wireless transmitter circuit, the truth is one kind microphone that developed to be used without a cable from
the microphone to the amplifier. Makes flexible to use than a plain microphone much Because without cumbersome cables. And
also save a microphone cable as much Because microphone cable is high quality that has relatively high prices.
Circuit Diagram:
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Operation of the circuit:
When we speak, the microphone will receive the audio signal is mixed with range FM frequency to transmit the
broadcast spectrum. The audio input is just bring to the FM radio receiver tuned provide the radio only. The detailed procedures
are as follows.
In Figure this circuit has very little equipment, MIC is used in the circuit be special that called the condenser microphone,
inside the MIC has an one amplifier section Serves to amplify the voice that speaks to the strength increases and send to the
output. So this MIC must a current one to them. Please note the circuit is supplied to the resistor 27K positive in the leg
microphone, and it is way out of with the audio signal, through the coupling capacitor to pin B of Q1, Which Q1 also acts as both
the radio frequency generator and the audio mixer on the Radio frequency is generated. and at B pin of the Q1 have the resistor R2
– 27K with R3 – 4.7K are divider circuit, Divided a number of voltage to the bias for Q1. And the capacitor C2-0.01uF is
connected to ground for bypass the high frequency, At C pin of the Q1 is connected pass the coil to the positive voltage
For this coil, we use copper wire No. 19-20 AWG, wrapped around the air core diameter of 7 mm. You should be bind
seven around , similar to coil spring, Then, stretching out to Length of 15 mm. close this coil has a capacitor C4 value 5-20pF is
the capacitor to adjust from 5pf to 20pF we called that the timmer. It is connected to a frequency tuning
And pin C of Q1 is connected to the antenna. Which in this circuit, we use an antenna that is built with yourself. By using
number of wire 16-20 AWG, about 7 inches in length, and curled into a circle like a spring, about 6 mm in diameter, the length of
the wire coil to the the end, then take one end soldered to the antenna connection.
Note: Principle, this circuit sends far about 100 meters, Depending on the location. There is low or high of noise oscillator,
Equipment with high quality or not, the soldering is good or not, therefore, it is difficult to determine how far? But from my
experience, in the center of the floor to the fourth floor of the building, it has been, they think that’s enough for the circuit with
very little equipment, and low cost of this.
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LABORATORY DETAILS
ELECTRICAL & ELECTRONICS LAB
(1)
Objectives and Relevance
(2)
Scope
(3)
Prerequisites
(4)
Syllabus
(5)
Lab Schedule
(6)
Suggested Books
(7)
Websites
(8)
Experts’ Details
1.
OBJECTIVES AND RELEVANCE
This lab introduces the basic concepts of Electrical and Electronics, which forms the core of the advanced concepts in the area of
Electrical and Electronics. The emphasis is laid on the basic circuit designing to the solutions of complex circuits, also concepts
regarding working of electrical machines and measuring equipments is explored.
Different Diodes are explored to have the basic idea of different characteristics of diode. In this lab we get the idea of flow of
current and voltage in simple and complex circuits practically.
2. SCOPE
The scope of this lab is to provide a thorough knowledge of the flow of voltage and current in electrical networks and circuits.
Explore the application of diode and to find the different application of machines and network reduction techniques. It also
provides the insight of the working and applications of electrical machines and measuring instruments.
3.
PREREQUISITES
Before the start of the experiments one should have the knowledge of voltage, current, basic electrical components, relation
between V and I w.r.t electrical components, difference between ac and dc, different diode, transistors and rectifier characteristics.
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4. SYLLABUS – JNTUH
PART-A
S. No
Name of the Experiment
1
Verification of KCL and KVL
2
Verification of Superposition and Reciprocity theorems.
3
Verification of Maximum Power Transfer Theorem. Verification on DC with Resistive load.
4
Experimental Determination of Thevenin’s theorem.
5
Series and parallel resonance
6
Z and Y parameters
7
Transmission and Hybrid parameters
8
Swinburne’s Test on DC Shunt Machine (Predetermination of efficiency of a given DC shunt
machine working as motor and generator).
9
Brake test on DC Shunt Motor. Determination of performance Characteristics.
10
OC & SC tests on Singles-phase Transformer (Predetermination of efficiency and regulation at
given power factors).
11
Brake test on 3-phase Induction Motor (Performance characteristics).
12
Magnetization characteristics of D.C Shunt Generator.
5.
LAB SCHEDULE
S.No
32
Date of
Completion
Experiment
1
Verification of KCL and KVL
2
Verification of Superposition and Reciprocity theorems.
3
Verification of Maximum Power Transfer Theorem. Verification on DC
with Resistive load.
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4
Experimental Determination of Thevenin’s theorem.
5
Series and parallel resonance
6
Z and Y parameters
7
Transmission and Hybrid parameters
8
Swinburne’s Test on DC Shunt Machine (Predetermination of efficiency
of a given DC shunt machine working as motor and generator).
9
Brake test on DC Shunt Motor. Determination of performance
Characteristics.
10
OC & SC tests on Singles-phase Transformer (Predetermination of
efficiency and regulation at given power factors).
11
Brake test on 3-phase Induction Motor (Performance characteristics).
12
Magnetization characteristics of D.C Shunt Generator.
ADDITIONAL RESEARCH EXPERIMENTS
1
33
Regulation of alternator by Synchronous impedance method
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KCL and KVL:
OBJECTIVE:
This is the basic experiment to calculate the current flow and voltage across any elements.
KIRCHOFFS CURRENT LAW(KCL):
The total current flowing into any DC circuit node, also called a branch point, is always the same
as the total current flowing out of the node.
KIRCHOFFS VOLTAGE LAW (KVL):
Voltage law states "The algebraic sum of the voltages around a closed circuit path must be zero".
Aim: Study & verification of Kirchhoff’s Current Law.
Study & verification of Kirchhoff’s Voltage Law.
Apparatus Required:
Apparatus
specification
R.P.S
quantity
1
voltmeter
(0 – 20V)
1
Ammeter
(0 – 200mA)
1
Decade resistance box
Connecting wires
3
Few
SCOPE:
Kirchoffs voltage law and Kirchoffs current laws are used in electrical and electronics circuits to
find out the currents flowing in different branches and to find out the voltages across
the
elements.
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SUPERPOSITION THEOREM
AIM: To verify Superposition theorem
APPARATUS:
S.No
Components
Specification
Quantity
1.
Resistors
2.2k, 2.7k, 1kohms
Each 1 NO
2.
DC RPS
(0-30)V
1 NO
3.
Bread Board
-
1 NO
4.
Ammeter
(0-200)mA
1 NO
5.
Connecting Wires
-
Required
ACTUAL CIRCUIT DIAGRAM:
STATEMENT:
This theorem states that in any linear bilateral network containing N sources, the response in any element is
equal to the algebraic sum of the responses caused by individual sources acting alone while other sources are
deactivated.
THEORITICAL CALCULATIONS:
STEP-I: When V1 Source is acting alone:
The total resistance of the circuit RT=R1+ (R2//R3)
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The total current in the circuit IT= V1/RT
Current in R3 element due to V1 Source I1= IT*[R2/( R2+ R3)]
STEP-II: When V2 Source is acting alone:
The total resistance of the circuit RT=R2+ (R1//R3)
The total current in the circuit IT= V2/RT
Current in R3 element due to V2 Source I2= IT*[R1/ (R1+ R3)]
Using Superposition theorem the current in R3 element = I1+I2
Using mesh analysis calculate the current in R3 element.
PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. By varying the regulated power supply apply the voltage of 10V in arm CD and 15V in the arm AB.
3. Note down the corresponding ammeter readings
4. Calculate the theoretical values and compare with it practical values
5. Repeat the experiment for different voltages
PRECAUTION:
1. The input supply should be within the limits so that it does not damage the network components
2. Connections should be made perfectly and correct.
Voltage sources
Theoritical
Practical
When v1is acting
When v2is acting
When v1and v2 are acting
RESULT:
RECIPROCITY THEOREM
AIM: To Verify the Reciprocity theorem
APPARATUS:
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S.No
Components
Specification
Quantity
1.
Resistors
2.2k, 2.7k, 1kohms
Each 1 NO
2.
DC RPS
(0-30)V
1 NO
3.
Bread Board
-
1 NO
4.
Ammeter
(0-200)mA
1 NO
5.
Connecting Wires
-
Required
CIRCUIT DIAGRAM:
STATEMENT:
In any linear bilateral network, if a source of emf E in any branch produces a current I in any other branch ,then
the same emf E acting in the second branch would produce the same current I in the first branch.
THEORETICAL CALCULATIONS:
WHEN THE SOURCE IS CONNECTED ACROSS AB:The total resistance of the circuit RT= R1+ (R2//R3)
The total current in the circuit IT= V1/RT
Current in MN Branch due to V1 Source I1= IT*[R3/ (R2+ R3)]
WHEN THE SOURCE IS CONNECTED ACROSS MN:The total resistance of the circuit RT= R2+ (R1//R3)
The total current in the circuit IT= V1/RT
Current in AB Branch due to V1 Source I2= IT*[R3/ (R1+ R3)]
PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. By varying the regulated power supply apply the voltage of 15V in the arms AB
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3. Connect the ammeter in load terminals MN and measure the current.
4. Now apply the voltage of 15V in the arms MN.
5. Connect the ammeter across AB terminals & measure the current.
6. Calculate the theoretical values and compare with it practical values
Current
Voltages
Theoretical
Practical
Source connected across MN
Source connected across AB
RESULT:
MAXIMUM POWER TRANSFER THEOREM
AIM:
To verify the maximum power transfer theorem for D.C network considering the resistive load.
APPARATUS:
1. Resistor-1000ohms
2. DC regulated power supply
3. Bread board
4. Ammeter – (0-200) ma range
5. Volt meter – (0-20) v range
6. Resistance box
ACTUAL CIRCUIT DIAGRAM:
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STATEMENT:
The maximum power transfer theorem states that in a linear bilateral network the maximum power is
transferred to the load resistance RL is connected across an voltage source V and internal resistance RS is maximum
when the value of load resistance is equal to the internal resistance of the voltage source.
THEORY:
Basically the maximum power transfer theorem network consists of sources supplying voltage, current or
power to the load. for example a radio speaker system or a micro phone supplying the input signals to the voltage
pre amplifiers sometimes it is necessary to transfer more power to the load .our aim is to find the necessary
condition to transfer the maximum power to the load for many applications in considerations .
Current in the circuit is I= V / (Rs+ RL)
Power delivered to the load is PL=I2 * RL
PL = [V / (Rs+ RL ) ]2 * RL
To determine the value of RL for maximum power to be transferred to the load we have to set the first
derivative of the above equation with respect to RL is equal to zero i.e. dp/d RL = 0
i.e. RL = RS
So the maximum power will be transferred to the load when load resistance is equal to the source resistance
So maximum power Pmax = V2 / 4 RL
PROCEDURE:
1.Connect the circuit as per the circuit diagram
2. By varying the regulated power supply apply the voltage of 12v to the circuit
3. Varying the load resistance note down the corresponding ammeter and voltmeter readings
4. Find the power for each reading using the formula=I2RL
Precaution:
1. The input supply should be within the limits so that it does not damage the network components
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2. Connections should be made perfectly and correct .
TABULAR FORM:
S.No
Resistance
Power = I2 * RL
Current in
(mAmp)
GRAPH:
RESULT: Maximum power transfer theorem verified.
Theoretical value Pmax=
Practical value Pmax=
THEVENIN’S THEOREM
AIM: To find the Thevenin’s Voltage and Thevenin’s Resistance for the given network.
APPARATUS:
S.No
Components
Specification
Quantity
1.
Resistors
2.2k, 2.7k, 1kohms
Each 1 NO
2.
DC RPS
(0-30)V
1 NO
3.
Bread Board
-
1 NO
4.
Ammeter
(0-200)mA
1 NO
5.
Connecting Wires
-
Required
6.
Voltmeter
(0-20)V
1 NO
ACTUAL CIRCUIT DIAGRAM:
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STATEMENT:
This theorem states that any network having terminals A & B can be replaced by a single voltage source VTH in
series with a single resistance RTH, here the value of voltage source is equal to the open circuit voltage between the
given load terminals A & B, the value of RTH= resistance of the network measured between A & B with load removed
and sources replaced by their internal resistances.
THEORITICAL CALCULATIONS:
CALCULATION OF VTH : Open circuit the load terminals i.e., remove load RL .
Calculate VTH, here VTH=VAB .
Here A,B terminals are open circuited so VAB=Voltage across R3 element
Apply ohm’s law to R3 element
Voltage across R3 element=Current in R3 element * R3
Current in R3 element=V1/(R1+R3)
VTH=VAB=V1* R3/ (R1+R3).
CALCULATION OF RTH :
Open circuit the load terminals and short circuit the voltage source calculate RTH.
RTH= (R1//R3) +R2.
PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. By varying the regulated power supply apply the voltage of 15V to the network.
3. By connecting the voltmeter across the open circuited terminals measure the open
circuit voltage
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4. By connecting the multimeter across the open circuited terminals measure the
equivalent resistance across the open circuited terminals the Thevenin’s equivalent
resistance .
5. Calculate the theoretical values and compare with practical values.
Precaution:
1. The input supply should be within the limits so that it does not damage the network components
2. Connections should be made perfectly and correct.
Thevenin’s voltage
Thevenin’s resistance
Voltage
Theoretical
Practical
Theoretical
Practical
RESULT:
SERIES RESONANCE
AIM: TO obtain the resonance condition and calculations of resonant frequency, bandwidthand q-factor
APPARATUS:
1.signal generator-1
2.inductor -30mh
3.capacitor-.47µf
4.resistor-100 ohms
5.cro
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6.connecting wires
CIRCUIT DIAGRAM:-
THEORY:THE PARALLEL RESONANCE OCCURS when xc=xl the frequency at which resonance occurs is called
resonance frequency when xc=xl the two branch currents are equal in magnitude and 180degree out of phase with
each other therefore the two currents cancel each other out and the total current is zero the condition for the
resonance occurs when xc=xl
The resonance frequency of a parallel circuit is Fr=1/ (2Π√LC)
Band width of a parallel circuit is =1/ (2 ΠL)
Q-factor for a parallel circuits= Fr/BW
The frequency at which the resonance occurs is called the resonance frequency and it is dented by Fr
Bandwidth is defined as the differences between the upper cut off frequency and lower cut off frequency
Q-factor is defined as the ratio of resonate frequency to the band width
PROCEDURE: 1.connect the ckt as per the ckt diagram
2. Give the input signal to the ckt through the signal generator and set the desired input voltage value
3. Second probe at the output terminals of the ckt by varying the frequency note down the output voltages
4. Calculate the resonant frequency bandwidth and q-factor
5. Compare practical values with theoretical values
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THEORITICAL CALCULATIONS:
RESONANT FREQUENCY Fr=1/ (2Π√LC)
BAND WIDTH (BW) =1/ (2 ΠL)
Q-FACTOR=Fr/BW
Sl.no
Output
voltage
Gain=vo/vin
Gain(db)
Model Graph:
RESULT: THE RESONANCE CONDITION IS OBTAINED AND ALSO CALCULATE D THE Fr, BW, Q-FACTOR
SL.NO
44
PARAMETERS
THEORITICAL VALUES
PRATICAL VALUES
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Fr
BW
Q-FACTOR
PARALLEL RESONANCE
AIM: TO obtain the resonance condition and calculations of resonant frequency, bandwidthand q-factor
APPARATUS:
1. Signal generator-1
2. Inductor -30mh
3. capacitor-.47µf
4. resistor-100 ohms
5. Bread board
6. Connecting wires
CIRCUIT DIAGRAM:-
THEORY: the parallel resonance occurs
when Xc=Xl the frequency at which resonance occurs is called resonance
frequency when Xc=Xl the two branch currents are equal in magnitude and 180degree out of phase with each other
therefore the two currents cancel each other out and the total current is zero the condition for the resonance occurs
when Xc=Xl
The resonance frequency of a parallel circuit is Fr=1/ (2Π√LC)
Band width of a parallel circuit is =1/ (2 ΠRC)
Q-factor for a parallel circuits= Fr/BW
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The frequency at which the resonance occurs is called the resonance frequency and it is dented by Fr
Bandwidth is defined as the differences between the upper cut off frequency and lower cut off frequency
Q-factor is defined as the ratio of resonant frequency to the band width
PROCEDURE: 1.connect the ckt as per the ckt diagram
2. Give the input signal to the ckt through the signal generator and set the desired input voltage value
3. Second probe at the output terminals of the ckt by varying the frequency note down the output voltages
4. Calculate the resonant frequency bandwidth and q-factor
5. Compare practical values with theoretical values
THEORITICAL CALCULATIONS:
Resonant frequency Fr=1/ (2Π√LC)
Band width (BW) =1/ (2 ΠRC)
Q-factor=Fr/BW
S.no
Output voltage
Gain=vo/vin
Gain(db)
Model graph:
RESULT: the resonance condition is obtained and also calculated the resonant frequency, band width and q-factor
are calculated
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SL.NO
PARAMETERS
CMR Engineering College
THEORITICAL VALUES
PRATICAL VALUES
Fr
BW
Q-FACTOR
Z and Y parameters
AIM: To verify Z and Y network parameters
APPARATUS:-
S.NO
components
specifications
quantity
1
resistors
2.2,1,3.3kilo ohms
1no
2
D.c r.p.s
(0-30)V
1no
3
Bread board
----
1no
4
ammeter
(0-200)mA
1no
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5
voltmeter
(0-20)V
1no
6
Connecting wires
---
required
STA
TEM
ENT:- Aport is defined as any pair of terminals into which energy is supplied or from which is withdrawn are where
the network variables are measured.in case of transmission parameters the sending end parameters are expressed
in terms of receiving end parameters and incase of hybrid parameters the sending end voltage and reciveing end
current are expressed in terms of the sending end current and reciveing end voltage
CIRCUIT DIAGRAM:-
THEORITICAL CALCULATIONS:FOR Z-PARAMETERS
V1=Z11I1+Z12I2
V2=Z21I1+Z22I2
Z11= V1/ I1 when I2 =0
Z12 = V1 / I2 when I1=0
Z21 = V2/ I1 when I2=0
Z22 = V2/ I2 when I1=0
For Y-PARAMETERS
I1=Y11V1+Y12V2
I2=Y21V1+Y22V2
Y11= I1/ V1 when V2=0
Y12= I1/ V2 when V1 =0
Y21= I2/ V1 when V2=0
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Y22= I2/ V2 when V1=0
PROCEDURE:1. CONNECT CIRCUIT AS show in figure
2. open and short the input and out put ports depending up on the required parameters
3. take the reading of both voltmeter and ammeter
PRECUATIONS:1. CONNECTIONS SHOULD BE CORRECT AND PERFECT.
2. THE INPUT POWER SUPPLY SHOULD BE IN LIMITS SO THAT IT SHOULD NOT DAMAGE THE NETWORK
RESULT:The impedance and admittance parameters of network are verified
S.NO
THEORITICAL VALUES
PRATICAL VALUES
TRANSMISSION AND HYBRID NETWORK PARAMETERS
AIM: To verify transmission and hybrid network parameters
APPARATUS:-
S.NO
components
specifications
quantity
1
resistors
2.2,1,3.3kilo ohms
1no
2
D.c r.p.s
(0-30)V
1no
STA
TEM
ENT:
-
Aport
is
4
ammeter
(0-200)mA
1no
defin
ed as
5
voltmeter
(0-20)V
1no
any
pair
6
Connecting wires
--required
of
termi
nals into which energy is supplied or from which is withdrawn are where the network variables are measured.in case
3
49
Bread board
----
1no
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of transmission parameters the sending end parameters are expressed in terms of receiving end parameters and
incase of hybrid parameters the sending end voltage and reciveing end current are expressed in terms of the
sending end current and reciveing end voltage
CIRCUIT DIAGRAM:-
THEORITICAL CALCULATIONS:FOR TRANSMISSION NETWORK PARAMETERS
V1=AV2-BI2
I1=C V2 -DI2
A= V1/ V2 when I2 =0
B = V1 / I2 when V2=0
C = I1 / V2 when I2=0
D= I1 / I2 when V2=0
For HYBRID NETWORK PARAMETERS
V1=h11 I1 + h12V2
I2 = h21I1+h22 V2
PROCEDURE:4. CONNECT CIRCUIT AS show in figure
5. open and short the input and out put ports depending up on the required parameters
6. take the reading of both voltmeter and ammeter
PRECUATIONS:1. CONNECTIONS SHOULD BE CORRECT AND PERFECT.
2. THE INPUT POWER SUPPLY SHOULD BE IN LIMITS SO THAT IT SHOULD NOT DAMAGE THE NETWORK
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RESULT:The impedance and admittance parameters of network are verified
S.NO
THEORITICAL VALUES
PRATICAL VALUES
SWINBURNE’S TEST ON DC SHUNT MACHINE
AIM: To conduct Swinburn’s test on a D.C shunt machine and to predetermine the efficiency, when the machine is
running as (i) Motor and (ii) Generator.
NAME PLATE DETAILS:
1.
2.
3.
4.
5.
K.W / HP
Voltage
Current
Speed
Type of winding
:
:
:
:
:
APPARATUS REQUIRED:
S. No.
1.
2.
3.
4.
Name
Range
Type
Quantity
Voltmeter
Ammeter
Tachometer
Rheostat
THEORY:
In direct testing of dc machines, it is very difficult to measure accurately the mechanical power input to the
generators and mechanical power output for motors. So efficiency cannot be determined accurately. Also direct
loading consumes lot of power for testing the machine. Also for large generators large power absorbing load may
not be available at testing place. Hence it is advisable to adopt indirect methods for the determination of efficiency
of dc machines. Most widely used method is Swinburn’s test.
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This test is useful only for those machines for which flux is practically constant.
The major advantages of determining the efficiency of dc machines by performing Swinburn’s test are:ADVANTAGES:
1. The efficiency obtained by Swinburn’s test is comparatively higher than the actual one.
2. Efficiency can be forecasted at any load without actual applying that load. This saves lot of power.
3. Efficiency can be predicted for a machine both as a motor and as a generator.
DISADVANTAGES:
1. Only shunt and compound machines can be tested by this method.
2. Series machines cannot be tested by this method.
3. The effect of commutation and armature reaction are not considered or tested.
4. This test does not give any idea of the behaviour of the machine under loading conditions.
PROCEDURE:
1. Give connections as per the circuit diagram.
2. Initially the resistance in armature circuit is kept at its maximum resistance position and in field circuit in
minimum resistance position.
3. Give supply and cutoff the resistance in armature circuit gradually, and adjust the motor speed to its
rated value by adjusting the field regulator.
4. Take the readings of the voltmeter (Vo) and ammeter in armature (Ia0) and ammeter in field circuit ( I f o ).
5. Switch off the supply and wire up the circuit for measuring armature resistance. Switch on the supply
and by varying position of the potential divider impress different voltages across the armature and note
down the corresponding currents.
6. Calculate the armature resistance, efficiency of the machine as motor and as generator for various loads
and plot the graph: efficiency Vs output.
OBSERVATIONS:
Ish=
; V=
; Iao=
MODEL CALCULATIONS:
Data from test :
Constant loses :
52
Vo, Iao, Ifo , Ra
Wi= Vo (Iao +Ifo)- Iao 2 Ra
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AS MOTOR
AS GENERATOR
Let line current be IL amps
let load current be IL amps
Field current Ish = Ifo
Field current Ish = Ifo
Applied voltage V= Vo
Terminal voltage= Vo
Ia = IL- Ish
Ia = IL+ Ish
Total loses WL= Wi+ Ia2 Ra
output = VIL
WL= Wi+ Ia2 Ra
Output= input- WL= VIL- WL
Input= VIL + WL
Efficiency = output / input
Efficiency = output / input
RESULTS:
(MOTOR)
S.No.
IL (amp)
Ia= IL- Ish (amp)
WL (watts)
Input
Output
Efficiency
Input
Output
Efficiency
1
2
3
4
(GENERATOR)
S.No.
IL (amp)
Ia= IL+ Ish (amp)
WL (watts)
1
2
3
4
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GRAPHS:
1. Efficiency Vs. Output (As motor)
2. Efficiency Vs. Output (As generator)
MODEL GRAPH:
EFFICIENCY
GENERATOR
MOTOR
OUTPUT(W
ATTS)
OC & SC TEST, EQUIVALENT CIRCUIT OF
A SINGLE PHASE TRANSFORMER
AIM:
 To predetermine the efficiency, regulation at different operating conditions
 To determine the equivalent circuit parameters.
 To draw Equivalent circuit of the transformer
By conducting open circuit and short circuit tests on a single-phase transformer
APPARATUS:
S. No.
Name
1.
Voltmeter
2.
Ammeter
3.
Wattmeter
4.
Single-phase variac
Range
Type
Quantity
Name Plate Details:
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H.V. side
1.
2.
3.
4.
KVA
Voltage
Current
Frequency
CMR Engineering College
L.V. side
:
:
:
:
The rating of a transformer is expressed in Kilo Volt - Amperes (KVA) rather than in kilowatts (KW). This is due to
the fact that rated transformer output is limited by heating and hence by the losses in the transformer. Copper loss
of a transformer depends on current and iron loss on voltage. Hence total transformer loss depends on volt-ampere
and not on phase angle between voltage and current i.e. it is independent of load power factor.
THEORY:
Open circuit test or No-load test:
The purpose of this test is to determine no-load loss or core loss and no-load current I0 which is helpful in finding X0
and R0. One winding of the transformer which ever is convenient, but usually high voltage winding is left open and
the other is connected to its supply of normal voltage and frequency. A wattmeter W, voltmeter V and an ammeter
A are connected in the low voltage winding i.e. primary winding in the present case with normal voltage applied to
the primary. Normal flux will be set up in the core, hence normal iron losses will occur which are recorded by the
wattmeter. As the primary no-load current I0 (as measured by the ammeter) is small (usually 2 to 10% of rated load
current), Cu loss is negligibly small in primary and nil in secondary (it being open). Hence the wattmeter reading
represents practically the core loss under no-load condition (and which is the same for all loads).
Short circuit test or Impedance test:
This is an economical method for determining the following:
i)
Equivalent impedance (Z01 or Z02), leakage reactance (X01 or X02) and total resistance (R01 or R02) of the
transformer as referred to the winding in which the measuring instruments are placed.
ii) Cu loss at full load (and at any desired load). This loss is used in calculating the efficiency of the transformer.
iii) Knowing Z01 or Z02, the total voltage drop in the transformer as referred to primary or secondary can be
calculated and hence regulation of the transformer determined.
In this test, one winding, usually the low voltage winding is solidly short circuited by a thick conductor (or
through an ammeter). A low voltage (usually 5 to 10% of normal primary voltage) at correct frequency is applied to
the primary and is continuously increased till full-load currents are flowing both in primary and secondary.
Since in this test, the applied voltage is a small percentage of the normal voltage, the mutual flux
production is also a small percentage of the normal value. Hence core losses are very small with the result that the
wattmeter reading represents the full-load Cu loss or I2R loss for the whole transformer i.e., both primary Cu loss
and secondary Cu loss.
PROCEDURE:
Open Circuit Test:
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It is usually done on the L.V. side, keeping the H.V. side open.
i. Make the connections as shown in the circuit diagram.
ii. Apply the rated voltage to L.V. side keeping H.V. side open.
iii. Note down the current I0 and power W0 for rated voltage V0.
Short Circuit Test:
Short circuit test, is usually done on the H.V. side keeping the L.V. side short circuited.
i. Make connections as shown in the circuit diagram.
ii. Apply the required voltage (VSC) so that current drawn (ISC) is equal to the rated current.
iii. Note the corresponding power input (WSC).
OBSERVATIONS:
O.C. Test:
Voltage
Current
V0 (Volts)
I0 (amps)
Power
W0(Watts)
S.C. Test:
Voltage applied
VSC (Volts)
Power Input
Current Drawn
Isc (amps)
Wsc (Watts)
CALCULATIONS:
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From O.C. Test:
No Load Power factor = Cos 0 =
w0

V0 I 0
0 
Sin  0 
I w  I 0 Cos 0 
R 0  V0 / I w 
I  I 0 Sin0 
X 0  V0 / I  
From S.C. Test:
Total impedance referred to the H.V. side
Z 02 
V SC

I SC
Total resistance referred to the H.V. side
R02 
W SC
I 2 SC

2
2
X 02  Z 02
 R02
Therefore, total resistance and reactance reffered to L.V. side (Primary side)
R01 
R02
K
2
X 01 
X 02
K2
Where ‘k’ is transformation ratio
% Efficiency at any load and given p.f :
Let
the load p.f. is Cos and X = actual load / full load
then, output power at actual load = X * full load = (X) (KVA) (p.f.)
= _______ Watts
Iron losses Wi = WOC =
Copper losses Wcu = (X2) (WSC) =
Total losses (Wt) = Wi + Wcu
% Efficiency = (output power)/(output + losses) =
% Voltage regulation at full load of given p.f. :
% Regulation at full load = (I2R02 Cos  + I2 X02 Sin  /V2
57
II/IIB.Tech-ECE Academic Planner for AY 2013-14
Department of Electronics& Communication Engineering
CMR Engineering College
% Regulation at any load = (xI2R02 Cos  + xI2 X02 Sin  /V2
‘+’ for lagging power factor
‘-’ for leading power factor
Table - 1: Efficiency calculations:
Fraction of
load (x)
p.f = Cos
1.0
0.8
1/4
1/2
3/4
1
Table - 2: % regulation:
p.f. = Cos 
1.0
Fraction of load
(x)
Lead
0.8
Lag
Lead
.0.6
Lag
Lead
0.4
Lag
Lead
0.2
Lag
Lead
Lag
1/4
1/2
3/4
1
GRAPHS:
1. Efficiency Vs. Output (For different power factors)
2. Regulation Vs. Power Factors
58
II/IIB.Tech-ECE Academic Planner for AY 2013-14
Department of Electronics& Communication Engineering
CMR Engineering College
ADDITIONAL RESEARCH EXPERIMENTS
REGULATION OF 3- ALTERNATOR BY SYNCHRONOUS IMPEDANCE AND MMF
METHODS
AIM: To predetermine the regulation of an alternator by
a) Synchronous impedance method and
b) MMF method.
NAME PLATE DETAILS:
Motor
Generator
Voltage
Voltage
Current
Current
Output
Output
Speed
Speed
Frequency
phase
59
II/IIB.Tech-ECE Academic Planner for AY 2013-14
Department of Electronics& Communication Engineering
CMR Engineering College
APPARATUS:
Si.No.
Item
Type
Range
Quantity
1
Ammeter
(M.I)
0–5A
1 No
2
Ammeter
(M.C)
0–2A
1 No
3
Voltmeter
(M.I)
0 – 600 Volts
1 No
4
Rheostats
0 – 360 ohms /
1.7A
1 No
5
Rheostats
0 – 1000 ohms /
1.2A
1 No
CIRCUIT DIAGRAM:
TH
EO
RY:
PR
OC
ED
UR
E:
1.
Make the connections as per the circuit diagram.
2.
Start the alternator with the help of prime mover (DC Shunt motor) and adjust
speed to the synchronous speed. The speed of the alternator is to be kept
constant throughout the experiment.
3.
60
Excite the field winding alternator keeping armature open.
II/IIB.Tech-ECE Academic Planner for AY 2013-14
Department of Electronics& Communication Engineering
CMR Engineering College
4.
Note down the terminal voltage at different values of field currents.
5.
Draw the graph of armature voltage versus field current to get the open circuit
characteristic (O.C.C) of the Alternator.
6.
Close the TPST switch.
7.
Excite the field winding of the alternator till the rated current flows through the
armature.
8.
Note down all meter readings.
9.
Draw the graph of the short circuit current versus field current to get the short
circuit characteristic (SCC).
10. Obtain the synchronous impedance corresponding to the rated voltage.
Zs 
Voc
, If const
I sc
11. Measure the armature resistance per phase by drop method. The a.c.
resistance will be 20% more than the D.C. Resistance: Ra = 1.2 Rdc
12. Calculate the synchronous reactance, Xs = Z2s – R2 ac
13. Calculate the generated e.m.f. With full load at a power factor
Cos¢ E =[(V Cos¢ + I R
a )2
( V Sin ¢ + I Xs )2]1/2
(+) sign for lagging p.f. and (-) sign for leading power factors.
14. Calculate full load regulation at different power factors.
15. Draw the graph of regulation versus p.f.
61
II/IIB.Tech-ECE Academic Planner for AY 2013-14
Department of Electronics& Communication Engineering
CMR Engineering College
CALCULATIONS:
TABULAR COLUMN:
S.NO.
If
Eg
If
ISC
1.
2.
3.
4.
5.
6.
7.
8.
RESULT:
APPLICATIONS
1. Design of lighting arcs
2. Design of battery charges
6.SUGGESTED BOOKS
62
1.
Electro Mechanics-I(D.C.Machines), S. Kamakshaiah, Right Publishers.
2.
Electrical Machines, P.S Bhimbra, Khanna publications.
3.
Performance and Design of DC machines, Clayton and Hancock, BPB publishers
4.
Electrical machinery, AE .Fritzerland, C.Kingsley, S.Umas , MGH publishers
5.
Electrical Machines, S.K Bhattacharya, TMH publishers
II/IIB.Tech-ECE Academic Planner for AY 2013-14
Department of Electronics& Communication Engineering
6.
CMR Engineering College
BASIC ELECTRICAL ENGINEERING – BY M.S NAIDU AND S.KAMAKSHAIAH TMH.
7.
ELECTRONIC DEVICES
AND
C IRCUITS – R.L. BOYLESTAD
AND
LOUIS NASHELSKY , 9
ED.,
2006,
PEI/PHI.
6. WEBSITES
1.
www.mit.edu (Massachusetts institute of technology)
2.
www.soe.stanford.edu (Stanford University)
3.
www.grad.gatech.edu (Georgia institute of technology)
4.
www.gsas.harward.edu (Harward University)
5.
www.eng.ufl.edu (university of Florida)
6.
www.ieee.org
7.
www.school-for-champions.com / science
8.
www.onesmartclick.com/engineering/electrical - machines.htmlwww.ece.rice.edu
7. EXPERT DETAILS
The Expert Details which have been mentioned below are only a few of the eminent
ones known Internationally, Nationally and Locally. There are a few others known as
well.
INTERNATIONAL
1.
Dr. Steven W. Blume Professor of Electrical Engineering, Dept. of Electrical Engg. University of
California, New Jersey.USA.
NATIONAL
1.
Prof P S Sastry, Dept of Electrical Engineering, IISc Bangalore.
2.
Dr. D.Ganesh Rao - Prof. & Head, Deptt. of Telecommunication Engg., M.S. Ramayya Instt. of
Tech., Bangalore
REGIONAL
63
1.
Prof. Shyam Mohan S Palli, HoD of Dept, EEE, SIR CRR College Of Engineering .
2.
Mr.M.Raghupathi, Dept. of ECE, Gitam University, Hyderabad
II/IIB.Tech-ECE Academic Planner for AY 2013-14
Department of Electronics& Communication Engineering
CMR Engineering College
Good Quotations
“By three methods we may learn wisdom: First, by reflection, which is noblest; second, by imitation, which is easiest and third by
experience, which is the bitterest.” – Confucius
Self confidence is the most attractive quality a person can have. how can anyone see how awesome you are if you can’t see it
yourself?” – Confucius
“Do not dwell in the past, do not dream of the future, concentrate the mind on the present moment.” – Confucius
“With realization of one’s own potential and self-confidence in one’s ability, one can build a better world.” – Confucius
Mastering others is strength. Mastering yourself is true power. –Lao Tzu
Knowing others is intelligence; knowing yourself is true wisdom. Mastering others is strength; mastering yourself is true power. If
you realize that you have enough, you are truly rich.” ― Lao Tzu, Tao Te Ching
When you are content to be simply yourself and don't compare or compete, everyone will respect you.” ― Lao Tzu, Tao Te
Ching
Watch your thoughts; they become words. Watch your words; they become actions. Watch your actions; they become habit.
Watch your habits; they become character. Watch your character; it becomes your destiny.” ― Lao Tzu
To attain knowledge, add things every day. To attain wisdom, remove things every day.” ― Lao Tzu
“Knowledge is a treasure, but practice is the key to it.” ― Lao Tzu
If you try to change it, you will ruin it. Try to hold it, and you will lose it.” ― Lao Tzu
Hope and fear are both phantoms that arise from thinking of the self. When we don't see the self as self, what do we have to fear?”
― Lao Tzu
“Knowing others is wisdom;
Knowing the self is enlightenment.
Mastering others requires force;
Mastering the self requires strength;
He who knows he has enough is rich.
Perseverance is a sign of will power.”
― Lao Tzu, Tao Te Ching
64
II/IIB.Tech-ECE Academic Planner for AY 2013-14