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Arieh Nachum
Logic Families
EB-3155
Arieh Nachum
Logic Families
EB-3155
1_9
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from DEGEM Systems.
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I
Contents
Preface ............................................................................................................. II
Experiment 1 – Gate Characteristics ............................................................ 1
1.1
1.2
1.3
1.4
Solid state devices – the major technologies ........................................ 2
The TTL family ..................................................................................... 3
CMOS technology............................................................................... 10
Input and output stages ....................................................................... 14
1.4.1
1.4.2
1.4.3
1.4.4
Input stages ......................................................................................... 14
Output stages ....................................................................................... 15
Characteristics ..................................................................................... 19
Schmitt trigger..................................................................................... 21
1.5
1.6
Gates materialized by discrete components ........................................ 23
Technical specifications & data sheets reading .................................. 25
Experiment 2 – Troubleshooting ................................................................. 39
EB-3155 – Logic Families
II
Preface
The experiments in this manual are meant to be run on the experiment board
EB-3515 with the Universal Training System EB-3100.
The EB-3100 includes:
 5 voltages power supply (+12V, +5V, –5V, –12V and –12V to +12V
variable voltage).
 2 voltmeters.
 Ampere-meter.
 Frequency counters up to 1MHz.
 Logic probe (High, Low, Open, Pulse, Memory).
 Logic analyzer with 8 digital inputs and trigger input.
 Two channel oscilloscope (with spectrum analysis while connecting to the
PC).
 Function generator (sine, triangle and square wave signals) up to 1MHz.
 3.2" color graphic display with touch panel for signal and measurement
display.
 USB wire communication with the PC.
 20 key terminal keyboard.
 10 relays for switching the plug-in boards or for planting faults.
 48 pin industrial very low resistance connector for plug-in boards
connection.
 Transparent sturdy cover covers the upper part of the plug-in boards in
order to protect the board's components that should be protected.
EB-3155 – Logic Families
III
The EB-3100 boards are:
Electricity and Electronics
EB-3121
Ohm and Kirchoff Laws and DC circuits
EB-3122
Norton, thevenin and superposition
EB-3123
AC circuits, signals and filters
EB-3124
Magnetism, electromagnetism, induction and transformers
Semiconductor Devices
EB-3125
Diodes, Zener, bipolar and FET transistors characteristics and DC circuits
EB-3126
Bipolar and FET transistor amplifiers
EB-3127
Industrial semiconductors – SCR, Triac, Diac and PUT
EB-3128
Optoelectronic semiconductors – LED, phototransistor, LDR, 7-SEG.
Linear Electronics
EB-3131
Inverter, non-inverter, summing, difference operational amplifiers
EB-3132
Comparators, integrator, differentiator, filter operational amplifiers
EB-3135
Power amplifiers
EB-3136
Power supplies and regulators
EB-3137
Oscillators, filters and tuned amplifiers
Motors, Generators and Inverters
EB-3141
Analog, PWM DC motor speed control, step motor control, generators
EB-3142
Motor control – optical, Hall effect, motor closed control
EB-3143
AC-DC and DC-AC conversion circuits
EB-3144
3 Phase motor control
Digital Logic and Programmable Device
EB-3151
AND, OR, NOT, NAND, NOR, XOR logic components & Boolean algebra
EB-3152
Decoders, multiplexers and adders
EB-3153
Flip-flops, registers, and counters sequential logic circuits
EB-3154
555, ADC, DAC circuits
EB-3155
Logic families
Microprocessor/Microcontroller Technology
EB-3191
Introduction to microprocessors and microcontrollers
EB-3155 – Logic Families
IV
The EB-3154 is connected to the EB-3100 via a 48 pin industrial connector.
It has a built-in microcontroller that identifies (for the EB-3100 system) the
experiment board when it is being plugged into the system, and starts a selfdiagnostic automatically.
The following figure describes the EB-3154 experiment board.
B2
B1
B5
TTL
B7
SCHMITT TRIGER
0
1
S0
L0
B3
CMOS
B6
0
1
S1
TRI -STATE
L1
B4
0
1
S2
OPEN COLECTOR
VCC
L2
R1
1K
0
1
S3
L3
EB-3154 Panel Layout
EB-3155 – Logic Families
V
The experiment method:
The system uses an external switching power supply for safety reasons. The
power supply low voltage output is converted to the 5 voltages by linear
regulators for noise reduction.
Two potentiometers on the panel are used to setup the variable voltage and the
function generator amplitude.
The system cut-off the voltages in overload and displays a massage about that.
The plug-in cards are connected directly to system without any flat cable for
noise and resistance reduction.
The 10 relays are change over relays that can switch active and passive
components.
Every selecting of a relay configuration is saved in a non-volatile memory
located on the connected plug-in card.
The components are located on the board with silk screen print of the
analytical circuit and component symbols. The central part of the
experimenting board includes all the circuit block drawings and all the hands
on components, test points and banana sockets.
The protected components are located on the circuit board upper side, clearly
visible to the student and protected by a sturdy transparent cover.
On plugging the experiment board, it sends a message to the EB-3100 which
includes the board's number and which of its block are faulty. If there is a
faulty module (B1-B8), it will be displayed on the screen.
The experiment board checks itself while it is being plugged. This is why,
during the plug-in, any banana wire should not be connected on the
experiment board.
5 LEDs should turn ON on the top right.
EB-3155 – Logic Families
VI
The system includes 5 power supply outputs. The system checks these
voltages and turns ON the LEDs accordingly.
+12V
+5V
–5V
–12V
–
–
–
–
Red LED
Orange LED
Yellow LED
Green LED
The fifth voltage is a variable voltage (Vvar) controlled by a slider
potentiometer.
The LED of the Vvar is both green and red: when the Vvar voltage is positive
– the color is red and when it is negative – the color is green.
There are no outlets for the power supply voltages on the
The voltages are supplied only to the 48 pin connector.
TSP-3100 panel.
The experiment boards take these voltages from the 48 pin connector.
EB-3100 Screens
The system has 3 operating screens: DVM, Oscilloscope and Faults.
Moving from one screen to another is done by the Options/Graph key.
The keyboard is always at Num Lock position.
The keys can also be used as function keys. In order to do so, we have to press
once on the Num Lock key and then on the required key. The keyboard
returns automatically to Num Lock mode.
On scope screen, pressing the Num Lock key and then the Digital key will
change the screen to Digital signal screen display.
Pressing the Num Lock key and then the Analog key will change the screen to
Analog signal screen display.
EB-3155 – Logic Families
VII
DVM Screen
DVM
V1 [V]
0.00
V2–V1 [V]
0.00
Fout [KHz]
5.00
V2 [V]
0.00
I [mA]
0.0
Cin [Hz]
5.00
I (+5V) [mA]
I (+12V) [mA]
0
0
I (–5V) [mA]
I (–12V) [mA]
0
0
Num Lock
V1 is the voltage measured between V1 inlet and GND.
V2 is the voltage measured between V2 inlet and GND.
V2–V1 is the voltage measured between V1 and V2. It enables us to measure
floating voltage.
I is the current measured between A+ and A– inlets.
Cin displays the frequency is measured in the Cin inlet.
The EB-3100 includes a function generator.
The frequency of the function generator is displayed in the Fout field and can
be set by the arrow keys or by typing the required values.
The square wave outlet is marked with the sign
.
Near the analog signal outlet there is a sine/triangle switch marked with the
signs
/
.
EB-3155 – Logic Families
VIII
Scope Screen
CH1 3.0VCH2
3.0V t 50s
CH1
1.0V
Num Lock Analog Run
The scope and the display parameters (CH1 Volt/div, CH2 Volt/div, time base
Sec/div, Trigger Channel, Trigger rise/fall, Trigger Level) appear on the
bottom of the screen.
The Up and Down arrow keys highlight one of the fields below.
The required field can be selected by touching it and can be changed by the
Up and Down arrows.
The function generator amplitude is changed by the amplitude potentiometer.
The sampling and display can be stopped by pressing the Num Lock key and
then pressing the Stop (8) key.
Performing a single sampling is done by pressing the Num Lock key and then
pressing the Single (9) key.
Running again the sampling is done by pressing the Num Lock key and then
pressing the Run (7) key.
EB-3155 – Logic Families
IX
Digital Screen
Pressing the Num Lock key and then the Digital key on scope screen displays
the Digital screen.
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
t 50s
TRIG
Num Lock Digital Run
Check that.
The logic analyzer includes 8 digital inlets and one trigger signal inlet.
The controller waits for trigger and when it encounters a trigger pulse it
samples the 8 digital inputs.
If a trigger pulse is not found the sampling will be according to the time base.
The sampling and display can be stopped by pressing the Num Lock key and
then pressing the Stop (8) key.
Performing a single sampling is done by pressing the Num Lock key and then
pressing the Single (9) key.
Running again the sampling is done by pressing the Num Lock key and then
pressing the Run (7) key.
EB-3155 – Logic Families
X
Logic Probe
The EB-3100 Logic Probe includes 5 LEDs indicating the Logic Probe (LP)
input state – High, Low, Open (unconnected), Pulses and Memory (registering
single pulse).
The Logic Probe also has a TTL/CMOS switch that determines which logic
level is selected.
When the LP is connected to a point with a voltage blow 0.8V (for TTL) or
1.3V (for CMOS), the L green LED should turn ON.
When the LP is connected to a point with a voltage above 2.0V (for TTL) or
3.7V (for CMOS), the H red LED should turn ON.
The voltage between these levels turns ON the OP orange LED.
Fault Screen
The EB-3100 includes 10 relays for fault insertion or for switching external
components.
The fault screen is selected by the Options/Graph key.
FAULTS
Please choose
Fault No.: 0–9
Activated fault
Number: 0
Num Lock
Typing a fault number and pressing ENTER operates the required relay for the
required fault.
Fault No. 0 means No Fault.
Which relay creates the required fault is registered in the plug-in experiment
board controller.
EB-3155 – Logic Families
XI
On entering a fault number, the system addresses the experiment board
controller and asks for the relay number. After that, it executes the required
fault.
The experiment board controller saves the last registered fault number in its
memory. This memory is non-volatile.
This is why the system does not allow us to enter a fault number when no
experiment board is plugged.
When an experiment board that a certain fault (other than zero) is registered in
its memory is plugged into the system, a warning message appears on the
system's screen.
This feature enables the teacher to supply the students various experiment
boards with planted faults for troubleshooting.
Note:
It is recommended (unless it is otherwise required), to return the
experiment board fault number to zero before unplugging it.
EB-3155 – Logic Families
XII
EB-3155 – Logic Families
1
Experiment 1 – Gate Characteristics
Objectives:
After completing this experiment explain:




The gate transfer characteristics.
The Schmitt Trigger gate behavior.
The open collector application.
The tri-state method.
Equipment required:
 EB-3100
 EB-3154
 Banana wires
Discussion:
Up to this chapter, we have related to the electronic logic components from
the point of view of the functions that they have to perform. We did not
consider neither their structure nor their electronic features, but rather treated
them as a black box with inputs and outputs. We were merely interested in the
relations between the outputs and the inputs.
In this chapter, we shall become familiar with the technology of the solid state
electronic logic devices – their structure, parameters, characteristics,
packaging and so on. We shall mention the bipolar transistor (NPN and PNP)
and the Field Effect Transistor (FET). We shall assume that the reader is
familiar with these components.
EB-3155 – Logic Families
2
In paragraph 1.7 we present a tutorial, explaining how to conduct an
experiment and how to write the very important "Lab Report", summarizing
the work performed and the results obtained. Selected data sheets of logic
components are duplicated for your convenience and presented in the
appendix.
1.1
Solid state devices – the major technologies
The logic components are divided into logic families. One approach is to
perform the classification in accordance with the technology of
manufacturing.
It is possible to encounter a rather large number of devices which are
performing the same functions, and we may even find them identical when we
study their packaging or pin layouts, but a closer look reveals that they differ
in the technology used for manufacturing them. The manufacturing
technology has significant influence on the performance capabilities and
features of the devices, hence on their operation characteristics. Parameters
such as response speed, power – both output and consumption, functional
characteristics, supply voltages, prices and many more, are all dependent on
and influenced by the manufacturing technology.
A rough classification distinguishes between two major logic families. TTL
logic devices based on bipolar transistors (mostly NPN) and MOSFET (Metal
Oxide Semiconductor FET's) logic devices. Each such family is further
subdivided into secondary families, as shall be presented in detail later on.
Other less popular families, for example ECL (Emitter Collector Logic)
devices are also found, but we shall not treat them as they are seldom used.
In addition to the classification by families and subfamilies, we also classify
the devices into "military" and non-military (commercial) devices. The
requirements for a "military device" (also known as MIL-STD) are much more
severe than the parallel ones for the commercial devices. Here we refer to the
environmental conditions requirements, namely withstanding temperature
extremes and variations (including temperature cycling), current and voltage
limits, etc. This is of course strongly expressed in the relative prices of these
devices.
EB-3155 – Logic Families
3
The military devices are much more expensive than the commercial ones (but
of course they are also much more reliable). The military devices undergo a
much larger range of quality and reliability tests than their commercial
counterparts.
These military specifications devices are used not only in military equipment
and applications. They are used whenever high reliability is at a premium,
e.g., in medical equipment, airborne equipment or equipment located at "hard
to get to' sites, where it will be very inconvenient to go to when repairs (and
regular maintenance) are to be performed.
1.2
The TTL family
As mentioned earlier, the TTL family is based on the bipolar transistor. The
structure of the TTL NAND gate is presented in figure 1-1.
VCC
RC
RB
Q
B1
A
B
TR1
TR2
Figure 1-1 A TTL NAND gate
A NOT gate is a 1-input NAND gate. All other devices are materialized by a
combinations of NAND gates. We have already seen in chapter 2 that this can
be achieved.
EB-3155 – Logic Families
4
Transistor TR1 in the figure is a transistor with several emitters. The number
of emitters is the same as the number of inputs of the gate. The transistor
actually operates as two back to back diodes.
VCC
RC
RB
A
Q
B1
B
Figure 1-2 DDTL logic
When one of the inputs is at '0', it may be looked upon as short circuited to
ground. The diode connected to it is conducting and the voltage at point B 1 is
approximately 0.7V. This voltage is too low and it cannot drive diode D3 (turn
it to become conducting) nor to activate TR2. We need a voltage of
approximately 1.4V to render TR2 conducting (i.e., the voltage of D1 and
VBE2) and hence TR2 is at cutoff. When TR2 is at cutoff, the voltage at point
Q is nearly VCC, namely '1'.
When both inputs are at '1', current does not flow through the diodes (D 1 and
D3). Hence, current shall flow in the VCC, Rb, D3, VBE2 loop. Transistor TR2
enters saturation (Rb is pre calculated accordingly) and the voltage at Q tends
to 0V, i.e., '0'. Moreover, when the pin is "open" (i.e., not connected) there
shall be no current's flow, hence an unconnected pin (an open circuit pin) of a
TTL gate behaves like a '1'.
In the "recent" past, people really used the DDTL (Diode Diode Transistor
Logic), as described in figure 1-2. The reason for replacing the two diodes by
a transistor is related to the higher speed that we achieve in changing the state
of the gate.
EB-3155 – Logic Families
5
When the TR2 transistor is in its saturation state, a surplus of charge (an
overcharges) is accumulated in the base of the transistor. These overcharges
have only one way for discharging by a leakage current through D3. Hence,
the switching times are low high. When the diodes are replaced by TR1, this
transistor functions as the switching transistor of TR2 from saturation to cutoff
and discharges the excess charges, which were stored in the base. This is one
of the reasons for the high switching speeds of the TTL gates.
The resistance of Rb is relatively low (several hundreds Ohms). This value is
selected in order to enable transistor TR2 to achieve saturation. For this
reason, when '0' exists at the input, a relatively high current flows into the
component activating this input.
Example:
'0' I
Figure 1-3 '0' induced current I
The resistance of Rc is also not so large (approximately 300). This resistor is
intended to enable driving reasonable amounts of current through the output of
the device when TR2 is at cutoff. Note that when TR2 is at cutoff, the output
voltage is given by:
Vo  VC C  I L  R C
Where IL is the load current (see figure 1-4).
VCC
RC
RB
TR1
IL
Vo
T
R
2
Figure 1-4 IL (Load Current)
EB-3155 – Logic Families
6
If the resistance of Rc will be too high, the output voltage would drop
significantly even for low output currents. It may drop to below the level
defined as '1', even though from the functioning point of view, it should have
been at '1'. Hence we are interested in a low resistance at the output.
On the other hand, when '0' exists at the output, an unwanted current to ground
flows through this resistor and TR2. This is simply a waste of energy (power)
at the gate. From this point of view, we would have preferred a larger output
resistance. Obviously, the value of the resistor actually selected is a matter of
compromise between the two opposite requirements. The output stages of
logic gates are discussed in more detail in one of the following sections
(paragraph 1.4.2).
The major drawback of gates employing TTL technology is its high current
consumption, and its leading advantage is its high speed: the duration of state
switchover at the output relative to the changes occurring at the inputs is short.
See for example the timing diagram of an inverting gate ( A
Y ) whose
logic performance is given by figure 1-5.
Y
A
t
Figure 1-5 Inverting gate – timing diagram
Y is the complement of A. The state switchover is executed simultaneously
for the two of them. Actually, this picture is over idealized. The true state of
affairs is depicted by figure 1-6.
Y
A
t
Figure 1-6 Inverting gate timing diagram, realistic presentation
EB-3155 – Logic Families
7
A does not perform an infinitely fast switchover (in zero time – such a
phenomena does not exist in nature). Nor does Y start to switchover on the
onset of the change of A, as there is a short lag – it starts a little later, and it
need some time to accomplish the change over. This additional time is called
"transition time".
In slow systems, this transition times are not significant. Its order of
magnitude is in tens or hundreds nanoseconds (nanosecond = ns = 10 -9sec).
On the other hand, in fast systems which include a large number of cascaded
gates where the response times of the components play a significant part (e.g.,
microcomputer systems), the transition times constitute an important factor to
be reckoned when selecting the suitable device.
TTL device numbers are written in the form 74xxx or 54xxx. 74 denotes a
device with non military (commercial) characteristics and 54 denotes military
specifications device characteristics. The digits xxx following the first two
digits denotes the serial number of the device in the family. Actually, this
number denotes the function performed by the device. For example, the device
numbered 7400 is a device comprising four NAND gates each with two
inputs, in its non military characteristics. The device numbered 5400 is a
similar device, but with military characteristics.
All the companies manufacturing logic components use the same ordinal
designations. This allows the use of devices manufactured by these
companies, even though the circuits were not originally designed for
employing them. For example, a manufacturer who have used a 7400
component manufactured by Motorola, may replace them by 7400's of Texas
Instruments production at a later stage, and so on.
With advancing time, the TTL technology has been improved and several subfamilies, designed primarily to increase the speed of the devices and
simultaneously to decrease their current consumption have been developed. It
has to be remembered that a single device consumes only a low current (a few
milliamperes), but that in a digital system, which may contain tens of devices,
the current consumption becomes unruly large. This is expressed by a heavy
load on the power supply and overheating of the circuit, which in turn dictates
the design and use of special implements for power (heat) dissipation.
EB-3155 – Logic Families
8
The following features are common to all TTL families:
Supply voltage - 5V  0.25V
'1' input voltage - ViH > 2.75V
'0' input voltage - ViL > 0.7V
'1' output voltage - VoH > 3V
'0' output voltage - VoH > 0.5V
In order to denote the sub-families, a letter or letters were added between the
first two digits (74/54) and the remainder of the numerical designation (the
ordinal number).
EB-3155 – Logic Families
9
We present below the sub-families, which have been developed (more of less
according to the order of events), comparing the three most significant
features which constitutes the major differences between them.
a) The basic family series (TTL)
Power dissipation
Delay time
Operating frequency
b) Low power TTL series
Power dissipation
Delay time
Operating frequency
c) Schottky TTL series
Power dissipation
Delay time
Operating frequency
54/7xxx
10mW per gate
10ns
35MHz
54/7Lxxx
1mW per gate
33ns
3MHz
54/7Sxxx
20mW per gate
3ns
70MHz
d) Low power Schottky TTL series
Power dissipation
2mW per gate
Delay time
9ns
Operating frequency
40MHz
54/7LSxxx
e) Advanced TTL series
Power dissipation
Delay time
Operating frequency
54/7Axxx
f) Fast TTL series
Power dissipation
Delay time
Operating frequency
5mW per gate
3ns
70MHz
54/7Fxxx
5.5mW per gate
3.7ns
125MHz
The transistors of the gates in the Schottky TTL series are produced by a
technology called "The Schottky Transistor Technology". In this technology,
the PN junction between the p-type semiconductor and n-type semiconductor
is replaces by a junction between METAL and a semiconductor. The
technology is characterized by extremely high speed switching times.
EB-3155 – Logic Families
10
1.3
CMOS technology
The families of gates in the CMOS technology are based on the MOSFET
devices. The MOSFET, or as also referred to "The Insulated Gate Transistor"
(IGFET), is symbolized as shown in figure 1-7.
D
G
S
n-channel MOSFET
D
G
S
p-channel MOSFET
Figure 1-7
In this transistor, the metal gate (G in the figure) is separated from the
semiconductor by an extremely thin silicon dioxide layer. The influence of the
gate on the semiconductor (and the conduction processes) is transferred by the
electric field. This is the reason for the name of the device – MOSFET (Metal
Oxide Semiconductor Field Effect Transistor). The conductance between the
source (S) and the drain (D) increases in an n-channel device as the gate
voltage becomes higher. The opposite is true for a p-channel device. If the
gate voltage is switched between two extreme levels, the MOSFET behaves
like, and can be considered as, a voltage controlled switch.
The materialization of logic gates by MOSFET transistors is very simple. We
do not have to use any resistances, nor any de Morgan transformations. The
technology is based on the coupling of the two types of transistors, which
complement each other. This is the reason for the C- in the name
Complementary MOSFET transistors.
EB-3155 – Logic Families
11
Examples of various gate materializations are depicted by figure 1-8.
VDD
VDD
VDD
A
A
Y
Y
Y
A
VSS
B
B
VSS
VDD
Figure 1-8 Various CMOS technology gates
We can see that the gates are made up of couples of complimentary n-channel
and p-channel transistors. The two respective gates of each couple are
connected together and constitute the input of the logic gate. When '1' is
applied at the input, the p-channel transistor connected to this input is cutoff
and the n-channel transistor is switched ON. When a '0' appears at the input,
the p-channel transistor is switched ON and the n-channel transistor is cutoff.
The transistors behave as switches. The logic circuits are based on integrating
combinations of switches in series and in parallel. Apply this hint to analyze
the gates introduced by figure 1-8.
The CMOS logic enjoys several important features. First, the simplicity of the
structure allows a highly dense construction to be used. No bias resistance has
to be used. Any voltage source from 3V to 18V may be connected to CMOS
technology devices. The insulated gate transistors draw negligible current and
its input impedance is virtually infinite. The order of magnitude of a CMOS
gate current is extremely low – its power consumption is only a few nanoW
per gate, which is an extremely low value.
EB-3155 – Logic Families
12
This last feature resulted in the early CMOS devices being susceptible to
electrostatic charging. The device could have even be charged in the free air,
or by the hand of a person holding it, to such a high voltage level, that it
would cause a discharge breakdown of the gate and to irreversible damage. A
protective net for safeguarding the device has been added and employed in
later types.
As a result of the gate insulation of the MOSFET transistors, capacitances are
formed at the inputs of the CMOS gates, which reduce the speed of the
devices. The early generations of these devices were not really intended for
high speed (high frequency) applications. Another limitation of the CMOS
devices is their inability to draw or drive current. This capability is lower than
that of the TTL gate devices, because of the high output impedance of the
MOSFET gate.
The CMOS family of devices has been assigned serial numbers of the form
4xxx or 14xxx. Devices conforming to the military specifications have been
assigned the suffix MIL (MILitary) at the head of the number. For no specific
reason, the manufacturers of devices have decided that the 4xxx series (as far
as the xxx ordinal number is concerned and also in the description of the pin
layouts) shall not be compatible with the 74xxx series. For example, it is
impossible to insert a TTL NAND gate device with two inputs into the socket
of a CMOS NAND gate device with two inputs, even though both devices do
have 14 pins.
Two advanced versions of the 4xxx series are the 4xxxB series (B for
Buffered) and the 4xxxUB (UnBuffered) series. The 4xxxB devices are
equipped with anti electrostatic charging protection, and the 4xxxUB devices
are devices exhibiting extremely high operation speeds.
Other series of CMOS devices are series intended to provide solutions to
device speed, and to render them nearly equal to the speed of the TTL family.
These sub-families were already organized in packages compatible with those
of the TTL family, thus we refer to them as "Pin Compatible". They have
similar ordinal numbers and so they are inter-changeable, provided their
current driving capabilities and the speeds are suitable.
EB-3155 – Logic Families
13
Examples:
a) CMOS in TTL packaging
Delay time
b) High speed CMOS
Power supply
Delay time
54/74Cxxx
20ns
54/7HCxxx
2-6V
10ns
c) High speed CMOS TTL compatible
Power supply
54/74HCTxxx
4.5-5.5V
By its features, this device is similar to the HC devices, but its current
driving capability is more similar to that of the LSTTL sub-family,
though drawing current in the fashion of the CMOS gates. Obviously,
this is a nearly ideal combination of features (the best of everything!).
d) Advanced CMOS
54/74ACxxx
Speed wise, it is similar to the advanced TTL devices, but its current
consumption is much lower.
e) Advanced CMOS TTL compatible
54/74CTxxx
Frequency performance of up to 200MHz combined with a CMOS gate
current consumption and current driving capability of the LSTTL.
f) Fast CMOS
This is a very fast, low power consumption family.
EB-3155 – Logic Families
54/74FCxxx
14
1.4
Input and output stages
1.4.1
Input stages
We have seen that the input stage of the TTL gates is composed of a multi
emitter transistor. We have also noted that an unconnected pin behaves as a
logic '1' state. With '0' at the input, a current flows through the device out of
the gate. This current is relatively high. In CMOS gates, the inputs consist of
MOSFET transistors. This input is a high impedance input, namely, the
current consumption at the gate is negligible. It is forbidden to leave an
unconnected pin in a CMOS device, because then, due to the high impedance,
the input potential shall be undefined in this case. It may behave as a '1' or '0',
or even oscillate between the two ('0' and '1').
Sometimes it is required to employ an external system in order to activate the
gate.
Examples:
a)
Connecting a switch, so that '0' is connected to the input when the switch
is pressed (ON). Releasing the switch, is supposed to supply a '1' to the
input. In this case, we require that when the switch is open, the input
shall be at '1'. On the other hand, we cannot short circuit the input to V CC,
because then VCC shall be connected to GND upon activating the switch.
We connect the resistor to accomplish this requirement. This is called "A
Pull Up Resistor", and is shown by figure 1-9.
VCC
R
Figure 1-9
EB-3155 – Logic Families
15
R is the pull up resistor. An accepted value of a VCC pull up resistor lies
in the 5K to the 10K range, for the TTL resistors case. A much higher
resistance may be used when CMOS gates are employed. It is possible, in
principle, to forgo the pull up resistor associated with TTL gates, but this
is not recommended.
b)
In the opposite case, where '1' is supplied when the switch is turned ON,
a pull down to GND resistor is required, as shown by figure 1-10.
VCC
R
Figure 1-10
The pull down to ground resistor shall not exceed the 1K to 1.5K
range, for the TTL pull down resistors case, because otherwise the
current flowing from the gate, shall have a large voltage drop across the
resistor, which would not be considered as a '0'. As before, a much higher
resistance may be used when CMOS gates are employed.
A concept related to input stages, is the "Fan In" input. This concept denotes
the number of inputs of the gate.
1.4.2
Output stages
In CMOS gates, the input stage constitutes also the output stage. Hence, in this
paragraph we discuss only output stages based on bipolar transistors. We have
presented the TTL NAND in figure 12-1. TR2 served as an output stage. We
have also learned that the level of the output current is limited, as a result of
the reasonable value of Rc. Under the conditions of '1' at the output and the
transistor TR2 at cutoff, Vo  VCC  I L  R C . The higher the current
consumption at the output, the lower will the output voltage be. Hence, we
strive for as far as practicable low Rc value.
EB-3155 – Logic Families
16
On the other hand, at a state with '0' at the output and transistor TR2 at
saturation, we are interested in as high as practicable Rc value, in order to
reduce the current consumption by the component. Hence, in the circuit
described earlier, we have to select Rc such that it would be a compromise
between the opposing requirements (approximately 300).
In case a large number of gates are driven, or if we have to drive a load, which
requires a relatively high current (say, more than 2-3mAmps), the resistance
of Rc may be lowered. This is accomplished by connecting a pulling resistor
between the output and VCC. This resistor is connected then in parallel to the
Rc transistor and reduces the resultant resistance at the collector of TR2.
This of course, makes things somewhat difficult for TR2, when it is in
saturation.
Also for the case of a capacitive reactance load connected to the output of the
gate, we prefer to lower the resistance Rc, in order to reduce the transition
times arising from the charging of the capacitor through Rc.
An ideal state would have been achieved, if between the collector and V CC we
would have installed a component whose resistance varies drastically. With a
'0' at the output, a very high resistance, and with a '1' at the output, a very low
resistance. Such a behavior can indeed be achieved.
EB-3155 – Logic Families
17
There exists an additional family of TTL's, carrying the designation "Buffer"
or "Driver", or both, in their technical data sheets. Such gates are terminated
by a stage known as "Totem Pole". This kind of output stages is used for a pair
of transistors, switched alternatively. The circuit diagram of this gate is
presented by figure 1-11.
VCC
TR3
RB
TR1
Q
TR2
TR4
Figure 1-11 "Totem Pole" gate
When TR2 is in saturation, TR4 is also in saturation and TR3 is at cutoff.
Hence, '0' is obtained at the output, with a very high resistance between the
output and VCC. When TR2 is at cutoff, TR4 is also at cutoff and TR3 in
saturation. '1' is obtained at the output with a very low resistance between the
output and VCC. This is an output state with a capability to both drive and pull
relatively high currents. When operating in capacitive load driving, fast
transition times are achieved.
Another type of gates being used is the one terminating with an open collector.
Simply, no resistor is connected between the output and VCC. They are mostly
employed in Wire-Or circuits. When using these gates, an external pull up to
VCC resistor has to be connected.
EB-3155 – Logic Families
18
Yet another output stage, which is particularly useful in microcomputer
systems, is the Tri-state stage. All the gates and components that we have
discussed so far, have one thing in common – their outputs could be in one of
two possible states: '0' or '1'. A gate, which includes a third state, possesses a
control input, which enables us to cutoff the output. The output enters a cutoff
state at which the two output transistors are at cutoff. This is referred to as the
"Tri-state" (third state) or also "High Impendance". This design enables the
connection of several outputs of components to a single line. The outputs are
activated one at a time, by employing a special control circuit. All the other
components, which are not active, do not cause interference, either. An
example of a gate of the type just presented is depicted by figure 1-12.
In
Out
E
Figure 1-12 Tri-state gate
We have mentioned that the input transistors of a CMOS gate also serve as
their output transistors. A FET transistor, even at its saturation state, does not
have a low output resistance. Hence, its capability of drawing or driving
current is not high. When a CMOS gate drives other CMOS gates, this
limitation is not of much importance, as in any case, the CMOS gates input
current consumption is very low.
When HCT or ACT logic configuration is used, the output stage of the gate is
a bipolar state, in order to arrive at the same current driving capability as in
TTL.
Another concept related to output stages, is the "Fan Out" concept. This
parameter indicates the number of gate inputs, which can be connected to the
output of a gate. All the connected gates are of the same family and each
family has a different fan out value.
EB-3155 – Logic Families
19
1.4.3
Characteristics
The typical characteristics of a gate are the input characteristics, the output
characteristics and the transfer characteristics. The input characteristics
describe the relation between the input current Ii and the input voltage Vi. For
example, the input characteristics of a TTL gate resembles the shape presented
by figure 1-13.
Iin
0.7
Vin
1.4
Figure 1-13 Input characteristics
From the graph, we learn that as long as Vi is lower than 1.4V, the current is
flowing outwards from the gate (a negative current). For Vi under 0.7V, we
obtain a straight line whose slope is actually Rb. When Vi is higher than 1.4V,
the current is a leakage current flowing into the gate.
There are two output characteristics for each gate. One for the case of '1' at the
output and the other with '0' at the output. Generally, with '0' at the output, the
voltage is simply very close to zero, with just a slight slope away from it. The
output characteristics with '1' at the output, is depicted by figure 1-14.
Vo
Io
Figure 1-14 Output characteristics
We see that as the output current increases, the output voltage decreases.
EB-3155 – Logic Families
20
The most important characteristic of a gate is the transfer characteristic. It
describes the relation between the output voltage and the input voltage. It also
presents several parameters relating to the gate. The transfer characteristic of a
TTL gate, for example, is depicted by figure 1-15.
Vo
NM0
E
D
C
B
Vi
A
NM1
Figure 1-15 Transfer characteristic
The points on the characteristic:
A is the operation point at which Vi = '1' (Vo = '0').
E is the operation point at which Vi = '0' (Vo = '1').
B is the marginal point for Vi = '1'.
D is the marginal point for Vi = '0'.
B and D are called "Unity Gain Points". At this point, the angle of the tangent
to the characteristics is 45o, and hence
ΔVo
ΔVi
 1.
The range between B and D is an undefined range of the curve for the gate, as
far as '0' and '1' are concerned. The crossing point between the straight line
connecting the operation points A and E with the characteristics is called the
threshold point and this is point C.
EB-3155 – Logic Families
21
An important parameter is the gap in volts between D and E, denoted NM0,
and the gap in volts between A and B, denoted NM1. Nm is the acronym of
Noise Margin. The concept of "noise" in electronics describes an unwanted
random voltage, which appears as a signal interfering with the desired signal.
The noise margins represent the amount of noise, which is capable of causing
the transition of the gate from its operating point to beyond the unity gain
point. In principle, we strive to obtain as high noise margin levels as possible.
Another phenomena, also related to the transfer characteristics, is the
following phenomena. In Totem Pole type TTL's gates and in CMOS gates,
there is hardly any current at the operation region ('0' and '1'). One of the
transistors is always at cutoff. On the other hand, in the transfer region
(between B and D), both transistors are conducting. One is just switching over
from cutoff to saturation, and the other goes from saturation to cutoff. Rather a
high enough current flows at the output stage. When a large number of gates
have their states changing simultaneously, a large current consumption from
the power supply is generated momentary, which may cause a momentary
voltage drop. For this reason, it is recommended to distribute capacitors
between VCC and GND in digital circuits, in order to account for this
momentary switching current demands. These capacitors are called filtering
capacitance. The accepted value is 0.1F. It is also desirable to connect, in
addition, one large capacitor between VCC and GND in each circuit, of say
from 10 to 47F, its value being determined by the size of the circuit.
1.4.4
Schmitt trigger
Sometimes the input voltage of the gate varies gradually. This state of affairs
may arise, for example, when a signal arriving at the input of the gate comes
from a capacitor being charged or from a sinusoidal wave, etc. The signal at
the input then varies at a continuous way and gradually, and hence the gate
will stay a relatively long time in its transfer range, between B and D. At the
range, the output of the gate is not uniquely defined, and in many cases we
shall obtain bouncing at the output, because small variation of V i at the
transfer region cause large variation of Vo.
In order to overcome this problem, a gate with a special transfer characteristics
is used – the characteristics being of the hysteresis loop type. The name of the
circuit with this property is "Schmitt Trigger", and it is denoted by the
following symbol: .
EB-3155 – Logic Families
22
Figure 1-16
The name hysteresis is borrowed from the electromagnetic field theory, where
it was first detected in transitional effects (the transfer characteristics). It looks
like the transfer characteristics presented by figure 1-17.
Vo
D
C
A
B
Vi
Figure 1-17 Hysteresis transfer characteristics
The outstanding trait of these characteristics, is that there exists a range at
which for the same value of Vi – two values of Vo are possible. The point
(value) we shall be operating in, depends on the direction from which we have
arrived to this point.
When Vi < A, namely '0', Vo shall equal '1' (D).
If Vi rises, it has to rise above the value of B for Vo to change its state and
drop to '0' (C). If Vi shall decrease now, it has to get lower than the value of A
for Vo to rise again to the '1' value. This time, it will not suffice that V i just
goes under B. In this manner, the transition region has been neutralized, and
Vo accepts a single, uniquely determined value. However, it still is important
to note the direction from which we have arrived into the range between A and
B.
EB-3155 – Logic Families
23
1.5
Gates materialized by discrete components
In the past, gates were materialized by discrete components, such as
transistors, resistors and diodes. This logic was called RTL (Resistor
Transistor Logic) and DTL (Diode Transistor Logic). In our times this logic
circuits have been replaced by integrated circuits (IC's). However, it is
important that we shall be familiar with these modes of gate implementation.
Sometimes we need a single gate and we do not want to use an integrated
circuit for this end. This is especially so, if the quality of the gate is not
particularly important. It also may happen that we have to add a gate to an
already existing circuit.
In such a case, it is much easier to add a discrete component than to add an IC
component.
Figure 1-18 depicts the method for materializing an AND gate.
VCC
R
A
Y
B
Figure 1-18 Materializing an AND gate by diodes
If the value at one of the inputs shall be '0', the diode shall conduct and the
voltage at output Y shall be a low (0.7V when the diode is a silicon solid state
diode, and 0.1V for germanium diodes). Only when the state of both inputs is
at logic '1', we shall obtain '1' at the output (the diodes shall not be
conducting), and the voltage shall be very near to VCC.
EB-3155 – Logic Families
24
The method for materializing an OR gate is depicted by figure 1-19.
A
Y
B
R
Figure 1-19 Materializing an OR gate by diodes
If the value at one of the inputs is '1', the diode connected to this input shall
conduct and '1' shall also appear at the output, its value being equal to the
input voltage minus the potential drop across the conducting diode. Only when
'0' exists at both inputs, the diodes shall not be conducting, and the resistor R
is determined in accordance with the type of the gate connected to Y,
An inverting gate, materialized by a transistor and two resistors, is shown in
figure 1-20.
VCC
RC
Y
A
Figure 1-20 Materializing an NOT gate by diodes
When Vi = '1', we see to it that the transistor shall be in saturation and then the
output Y is at '0'.
When Vi = '0', we drive the transistor to cutoff, and then the output Y shall be
at '1'.
EB-3155 – Logic Families
25
The value of the resistor R is calculated in accordance with the maximum
current density designed to flow through the output with state '1' at the output.
Under saturation conditions, the current Ic of the transistor is given by the
following relations:
I c, sat 
Vcc  Vce, sat
Rc
Where sat stands for "saturation".
From this we can derive the value of the current Ib, required to drive the
transistor into saturation. This is given by:
I b ,sat 
I C,sat
 min

VC C  Vce,sat
 min  R C
If the voltage of '1' at the input is defined as ViH (where iH = input High), we
shall obtain:
Rb 
1.6
ViH  Vbe
I b , sat
Technical specifications & data sheets reading
The manufacturers of electronic components provide technical specifications
sheets for each component they produce. In general, these data sheets are
collected in a binder or printed as a book (The Components Catalog). The data
sheets have a more or less standard format. Two such data sheets are reprinted
in the following two pages, divided, as you can see, to smaller rectangles.
Rectangle number 1 (see numbers at top right corner of each item) includes
the descriptive number of the component and a one line short description of
the device. The "component number" designates the family, the sub-family
and whether it is of military or commercial specification device.
Rectangle number 2 provides a more detailed description of the device. This
rectangle is used by the manufacturer to disclose information about the
component and to extol its most important features.
EB-3155 – Logic Families
26
2
MOTOROLA
DESCRIPTION – the LSTTL/MSI SN54LS/74LS139 is a high
speed dual 1 of 4 decoder/demultiplexer. The device has two
independent decoders, each accepting two inputs and providing
four mutually exclusive active LOW outputs. Each decoder has an
active LOW enable input which can be used as a date input for a 4output demultiplexer. Each half of the LS139 can be used as a
function generator providing all four minterms of two variables.
The LS139 is fabricated with the Schottky barrier diode process
for high speed and is completely compatible with all Motorola TTL
families.



SCHOTTKY PROCESS FOR HIGH SPEED
MULTIFUNCTION CAPABILITY
TWO COMPLETELY INDEPENDENT 1 OF
DECODERS
 ACTIVE LOW MUTUALLY EXCLUSIVE OUTPUTS
 INPUT CLAMP DIODES LIMIT HIGH SPEED
TERMINATION EFFECTS
ABSOLUTE
RATINGS
(above which the useful life may be impaired)
LS
Storage Temperature
- 65oC to +150oC
Temperature (Ambient) Under Bias
- 55oC to +125oC
Vcc Pin Potential to Ground Pin
- 0.5V to +7.0V
*Input Voltage (dc) diode Inputs
- 0.5V to +15V
*Input Current (dc)
- 30mA to +5.0mA
Voltage Applies to Open collector
Outputs (Output HIGH)
- 0.5V to +10V
High Level Voltage Applied to
Disabled 3-State Output
- 5.5V
* Either input voltage limit or input circuit limit is sufficient to
protect the inputs.
7
A0a A1a
E'a
1
2
15
DUAL 1 OF 4 DECODER/
DEMULTIPLEXER
LOW POWER SCHOTTKY
LOGIC SYMBOL
1
2 3
E
A0 A1
4
15
14 33
E
A0 A1
DECODER a
DECODER b
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
4 5 6 7
12 33 31 9
5
Vcc = Pin 16
GND = Pin 8
6
CONNECTION
DIAGRAM
DIP (TOP VIEW)
1
Vcc
16
2
E'a
A0a
E'b
15
3
A1a
A0b
4
Q'0a
A1b
14
13
5
Q'1a
Q'0b
12
6
Q'2a
Q'1b
11
7
Q'3a
GND
Q'2b
10
Q'3b
9
8
A0a A1a
E'a
3
SN54LS139
SN74LS139
4
MAXIMUM
LOGIC
DIAGRAM
1
14
13
3
J Suffix – Case 620-08 (Ceramic)
N Suffix – Case 648-05 (Plastic)
NOTE:
4
Vcc = Pin 16
GND = Pin 8
= Pin No.
5
6
7
32
Q'0a Q'1a Q'2a Q'3a
33
31
9
Q'0a Q'1a Q'2a Q'3a
EB-3155 – Logic Families
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
27
8
GUARANTEED OPERATING RANGES
SYMBOL
PARAMETER
Vcc
Supply Voltage
TA
Operating Ambient Temperature Range
IOH
Output Current – High
IOL
Output Current – Low
54
74
54
74
54
74
54
74
MIN
TYP
MAX
UNIT
4.5
4.75
-55
0
5.0
5.0
25
25
5.5
5.25
125
70
-0.4
-0.4
4.0
8.0
V
o
C
mA
mA
9
FUNCTIONAL DESCRIPTION – The LS139 is a high speed dual 1 of 4 decoder/demultiplexer fabricated
with the Schottky barrier diode process. The device has two independent decoders, each of which accept two
binary weighted inputs (A0, A1) and provide four mutually exclusive active LOW outputs ( Q 0 - Q 3 ). Each
decoder has an active LOW enable ( E ). When E is HIGH all outputs are forced HIGH. The enable can be
used as the data input for a 4-output demultiplexer application.
Each half of the LS139 generates all four minterms of two variables. These four minterms are useful in
some applications, replacing multiple gate functions as shown in Fig. a and thereby reducing the number of
packages required in a logic network.
E
TRUTH TABLE
INPUTS
A0
OUTPUTS
E
Q1
A0
E'
A0
A1
Q'0
Q'1
Q'2
Q'3
A1
E
A1
E
H
X
X
H
H
H
H
A0
Q1 A0
L
L
L
L
H
H
H
L
H
L
H
L
H
H
A1
E
A1
E
L
L
H
H
H
L
H
A0
Q2 A0
L
H
H
H
H
H
L
A1
E
A1
E
A0
Q3 A0
A1
A1
H = HIGH voltage Level
L = LOW Voltage Level
X = Don't Care
EB-3155 – Logic Families
Q1
Q1
Q2
Q3
28
Rectangle number 1 describes the component number description. The
component number indicates the family, the sub-family and if it is a military
or commercial characterization.
Rectangle number 2 includes a more detailed description of the component.
Here the manufacturer tells us about the best qualities of the component.
Rectangle number 3 describes the available packages in which the component
may be purchased. An IC component has two main types of packages, of the
so called DIP (Dual In line Package). One is the plastic package and the other
is the ceramic one. The ceramic package has a much better heat dissipation
properties and thus allows better conformance with environmental temperature
condition specifications. It also is a more robust package.
Rectangle number 4 presents maximum ratings prescribed for the component.
The significance of these values is, that if we use higher (lower) values than
prescribed, we may cause damage to the component (including irrecoverable
damage). The manufacturer also specifies, that in the allowed range of
parameters, there is no danger to the life of the component.
Rectangle number 5 presents the logic symbol of the device. This symbol aids
in understanding the functions of the component, in a much clearer manner
than just describing the functions of its pins. In this representation of logic
symbols, though, the pin numbers are included.
Rectangle number 6 designates the description of the pins of the component,
according to their location and function.
Rectangle number 7 presents the electrical drawing of the component. It is a
rather technical drawing, and usually it is not being used. It is, however, of
interest to us when we wish to find out the flow of the signals in the
component (how many stages it passes), the structure of the output stage or its
logic.
Rectangle number 8 designates the parameters related to the component.
These are the characteristically parameters. The manufacturer provides the
name of the parameter, the conditions under which it has been measured, its
symbol, the typical values and their units.
EB-3155 – Logic Families
29
The values are given in three columns: minimum value, typical and maximum
value. Usually the manufacturer gives only the typical value and the worst
value (from the user's point of view). For example, when discussing the input
resistance, he shall provide the typical value and the lowest value that may be
found in this component. On the other hand, if a parameter like transit time is
quoted, the manufacturer shall provide the typical value and the highest value
this parameter may present for this specific component.
Rectangle number 9 is a table of states describing the operation of the
component in accordance with the states at the inputs. Not all the components
necessitate a table of states to be presented.
After those two pages, additional pages presenting diverse characteristics
follow, Input characteristics, transfer characteristics, output characteristics,
dependence on temperature, transition times and so on.
EB-3155 – Logic Families
30
Preparation questions:
1.
What is the Vi voltage of a TTL NOT gate that above it the gate output is
low for sure?
ViH > ______V
2.
What is the Vi voltage of a TTL NOT gate that below it the gate output is
high for sure?
ViH < ______V
3.
What gate represents the following two open collector NOT gates?
B4
OPEN COLECTOR
VCC
R1
1K
(a)
(b)
(c)
(d)
AND
OR
NAND
NOR
EB-3155 – Logic Families
31
4.
In the following circuit, which switch affect the LED (S0 or S2) when
S1 = 1?
S0
L0
S1
S2
(a)
(b)
(c)
(d)
S0
S2
Both
None
EB-3155 – Logic Families
32
Procedure:
Step 1:
Connect the EB-3100 to the power supply.
Step 2:
Connect the power supply to the Mains.
Step 3:
Turn ON the trainer. The DVM screen should appear on the display.
Step 4:
Plug the EB-3154 into the EB-3100.
Step 5:
Observe the display and check that the experiment board name
appear and no fault is detected.
TTL transfer characteristics:
Step 6:
Set the function generator to triangle 1KHz 10Vp-p signal.
Step 7:
Connect the function generator output to the TTL NOT gate input.
Step 8:
Also connect the function generator output to oscilloscope probe
CH1.
Step 9:
Connect the output of the TTL NOT gate to CH2.
Step 10: Draw the two signals.
Step 11: Write the input voltage at which the output voltage changes from
High to Low.
Step 12: Write the input voltage at which the output voltage changes from
Low to High.
CMOS transfer characteristics:
Step 13: Connect the function generator output to the CMOS NOT gate
input.
Step 14: Also connect the function generator output to oscilloscope probe
CH1.
EB-3155 – Logic Families
33
Step 15: Connect the output of the CMOS NOT gate to CH2.
Step 16: Draw the two signals.
Step 17: Write the input voltage at which the output voltage changes from
High to Low.
Step 18: Write the input voltage at which the output voltage changes from
Low to High.
Schmitt Trigger transfer characteristics:
Step 19: Connect the function generator output to the Schmitt Trigger NOT
gate input.
Step 20: Also connect the function generator output to oscilloscope probe
CH1.
Step 21: Connect the output of the Schmitt Trigger NOT gate to CH2.
Step 22: Draw the two signals.
Step 23: Write the input voltage at which the output voltage changes from
High to Low.
Step 24: Write the input voltage at which the output voltage changes from
Low to High.
EB-3155 – Logic Families
34
Open collector application:
Step 25: Connect the inputs of the two open collector NOT gates to switches
S0 and S1.
B4
OPEN COLECTOR
VCC
R1
1K
Step 26: Connect the output of the two open collector NOT gates to the L0
LED.
Step 27: Change the switches and fill in the following table.
S1 S0 L0 Vout
0 0
0 1
1 0
1 1
Step 28: Is the Vout of the two gates in a not determined voltage range
(between 0.7V to 2.7V) in one of the input states?
Step 29: What kind of gate the two NOT gates act as?
EB-3155 – Logic Families
35
Tri-state gates:
Step 30: Connect the three inputs of the tri-state component circuit to the
switches S0,S1,S2 as follows:
S0
S1
S2
S1 acts as the selector switch.
Step 31: Set S1 to '0'.
Step 32: Change S0 and S2 and record the output voltage of the two buffers
in each state.
Step 33: Set S1 to '1'.
Step 34: Change S0 and S2 and record the output voltage of the two buffers
in each state.
Step 35: Connect both the two outputs to L0.
S0
L0
S1
S2
Step 36: Set S1 to '0'.
Step 37: Change S0 and S2.
Which one affects the L0 LED and why?
Step 38: Set S1 to '1'.
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Step 39: Change S0 and S2.
Which one affects the L0 LED and why?
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Summary questions:
1.
What is the Vi voltage of a TTL NOT gate that above it the gate output is
low for sure?
ViH > ______V
2.
What is the Vi voltage of a TTL NOT gate that below it the gate output is
high for sure?
ViH < ______V
3.
What gate represents the following two open collector NOT gates?
B4
OPEN COLECTOR
VCC
R1
1K
(a)
(b)
(c)
(d)
AND
OR
NAND
NOR
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4.
In the following circuit, which switch affect the LED (S0 or S2) when
S1 = 1?
S0
L0
S1
S2
(a)
(b)
(c)
(d)
S0
S2
Both
None
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Experiment 2 – Troubleshooting
Objectives:
 Troubleshooting faults in an electrical circuit.
Equipment required:
 EB-3100
 EB-3154
 Banana wires
Discussion:
The EB-3100 includes 10 relays for fault insertion or for switching external
components.
The fault screen is selected by the Options/Graph key.
FAULTS
Please choose
Fault No.: 0–9
Activated fault
Number: 0
Num Lock
Typing a fault number and pressing ENTER operates the required relay for the
required fault.
Fault No. 0 means No Fault.
Which relay creates the required fault is registered in the plug-in experiment
board controller.
On entering a fault number, the system addresses the experiment board
controller and asks for the relay number. After that, it executes the required
fault.
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The experiment board controller saves the last registered fault number in its
memory. This memory is non-volatile.
This is why the system does not allow us to enter a fault number when no
experiment board is plugged.
When an experiment board that a certain fault (other than zero) is registered in
its memory is plugged into the system, a warning message appears on the
system's screen.
This feature enables the teacher to supply the students various experiment
boards with planted faults for troubleshooting.
Note:
It is recommended (unless it is otherwise required), to return the
experiment board fault number to zero before unplugging it.
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Procedure:
Step 1:
Connect the EB-3100 to the power supply.
Step 2:
Connect the power supply to the Mains.
Step 3:
Turn ON the trainer. The DVM screen should appear on the display.
Step 4:
Plug the EB-3155 into the EB-3100.
Fault No. 1:
Step 5:
Implement the following circuit.
TTL
S0
CMOS
L0
S1
L1
NOT1
S2
NOT2
L2
S3
Step 6:
Enter fault no. 1.
What is the fault?
(a)
(b)
(c)
(d)
NOT1 input is not connected.
NOT2 input is not connected.
TTL input is not connected.
CMOS input is not connected.
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Fault No. 2:
Step 7:
Implement the following circuit.
TTL
S0
CMOS
L0
S1
L1
NOT1
S2
NOT2
L2
S3
Step 8:
Enter fault no. 2.
What is the fault?
(a)
(b)
(c)
(d)
NOT1 input is not connected.
NOT2 input is not connected.
TTL input is not connected.
CMOS input is not connected.
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Fault No. 3:
Step 9:
Implement the following circuit.
TTL
S0
CMOS
L0
S1
L1
NOT1
S2
NOT2
L2
S3
Step 10: Enter fault no. 3.
What is the fault?
(a)
(b)
(c)
(d)
NOT1 input is not connected.
NOT2 input is not connected.
TTL input is not connected.
CMOS input is not connected.
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Fault No. 4:
Step 11: Implement the following circuit.
TTL
S0
CMOS
L0
S1
L1
NOT1
S2
NOT2
L2
S3
Step 12: Enter fault no. 4.
What is the fault?
(a)
(b)
(c)
(d)
NOT1 input is not connected.
NOT2 input is not connected.
TTL input is not connected.
CMOS input is not connected.
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Fault No. 5:
Step 13: Implement the following circuit.
S0
L0
S1
S2
Step 14: Enter fault no. 5.
What is the fault?
(a)
(b)
(c)
(d)
The gate input of S0 is not connected.
The gate input of S1 is not connected.
The gate input of S2 is not connected.
The gate output is not connected.
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Fault No. 6:
Step 15: Implement the following circuit using the B1 and B6 components.
S0
L0
S1
S2
Step 16: Enter fault no. 6.
What is the fault?
(a)
(b)
(c)
(d)
The gate input of S0 is not connected.
The gate input of S1 is not connected.
The gate input of S2 is not connected.
The gate output is not connected.
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Fault No. 7:
Step 17: Implement the following circuit using the B1 and B6 components.
S0
L0
S1
S2
Step 18: Enter fault no. 7.
What is the fault?
(a)
(b)
(c)
(d)
The gate input of S0 is not connected.
The gate input of S1 is not connected.
The gate input of S2 is not connected.
The gate output is not connected.
EB-3155 – Logic Families