Download here

SOUTH EUROPEAN TEST SEMINAR - SETS 2017
AIM AND SCOPE
The aim of the seminar is to bring together Ph.D. stu- dents and researchers from universities and
companies to establish a forum for discussion and presenting the latest research results. Topics
include, but are not restricted to the following:
- Design for Testability, BIST and Embedded Test - Test Design for Reliability and Fault Tolerance - ATPG and Fault Simulation / Emulation - Defect-Oriented, Mixed Signal and Analog Test - Low Power Design and Test - Fault Diagnosis PROGRAM
1. MONDAY, MARCH 20 TH
Seminar Room: Opening Session 19:00
Welcome Introduction: Lorena Anghel
2. TUESDAY, MARCH 21 ST
08:00- 10:00 Morning Talks : Security Related Topics
Session Moderator: Giorgio Dinatale, LIRMM
Dr. Michael Kochte, U. of Stuttgart
i.
ii.
Ahmed Atteya, U. of Stuttgart
Specification and Verification of Access
Protection in Reconfigurable Scan Networks
Secure Filter for Reconfigurable Scan Network
Matthias Sauer, U. Freiburg
Sensitized Path PUF: A Lightweight Embedded
Physical Unclonable Function
Mael Gay – U. Passau
Small scale AES toolbox: Algebraic and
propositional formulas, circuitimplementations and fault equations."
17:00-19:00 Afternoon Talks: Scan, Compression, Functional Testing
Session Moderator: Hans-Joachim Wundelich, U. of Stuttgart
Mathieu Da Silva, LIRMM
Scan Chain Encryption for the Test, Diagnosis
and Debug of Secure Circuits
iii.
Harshad Dhotre (University of Bremen)
Automated Optimization of Scan Chain
Structure for Test Compression-Based Designs
iv.
Sebastian Huhn (DFKI Bremen,
University of Bremen)
VecTHOR: Architecture of TAP controller with
embedded compression and retargeting
framework
v.
Riccardo CANTORO, Politecnico di
Torino
Recent advancements in SBST
3. WEDNESDAY, MARCH 22 ND
08:00- 10:00 Morning talks: Emerging Technologies Applications
Session Moderator: Mehdi Tahoori, Karlsruhe Institute of Technology
i.
Ioana Vatajelu, TIMA
Embedded Tutorial: Emerging Technologies
based Neuromorphic Structures
Laura Roriguez, U. of Stuttgart
Neural-Network-based Fault Classification
Zahra Paria Najafi Haghi, U. of Stuttgart
Design Optimization and Fault Models in QCAbased Circuits
Samir Ben Dodo, KIT
Hardware Security Primitives based on
Sprintonics
17:00-19:00 Afternoon Talks: Fault Tolerant Design Related Topics
Session Moderator: Session Moderator: Sybille Hellebrand, U. Paderborn
ii.
Wenjing Rao, ECE department, University
of Illinois at Chicago, USA
iii.
Modeling and Constructing a guaranteed kFault Tolerance System
Matthias Kampmann, U. Paderborn
Efficient Output Masking for Faster-than-atSpeed Test
Florian Negebauer – U. Passau
Framework for quantifying and managing
accuracy in stochastic circuit design
Robust Printed Electronics Circuit Design
Dennis Weller, KIT
2
THURSDAY, MARCH 23RD
08:00-10:00 Morning Talks: Test At Speed Test related Topics
Session Moderator: Stephan Eggersgluss, U. Bremen
Chang Liu, U. of Stuttgart
Aging Monitor Reuse for Small Delay Fault
Testing
Alexander Sprenger, U. Paderborn
X-Reduction using Stochastic Compaction for
FAST
Marco RESTIFO, Politecnico di Torino
Advanced Functional Schema for optimized
Test and Stress of Automotive SoC
Felix Neubauer: U. Feiburg
iSAT3: Accurate Reasoning for Floating-Point
Arithmetic
16:00-17:20 Afternoon Talks: Miscellaneous Test Issues
Session Moderator: Ilia Polian, U. Passau
Stefan Holst, Assistant Professor, Kyushu
iv.
Institute of Technology
Analysis and Mitigation of IR-Drop Induced
Scan Shift-Errors
v.
vi.
Marcello Traiola, LIRMM
Test of Approximate Circuits
Pascal Raiola
SAT-based Combinational and Sequential
Dependency Computation
4. FRIDAY, MARCH 24 TH
CLOSING ACTIVITIES
3
ABSTRACTS
1. SECURITY RELATED TOPICS
Dr. Michael Kochte, U. of Stuttgart
Specification and Verification of Access Protection in Reconfigurable Scan Networks
A large amount of on-chip infrastructure, such as design-for-test, debug, monitoring, or calibration, is
required for the efficient manufacturing, debug, and operation of complex hardware systems. The access
to such infrastructure poses severe system safety and security threats since it may constitute a sidechannel exposing internal state, sensitive data, or IP to attackers.
Reconfigurable scan networks (RSNs) have been proposed as a scalable and flexible scan-based access
mechanism to on-chip infrastructure. While secure RSN architectures have been recently considered in
literature, the increasing number and variety of integrated infrastructure as well as diverse access
constraints over the system lifetime demand for systematic methods for the specification and formal
verification of access protection and security properties in RSNs.
This work presents a novel method to specify and verify fine-grained access permissions and restrictions
to instruments attached to an RSN. The permissions and restrictions are transformed into predicates
that are added to an overall model of a given RSN to formally prove which access properties hold or do
not hold.
Ahmed Atteya, U. of Stuttgart
Secure Filter for Reconfigurable Scan Network
Reconfigurable Scan Networks (RSNs) can be used to access, test, and configure different instruments
on modern SOCs. However due to the complexity of their structures, new methods need to be developed
to ensure the security of the SOCs and prevent attackers from being able to access or configure secured
parts of the RSN. In this work, a new technique is presented for creating filters for RSNs that is able to
detect and prevent attempts of access to protected registers. As well as ensuring that only well formed
accesses are performed.
Matthias Sauer, U. Freiburg
Sensitized Path PUF: A Lightweight Embedded Physical Unclonable Function
Physical unclonable functions (PUFs) can be used for a number of security applications, including secure
on-chip generation of secret keys. We introduce an embedded PUF concept called sensitized path PUF
(SP-PUF) that is based on extracting entropy out of inherent timing variability of modules already
present in the circuit. The new PUF sensitizes paths of nearly identical lengths and generates response
bits by racing transitions through different paths against each other. SP-PUF has lower area overhead
and higher speed than earlier embedded PUFs and requires no helper data stored in non-volatile
memory beyond standard error-correction information for fuzzy extraction. Compared with standalone
PUFs, the new solution intrinsically and inseparably intertwines PUF behavior with functional circuitry,
thus complicating invasive attacks or simplifying their detection.
Mael Gay – U. Passau
Small scale AES toolbox: Algebraic and propositional formulas, circuit-implementations and
fault equations."
Cryptography is one of the key technologies ensuring security in the digital domain. As such, its
primitives and implementations have been extensively analyzed both from a theoretical, cryptoanalytical perspective, as well as regarding their capabilities to remain secure in the face of various
attacks.
4
One of the most common cyphers, the Advanced Encryption Standard (AES) [1] (thus far) appears to be
secure in the absence of an active attacker. This renders the research and development of new or
improved attacks difficult because it is unlikely that the entire cipher will be broken right away. To
resolve this issue, [2] presented a small scale version of the AES with a variable number of rounds,
number of rows, number of columns and data word size, and a complexity ranging from trivial up to the
original AES.
In this paper we present a collection of various implementations of the relevant small scale AES versions
based on hardware, algebraic representations and their translation into propositional formulas.
Additionally, we present fault attack equations for each version.
5
2. SCAN, COMPRESSION, FUNCTIONAL TESTING
Mathieu Da Silva, LIRMM
Scan Chain Encryption for the Test, Diagnosis and Debug of Secure Circuits
Crypto-processors are the target of scan attacks. An attacker exploits facilities offered by scan chains to
retrieve embedded secret data closely related to the key. However, scan design is the most popular and
efficient method to test circuit. The goal is to preserve test efficiency, diagnostic and debug while
counteracting security threats. The solution proposed is to use the secret key already stored in the circuit
under test in order to encrypt test patterns by adding extra blocks ciphers. Both control and observed
test data are thus unusable without the knowledge of the key.
Harshad Dhotre (University of Bremen)
Automated Optimization of Scan Chain Structure for Test Compression-Based Designs
The physical defects caused due to impurities or process flaws during the manufacturing of an Integrated
Circuit (IC) results in stuck-at, stuck-open, bridging and delay faults.
These faults may cause malfunctioning of an IC and causing failure of system. These faults are modeled
and detected with help of Design for Testability (DFT) techniques. The Embedded Deterministic Test
(EDT) based designs are used in some IC’s to compress the scan test patterns and decrease the Test Data
Volume (TDV) thereby reduce test time and corresponding costs. The Automatic Test Pattern Generation
(ATPG) tool attempts to find an input assignment or patterns for a circuit such that the faults are
detected for the EDT based design. The faults which cannot be detected due to insufficient encoding
capacity of EDT and linear dependency are called as EDT Aborts (EAB). The EAB faults cause a notable
coverage loss in some designs.
A new approach is proposed to form scan chains which results in reduced number of EAB faults and
increase in the test coverage considering timing constraints or routing. This approach places the scan
cells corresponding to care bits at appropriate positions reducing linear dependency during pattern
generation. The previous approaches in industries to change scan chain architecture were to reduce
power and increase speed but not in improving test coverage or reduce EAB faults. The new approach
was used on some industrial projects as benchmarks and the results were found to be better than the
previous by default architecture. The approach is totally automated and can be integrated into the
existing design flow.
Sebastian Huhn (DFKI Bremen, University of Bremen)
VecTHOR: Architecture of TAP controller with embedded compression and retargeting
framework
System-on-Chip (SoC) designs are widely used in the semiconductor industry which typically contain
several nested sub-modules at once. These SoC designs necessitate board as well as in-field testing
capabilities and, furthermore, debugging techniques have also to be applicable. Generally, a dedicated
test access mechanism is embedded into the design to allow access to certain sub-modules. For instance,
the IEEE 1149.1 Std. specifies a commonly used test interface. In this scenario, strong memory
limitations exist on the test equipment that restrict the testing respectively debugging capabilities of
complex designs. Furthermore, due to the typical slow transfer speed of those interfaces, the test
application time should be also taken into account.
To tackle both challenges, i.e., reducing the test data volume as well as the test application time, a
standardized IEEE-1149.1-compliant TAP controller is extended by a dynamically configurable codebased compression architecture. This extension sill ensures the full legacy support and allocates only
slightly more hardware resources. Besides this architecture, a suitable software framework is required
that processes existing test sequences to take advantage of the proposed compression technique.
Hereby, the actual configuration of the embedded dictionary is most important. To realize this
retargeting procedure, a heuristic retargeting algorithm is drawn and benchmark runs show that some
shortcomings exist while processing high-entropic test data. Thus, a formal optimization-based
approach is implemented which determines an optimal dictionary that leads to higher compression in
test data volume and a reduced test application time. However, this formal approach consumes a high
6
run-time for the retargeting procedure which limits the overall size of test data that can be processed.
Consequently, this work introduces a partitioning technique into the retargeting flow. By invoking this
scheme, test data of arbitrary size can be processed. Additionally, the embedded compression technique
is extended in the way that a reconfiguration is also supported within the data stream, not only once in
front of the data transfer. Thus, the formal engine determines optimal dictionary partitions being
configured partition-wise leading to better results especially for huge test data sizes.
Benchmarks have shown that this approach allows to reduce the test data volume measurably even for
high-entropic data. For instance, the volume of fully-specified test data for industrial designs were
reduced by up to 50% and the number of required test cycles were decreased by nearly a fifth at once.
Finally, results of the current work in progress is drafted which improves the retargeting process even
more by introducing a partitioning and multi-reconfiguration scheme.
Riccardo CANTORO, Politecnico di Torino
Recent advancements in SBST
Software-based self-test (SBST) is becoming a real solution for the in-field test of modern electronic
devices based on microprocessors. This technique consists in uploading a test program in the available
memory (e.g., flash, caches) and forcing the processor to execute it: when the behavior (or results) of the
program is deviated in presence of a fault, then the fault is detected. This talk discusses about state-ofthe art and future perspectives of SBST generation techniques, highlighting their main advantages and
limitations when applied to industrial design flows. Experimental results are presented on both
academic and industrial processors.
7
3. EMERGING TECHNOLOGIES APPLICATIONS
Ioana Vatajelu, TIMA
Embedded Tutorial: Emerging Technologies based Neuromorphic Structures
The power and reliability issues of today's memories limit the improvements attained by their
implementation in scaled technology nodes. Several emergent memory technologies attempt to address
the technical constraints of today's memories, amongst which, the most promising solutions are the
Spin-Transfer-Torque Magnetic Random Access Memories (STT-MRAMs) and the Resistive Random
Access Memories (RRAM). One of the great advantages of the emerging memories is that they favor
increasing system complexity and performance. New applications and computation paradigms, such as
neuromorphic computing, unfeasible a few years back due to technological limitations, can take profit
from this technology. Intensive research has been conducted recently related to resistive and magnetoresistive device physics and their implementation as dedicated hardware for neuromorphic computing,
however, little work has been conducted to evaluate the reliability of such circuits. In this talk I will
describe the main characteristics of neuromorphic synaptic weights and artificial neutrons and how they
can be implemented using the main emerging memory technologies.
Laura Roriguez, U. of Stuttgart
Neural-Network-based Fault Classification
In order to reduce the number of defective parts and increase yield, especially in early stages of
production, systematic defects must be identified and corrected as soon as possible. Machine learning
can be taken advantage of due to the enormous amount of data available from test and diagnosis. This
talk presents a technique to raise a warning and prioritize costly physical analysis. Relevant values
related to fault activation are extracted with simulation. Then, a neural network predicts the fault class
to which the underlying defect belongs.
Zahra Paria Najafi Haghi, U. of Stuttgart
Design Optimization and Fault Models in QCA-based Circuits
QCA (Quantum-dot Cellular Automata) is a promising emerging nanotechnology which has been
introduced as an alternative to traditional CMOS VLSI. QCA features such as faster speed, smaller size
and low power consumption have made it so interesting to researchers in recent years. QCA operation
is based on single electron effects in Quantum-dots, to transfer data within its cells. Till now current
CMOS technology has been successful in keeping pace with increasing number of transistors. But as the
size of circuits scales down to the Nano level, some new fundamental challenges will be faced which can
dominate the devices’ performances. Some technology challenges like power consumption due to
leakage current, which is a result of decreasing supply voltage, make transistor-based technologies
resistance to scaling. Quantum effects, non-deterministic behavior of small currents and design
complexity are other challenges which may hold back further progress of microelectronics using
conventional scaling. Thus the need for alternative technologies seems unavoidable.
Nanotechnology is a possible solution for these problems. Some of them are carbon nanotubes,
quantum-dot structures, molecular devices and microfluidic biochips. QCA in an emerging paradigm
which allows an operation in the frequency range of THz (adiabatically), and since quantum-dots can
theoretically be shrunk down to molecular size, has the potential to have an integration density about
900 times more than what we can reach in current transistor-based technologies. In this work we
analyze the design rules in QCA in detail and see different design configurations by giving an example.
The aim is to make some optimizations in configuration and find an efficient way for designing with QCA.
These different configurations may also be used as faulty models in testing a QCA design. On the other
hand, different fault models are discussed by describing the way of fault detection in QCA circuits.
Samir Ben Dodo, KIT
Hardware Security Primitives based on Sprintonics
8
With the growing adoption of the Internet of Things , security is becoming a major challenge especially
for battery operated devices. Spin Transfer Torque – Magnetic RAM technology is a promising candidate
for these low power devices with many beneficial attributes such as non-volatility, no leakage, high
density and CMOS-compatibly. For memory application, this technology is currently facing reliability
challenges with process variations and stochastic switching time. However, from the security
perspective, these random variations can be exploited as hardware security primitives. This presentation
will detail the benefits of process variations for Physical Unclonable Function and the advantages of
stochastic switching for True Random Number Generator. Potential directions to improve these
Spintronics security primitives will be discussed.
4. FAULT TOLERANT DESIGN RELATED TOPICS
Wenjing Rao, ECE department, University of Illinois at Chicago, USA
Modeling and Constructing a guaranteed k-Fault Tolerance System
This work focuses on a system that can be proven to tolerate k faults, based on self-repair using spare
elements. A repair is carried out by a “replacement chain” of Processing Elements (PE’s), starting with a
spare, each taking over the task of the next one, to eventually reaching a faulty PE. Based on a Task-PE
relationship model, a “replacement chain algebra” can be formulated. This makes it possible to calculate
precisely how a repair will affect all the other potential repairs in the future, and to determine whether
the system remains repairable for subsequent faults. Overall, two equivalent conditions (both necessary
and sufficient) can be proven for such a system to be guaranteed k-FT, supporting on-the-fly repair after
every fault occurrence. We further propose a physical implementation of the system, where each PE is
assigned to a Router in the neighborhood. A localized Auxiliary Network is used to provide assignments
flexibilities between each Router and its peripheral PE’s. Faulty PE’s are repaired via spare PE’s in the
array, and replacement chains are implemented by shifting the assignments between Routers and
PE’s. This architecture is isomorphic to the Task-PE model, thus can be designed to deliver a proven
level of fault tolerance properties, while being scalable in hardware and interconnect overheads.
Matthias Kampmann, U. Paderborn
Efficient Output Masking for Faster-than-at-Speed Test
Hidden small delay defects pose a reliability issue since they can sometimes escape even state-of-the-art
timing-aware at-speed tests. Faster-than-at-speed test (FAST) is an approach to overcome these
limitations by overclocking the circuit under test (CUT), thus making even small additional delays
visible. However, FAST also introduces a large number of unknown logic values (X-values) into the test
responses since some outputs might be sampled before they have completed their computation. The rate
of these X-values depends on the target frequency, making conventional X-tolerant compaction
impractical for FAST. To support X-tolerant compaction during FAST, this talk presents and evaluates a
special Design-for-FAST approach that analyzes the topology of the CUT to obtain a scan-chain
configuration exploiting the individual “X-profiles“ of the scan-flip- flops (SFFs). This allows to
implement a very simple and efficient X-masking strategy to drastically reduce the amount of X-values
arriving at the compaction circuit. Furthermore, the presented SFF clustering method is easily
integrateable into existing commercial synthesis tools.
Simulation results indicate that the proposed Design-for-FAST approach indeed reduces the X- values to
quite large extends but also requires to trade of the reduction in X-values against the fault efficiency.
Special algorithms to generate the mask data are presented to allow fine-grained control over fault
efficiency, reduction in X-values and mask data overhead. Overall, this talk shows that the presented
approach should relieve the requirements of the compaction circuit significantly.
Florian Negebauer – U. Passau
Framework for quantifying and managing accuracy in stochastic circuit design
Stochastic circuits (SCs) offer tremendous area- and power-consumption benefits at the expense of
computational inaccuracies. Managing accuracy is a central problem in SC design and has no counterpart
in conventional circuit synthesis. It raises a basic question: how to build a systematic design flow for
stochastic circuits? We present, for the first time, a systematic design approach to control the accuracy
of SCs and balance it against other design parameters. We express the (in)accuracy of a circuit processing
9
n-bit stochastic numbers by the numerical deviation of the computed value from the expected result, in
conjunction with a confidence level. Using the theory of Monte Carlo simulation, we derive expressions
for the stochastic number length required for a desired level of accuracy, or vice versa. We discuss the
integration of the theory into a design framework that is applicable to both combinational and sequential
SCs. We show that for combinational SCs, accuracy is independent of the circuit’s size or complexity, a
surprising result. We also show how the analysis can identify subtle errors in both combinational and
sequential designs.
Dennis Weller, KIT
Robust Printed Electronics Circuit Design
Nowadays, printed electronics are gaining more and more attention as an advantageous technology
deployed for smart sensors, "Internet of Things" (IoT), wearables and other domains. It enables the
production of electrical circuits with low costs and printable on flexible substrates without the need for
clean rooms in contrast to silicon technologies. However, there are still some challenges to be tackled,
like the comparable big feature size, low printing accuracy and poor printing quality using state of the
art ink-jet printers. In this talk, we overview the development of printed electronics based on electrolytegated inorganic materials which provide high mobility and low voltage operation, which is very
promising in IoT applications. Furthermore, we provide some examples how increased reliability of
printed designs can be achieved.
10
5. TEST AT SPEED TEST RELATED TOPICS
Chang Liu, U. of Stuttgart
Aging Monitor Reuse for Small Delay Fault Testing
Small delay faults receive more and more attention, since they may indicate a circuit reliability
marginality even if they do not violate the timing at the time of production. At-speed test and fasterthan-at-speed test (FAST) are rather expensive tasks to test for such faults.
The paper at hand avoids complex on-chip structures or expensive high-speed ATE for test response
evaluation if aging monitors which are integrated into the device under test anyway are reused. The
main challenge in reusing aging monitors for FAST consists in possible false alerts at higher frequencies.
While a particular test vector pair makes a delay fault observable at one monitor, it may also exceed the
time slack in the fault-free case at a different monitor which has to be masked. Therefore, a
multidimensional optimizing problem has to be solved for minimizing the masking overhead, the
number of test vectors and the number frequencies while maximizing delay fault coverage.
Marco RESTIFO, Politecnico di Torino
Advanced Functional Schema for optimized Test and Stress of Automotive SoC
Thermal and electrical stress phases are commonly applied to automotive devices at the end of
manufacturing test to give rise to early life latent failures. This paper proposes a new methodology to
optimize the stress procedures during the Burn-In phase. In the proposed method, stress of CPU, RAM
memory and FLASH memory are run in parallel using DMA and CACHE interventions. In the talk I will
report some experimental results gathered in an automotive microcontroller, with a comparison
between traditional and parallelized burn-in stress techniques.
Alexander Sprenger, U. Paderborn
X-Reduction using Stochastic Compaction for FAST
Test response compaction is a major challenge in faster-than-at-speed-test (FAST). As the test is run at
a higher clock rates, the signal values on long paths may not have stabilized at the respective observation
times. This results in a larger number of unknown logic values (X-values) to be handled by the
compaction scheme. Moreover, FAST typically uses several different frequencies, which leads to varying
X-rates during the test. Therefore, an X-tolerant compaction method specifically tailored to FAST is
needed.
It has been shown in the literature that a stochastic X-Compact scheme can reduce the number of X’s
while the fault efficiency is kept high. However, this requires a constant X-rate for the scan slices entering
the compactor. This presentation describes a solution for the general case. The stochastic compactor is
divided into several smaller compactors and the optimal assignment of scan chains to compactors is
determined by a clustering technique. For a “good” cluster the X-Rate at the inputs of the compactor
should vary as little as possible. This problem is NP-complete. This talk will focus on finding scan chain
clusters using Heuristics, for the stochastic X-compact scheme and showing results for the compaction
scheme.
Felix Neubauer: U. Freiburg
iSAT3: Accurate Reasoning for Floating-Point Arithmetic
The process of testing typically includes a modeling step of the system under test. Due to the different
types of systems - analog, digital or mixed-signal - this process can be challenging. Analog systems
normally work with continous (real) values while digital systems - e.g. modern computers - use Boolean
values and represent numbers with integer or floating-point arithmetic. Mixed-signal systems on the
other hand include analog as well as digital components. Thus the support of these different domains is
mandatory when they are modeled for testing purposes and the employed tool chain has to support
these domains. iSAT3 is an SMT solver, which supports a great variaty of different domains: Boolean,
integer and real. Additionally, iSAT3 was recently extended to be able to reason in the floating-point
11
domain. This talk presents the general workflow of iSAT3, the challenges of the floating-point domain as
well as an application in the field of dead code detection. Furthermore possible relations to the
testingfield are discussed.
12
6. MISCELLANEOUS TEST ISSUES
Stefan Holst, Assistant Professor, Kyushu Institute of Technology
Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors
Excessive IR-drop during scan shift can corrupt test data due to hold-time violations.
We introduce new methods to assess the risk of corruption at each scan cycle and cell, and to handle
the problem by test data manipulation and masking.
Marcello Traiola, LIRMM
Test of Approximate Circuits
In the recent years Approximate Computing (AC) has emerged as new paradigm for energy efficient
design of Integrated Circuits (ICs). It addresses the problem of maintaining reliability and thus coping
with run-time errors exploiting an acceptable amount of overheads in terms of area, performances and
energy consumption. This work starts from the hypothesis that AC-based systems can intrinsically
accept the presence of faulty hardware (i.e., hardware that can produce errors). This paradigm is also
called “computing on unreliable hardware”. The hardware- induced errors have to be analyzed to
determine their propagation through the system layers and eventually determining their impact on the
final application. In other words, an AC-based system does not need to be built using defect-free ICs.
Under this assumption, we can relax test and reliability constraints of the manufactured ICs. One of the
ways to achieve this goal is to test only for a subset of faults instead of targeting all possible faults. In this
way, we can reduce the manufacturing cost since we eventually reduce the number test patterns and
thus the test time. We call this approach Approximate Test. The main advantage is the fact that we do not
need a prior knowledge of the workload (i.e., we are application independent). Therefore, the proposed
approach can be applied to any kind of IC, reducing the test time and increasing the yield. We present
preliminary results on a simple case study. The main goal is to show that by letting some faults
undetected we can save test time without having a huge impact on the application quality.
Pascal Raiola, U Freiburg
SAT-based Combinational and Sequential Dependency Computation
We present an algorithm for computing both functional dependency and unateness of combinational
and sequential Boolean functions represented as logic networks. The algorithm uses SAT-based
techniques from Combinational Equivalence Checking (CEC) and Automatic Test Pattern Generation
(ATPG) to compute the dependency matrix of multi-output Boolean functions. Additionally, the classical
dependency definitions are extended to sequential functions and a fast approximation is presented to
efficiently yield a sequential dependency matrix. Experiments show the applicability of the methods and
the improved robustness compared to existing approaches.
13